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2541626c |
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01-Jun-2022 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/acr: use common falcon HS FW code for ACR FWs Adds context binding and support for FWs with a bootloader to the code that was added to load VPR scrubber HS binaries, and ports ACR over to using all of it. - gv100 split from gp108 to handle FW exit status differences Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
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f15cde64 |
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01-Jun-2022 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/flcn: rework falcon reset Mostly preparation to fit in Ampere changes, but should result in reset sequences a lot closer to RM's, and perhaps help out with the issues we sometimes see reported in this area. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
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ea0b20d3 |
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01-Jun-2022 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/flcn: remove unused functions Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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bc3cfd18 |
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14-Jan-2020 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/flcn: specify EMEM address from subdev Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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ca3190e3 |
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14-Jan-2020 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/flcn: move bind_context WAR out of common code Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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fb0a5bbe |
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14-Jan-2020 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/flcn: specify FBIF offset from subdev Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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a128bbfa |
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14-Jan-2020 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/flcn: export existing funcs These will be used in upcoming commits which will provide more customisation. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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5210e967 |
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01-Jul-2019 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/flcn/gp102-: improve implementation of bind_context() on SEC2/GSP Fixes various issues encountered while attempting to initialise ACR. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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d30af7ce |
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31-Oct-2017 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/mmu: handle instance block setup We previously required each VMM user to allocate their own page directory and fill in the instance block themselves. It makes more sense to handle this in a common location. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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6ac2cc20 |
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13-Feb-2017 |
Alexandre Courbot <acourbot@nvidia.com> |
drm/nouveau/falcon: support for EMEM On SEC, DMEM is unaccessible by the CPU when the falcon is running in LS mode. This makes communication with the firmware using DMEM impossible. For this purpose, a new kind of memory (EMEM) has been added. It works similarly to DMEM, with the difference that its address space starts at 0x1000000. For this reason, it makes sense to treat it like a special case of DMEM. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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cfd044b0 |
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26-Jan-2017 |
Alexandre Courbot <acourbot@nvidia.com> |
drm/nouveau/falcon: fix base address of FBIF registers All falcons have their FBIF registers starting at offset 0x600, with the exception of the PMU and NVENC engines. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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65d9376b |
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25-Jan-2017 |
Alexandre Courbot <acourbot@nvidia.com> |
drm/nouveau/falcon: use NXTCTX register instead of NEW_INSTBLK Both registers allow to bind a new context, but NXTCTX will work on all falcons, while legacy NEW_INSTBLK is reserved to PMU. After setting NXTCTX we trigger a context switch by writing 0x090 and 0x0a4. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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17c602e3 |
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13-Feb-2017 |
Alexandre Courbot <acourbot@nvidia.com> |
drm/nouveau/falcon: fix IMEM port access All IMEM registers are duplicated per port. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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ca179c85 |
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13-Feb-2017 |
Alexandre Courbot <acourbot@nvidia.com> |
drm/nouveau/falcon: fix port offset for DMEM register DMEM registers are replicated with a stride of 8 bytes. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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6bd4b523 |
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25-Jan-2017 |
Alexandre Courbot <acourbot@nvidia.com> |
drm/nouveau/falcon: add missing context binding memory target This is not used currently, but is added for the sake of completeness. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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d2ee3605 |
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09-May-2016 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/core/memory: distinguish between coherent/non-coherent targets Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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31214108 |
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13-Dec-2016 |
Alexandre Courbot <acourbot@nvidia.com> |
drm/nouveau/core: add falcon library functions Falcon processors are used in various places of GPU chips. Although there exist different versions of the falcon, and some variants exist, the base set of actions performed on them is the same, which results in lots of duplicated code. This patch consolidates the current nvkm_falcon structure and extends it with the following features: * Ability for an engine to obtain and later release a given falcon, * Abstractions for basic operations (IMEM/DMEM access, start, etc) * Abstractions for secure operations if a falcon is secure Abstractions make it easy to e.g. start a falcon, without having to care about its details. For instance, falcons in secure mode need to be started by writing to a different register. Right now the abstractions variants only cover secure vs. non-secure falcon, but more will come as e.g. SEC2 support is added. This is still a WIP as other functions previously done by engine/falcon.c need to be reimplemented. However this first step allows to keep things simple and to discuss basic design. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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