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830531e9 |
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18-Sep-2023 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/gsp/r535: add interrupt handling Fetches the interrupt table from RM, and hooks up the GSP interrupt handler to message queue processing to catch async messages. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230918202149.4343-36-skeggsb@gmail.com
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176fdcbd |
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18-Sep-2023 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/gsp/r535: add support for booting GSP-RM This commit adds the initial code needed to boot the GSP-RM firmware provided by NVIDIA, bringing with it the beginnings of Ada support. Until it's had more testing and time to bake, support is disabled by default (except on Ada). GSP-RM usage can be enabled by passing the "config=NvGspRm=1" module option. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230918202149.4343-33-skeggsb@gmail.com
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a51c69ee |
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01-Jun-2022 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/fb/ga102: load and boot VPR scrubber FW v2. fixup for ga103 early merge Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Gourav Samaiya <gsamaiya@nvidia.com>
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2541626c |
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01-Jun-2022 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/acr: use common falcon HS FW code for ACR FWs Adds context binding and support for FWs with a bootloader to the code that was added to load VPR scrubber HS binaries, and ports ACR over to using all of it. - gv100 split from gp108 to handle FW exit status differences Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
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0e44c217 |
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01-Jun-2022 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/flcn: new code to load+boot simple HS FWs (VPR scrubber) Adds the start of common interfaces to load and boot the HS binaries provided by NVIDIA that enable the usage of GR. ACR already handles most of this, but it's very much tied into ACR's init process, and there's other code that could benefit from reusing a lot of this stuff too (ie. VBIOS DEVINIT/PreOS, VPR scrubber). The VPR scrubber code is fairly independent, and a good first target. - adds better debug output to fw loading process, to ease bring-up/debug v2: - whitespace, 0->false Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
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f15cde64 |
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01-Jun-2022 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/flcn: rework falcon reset Mostly preparation to fit in Ampere changes, but should result in reset sequences a lot closer to RM's, and perhaps help out with the issues we sometimes see reported in this area. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
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a9d90860 |
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01-Jun-2022 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/pmu/gm20b,gp10b: boot RTOS from PMU init Cleanup before falcon changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
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ea0b20d3 |
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01-Jun-2022 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/flcn: remove unused functions Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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4cdd2450 |
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24-Feb-2021 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/pmu/gm200-: use alternate falcon reset sequence Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Karol Herbst <kherbst@redhat.com> Signed-off-by: Karol Herbst <kherbst@redhat.com> Link: https://gitlab.freedesktop.org/drm/nouveau/-/merge_requests/10
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b7da823a |
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05-Feb-2021 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/falcon: use split type+inst when looking up PRI addr Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
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6997ea13 |
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05-Feb-2021 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/mc: use split type+inst in device reset APIs Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
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9c28abb7 |
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24-Jul-2020 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/subdev: store full subdev name in struct Much easier to store this to avoid having to reconstruct a string for a specific subdev, taking into account whether it's instanced or not. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
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e938c4e7 |
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14-Jan-2020 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/flcn: specify debug/production register offset from subdev Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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bc3cfd18 |
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14-Jan-2020 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/flcn: specify EMEM address from subdev Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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a128bbfa |
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14-Jan-2020 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/flcn: export existing funcs These will be used in upcoming commits which will provide more customisation. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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de048192 |
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14-Jan-2020 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/flcn: fetch PRI address from TOP if not provided by constructor Shortcut to avoid each subdev having to do this itself. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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5a4b98cd |
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14-Jan-2020 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/flcn: move fetching of configuration until first use We want to be able to register falcons with ACR during the constructor for the subdev it belongs to, however, we may not have access to the falcon's registers prior to DEVINIT. Delay touching registers until the first time the falcon is acquired. This may temporarily break secboot on non-production boards due to not being able to determine whether the falcon is in debug or production mode, the new ACR subdev will not have this issue, and it's not a use-case that's terribly important for bisectability. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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2944b19b |
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12-Feb-2019 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/gsp/gv100-: instantiate GSP falcon We need this for Turing ACR, but it's present from Volta onwards. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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936a1678 |
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10-Dec-2018 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/core: support multiple nvdec instances Turing GPUs can have more than one. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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d30af7ce |
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31-Oct-2017 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/mmu: handle instance block setup We previously required each VMM user to allocate their own page directory and fill in the instance block themselves. It makes more sense to handle this in a common location. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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6ac2cc20 |
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13-Feb-2017 |
Alexandre Courbot <acourbot@nvidia.com> |
drm/nouveau/falcon: support for EMEM On SEC, DMEM is unaccessible by the CPU when the falcon is running in LS mode. This makes communication with the firmware using DMEM impossible. For this purpose, a new kind of memory (EMEM) has been added. It works similarly to DMEM, with the difference that its address space starts at 0x1000000. For this reason, it makes sense to treat it like a special case of DMEM. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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ad147b7f |
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22-Feb-2017 |
Alexandre Courbot <acourbot@nvidia.com> |
drm/nouveau/falcon: better detection of debug register Not all falcons have a debug register, and it is not always found at the same offset. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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9e439757 |
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22-Feb-2017 |
Alexandre Courbot <acourbot@nvidia.com> |
drm/nouveau/falcon: delay construction of falcons to oneinit() Reading registers at device construction time can be harmful, as there is no guarantee the underlying engine will be up, or in its runtime configuration. Defer register reading to the oneinit() hook and update users accordingly. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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e444de56 |
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18-Jan-2017 |
Alexandre Courbot <acourbot@nvidia.com> |
drm/nouveau/falcon: protect against concurrent DMEM accesses The falcon library may be used concurrently, especially after the introduction of the msgqueue interface. Make it safe to use it that way. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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31214108 |
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13-Dec-2016 |
Alexandre Courbot <acourbot@nvidia.com> |
drm/nouveau/core: add falcon library functions Falcon processors are used in various places of GPU chips. Although there exist different versions of the falcon, and some variants exist, the base set of actions performed on them is the same, which results in lots of duplicated code. This patch consolidates the current nvkm_falcon structure and extends it with the following features: * Ability for an engine to obtain and later release a given falcon, * Abstractions for basic operations (IMEM/DMEM access, start, etc) * Abstractions for secure operations if a falcon is secure Abstractions make it easy to e.g. start a falcon, without having to care about its details. For instance, falcons in secure mode need to be started by writing to a different register. Right now the abstractions variants only cover secure vs. non-secure falcon, but more will come as e.g. SEC2 support is added. This is still a WIP as other functions previously done by engine/falcon.c need to be reimplemented. However this first step allows to keep things simple and to discuss basic design. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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