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727fd72f |
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01-Jun-2022 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/intr: add shared interrupt plumbing between pci/tegra Unifies the handling between PCI-based and Tegra GPUs, and makes more explicit/obvious where device interrupts can be expected. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
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#
1a3b1ea1 |
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19-May-2022 |
Guo Zhengkui <guozhengkui@vivo.com> |
drm/nouveau/tegra: remove needless NULL check There has already been NULL check in clk_prepare_enable() and clk_disable_unprepare(), so remove needless NULL check before calling them. Signed-off-by: Guo Zhengkui <guozhengkui@vivo.com> Reviewed-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Lyude Paul <lyude@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220519072950.128268-1-guozhengkui@vivo.com
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#
87fd2b09 |
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05-Apr-2022 |
Robin Murphy <robin.murphy@arm.com> |
drm/nouveau/tegra: Stop using iommu_present() Even if some IOMMU has registered itself on the platform "bus", that doesn't necessarily mean it provides translation for the device we care about. Replace iommu_present() with a more appropriate check. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Reviewed-by: Lyude Paul <lyude@redhat.com> [added cc for stable] Signed-off-by: Lyude Paul <lyude@redhat.com> Cc: stable@vger.kernel.org # v5.0+ Link: https://patchwork.freedesktop.org/patch/msgid/70d40ea441da3663c2824d54102b471e9a621f8a.1649168494.git.robin.murphy@arm.com
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#
7eef7f67 |
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15-Feb-2022 |
Lu Baolu <baolu.lu@linux.intel.com> |
drm/nouveau/device: Get right pgsize_bitmap of iommu_domain The supported page sizes of an iommu_domain are saved in the pgsize_bitmap field. Retrieve the value from the right place. Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> Reviewed-by: Robin Murphy <robin.murphy@arm.com> Link: https://lore.kernel.org/r/20211218074546.1772553-1-baolu.lu@linux.intel.com Reviewed-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> Link: https://lore.kernel.org/r/20220216025249.3459465-7-baolu.lu@linux.intel.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
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#
fc12262b |
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09-Dec-2019 |
Thierry Reding <treding@nvidia.com> |
drm/nouveau/tegra: Set clock rate if not set If the GPU clock has not had a rate set, initialize it to the maximum clock rate to make sure it does run. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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b0b651ae |
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09-Dec-2019 |
Thierry Reding <treding@nvidia.com> |
drm/nouveau/tegra: Avoid pulsing reset twice When the GPU powergate is controlled by a generic power domain provider, the reset will automatically be asserted and deasserted as part of the power-ungating procedure. On some Jetson TX2 boards, doing an additional assert and deassert of the GPU outside of the power-ungate procedure can cause the GPU to go into a bad state where the memory interface can no longer access system memory. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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#
b59fb482 |
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30-May-2018 |
Thierry Reding <treding@nvidia.com> |
drm/nouveau: tegra: Detach from ARM DMA/IOMMU mapping Depending on the kernel configuration, early ARM architecture setup code may have attached the GPU to a DMA/IOMMU mapping that transparently uses the IOMMU to back the DMA API. Tegra requires special handling for IOMMU backed buffers (a special bit in the GPU's MMU page tables indicates the memory path to take: via the SMMU or directly to the memory controller). Transparently backing DMA memory with an IOMMU prevents Nouveau from properly handling such memory accesses and causes memory access faults. As a side-note: buffers other than those allocated in instance memory don't need to be physically contiguous from the GPU's perspective since the GPU can map them into contiguous buffers using its own MMU. Mapping these buffers through the IOMMU is unnecessary and will even lead to performance degradation because of the additional translation. One exception to this are compressible buffers which need large pages. In order to enable these large pages, multiple small pages will have to be combined into one large (I/O virtually contiguous) mapping via the IOMMU. However, that is a topic outside the scope of this fix and isn't currently supported. An implementation will want to explicitly create these large pages in the Nouveau driver, so detaching from a DMA/IOMMU mapping would still be required. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Robin Murphy <robin.murphy@arm.com> Tested-by: Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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325a7282 |
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31-Oct-2017 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau: consolidate handling of dma mask Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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#
4d058fab |
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31-Oct-2017 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/core/mm: have users explicitly define heap identifiers Different sections of VRAM may have different properties (ie. can't be used for compression/display, can't be mapped, etc). We currently already support this, but it's a bit magic. This change makes it more obvious where we're allocating from. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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f5a5b523 |
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31-Oct-2017 |
Ben Skeggs <bskeggs@redhat.com> |
remove some useless semicolons Reported-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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#
fcd504e3 |
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09-Jun-2017 |
Mikko Perttunen <mperttunen@nvidia.com> |
drm/nouveau/tegra: Don't leave GPU in reset On Tegra186 systems with certain firmware revisions, leaving the GPU in reset can cause a hang. To prevent this, don't leave the GPU in reset. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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b1df2425 |
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09-Jun-2017 |
Mikko Perttunen <mperttunen@nvidia.com> |
drm/nouveau/tegra: Skip manual unpowergating when not necessary On Tegra186, powergating is handled by the BPMP power domain provider and the "legacy" powergating API is not available. Therefore skip these calls if we are attached to a power domain. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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e6e1817a |
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29-Mar-2017 |
Alexandre Courbot <acourbot@nvidia.com> |
drm/nouveau/platform: make VDD regulator optional GP10B's power is managed by generic PM domains, so it does not require a VDD regulator. Add this option into the chip function structure. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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91cf301f |
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31-Oct-2016 |
Christophe JAILLET <christophe.jaillet@wanadoo.fr> |
drm/nouveau/tegra: Fix error handling 'iommu_domain_alloc()' returns NULL in case of error, not an error pointer. So test it accordingly. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Reviewed-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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#
bad3d80f |
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17-Sep-2016 |
Karol Herbst <karolherbst@gmail.com> |
drm/nouveau: Revert "bus: remove cpu_coherent flag" This reverts commit aff51175cdbf345740ec9203eff88e772af88059. The commit caused fence timeouts within nvc0_screen_destroy and most likely other places as well. The most obvious effect is, that userspace processes take minutes to actually quit. Signed-off-by: Karol Herbst <karolherbst@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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aff51175 |
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13-Jul-2016 |
Alexandre Courbot <gnurou@gmail.com> |
drm/nouveau/bus: remove cpu_coherent flag This flag's only remaining function is to ignore the uncached flag for BOs on coherent architectures. However the reason for allocating an object uncache on a non-coherent architecture (namely because the cost of doing explicit flushes/ invalidations is higher than the benefit of caching the data because accesses are few and far between) should also apply on architectures for which coherency is maintained implicitly. Thus allocate coherent objects as uncached on all architectures. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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d2680907 |
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01-Jun-2016 |
Alexandre Courbot <acourbot@nvidia.com> |
drm/nouveau/tegra: fetch gpu_speedo_id The GPU speedo ID is required to select the right clk/volt parameters on GM20B. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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d3981190 |
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29-May-2016 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/mc: take nvkm_device as argument to public functions Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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#
34440ed6 |
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31-Mar-2016 |
Alexandre Courbot <acourbot@nvidia.com> |
drm/nouveau/tegra: acquire and enable reference clock if needed GM20B requires an extra clock compared to GK20A. Add that information into the platform data and acquire and enable this clock if necessary. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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9d0394c6 |
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24-Feb-2016 |
Alexandre Courbot <acourbot@nvidia.com> |
drm/nouveau/instmem/gk20a: set DMA mask early DMA mask is typically set in nouveau_ttm_init(), but this function is called late during initialization and GK20A's instmem will have called DMA functions before this happens. Having a wrongly set DMA mask can result in the use of unneeded bounce buffers. Set it early to avoid this. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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1b82111f |
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27-Jan-2016 |
Alexandre Courbot <acourbot@nvidia.com> |
drm/nouveau/device/tegra: fix uninitialized IRQ number nvkm_device_tegra_new initializes the irq member of the Tegra device to -1 in order to signal that it is uninitialized. However, nvkm_device_tegra_fini tests it against 0 to check whether an IRQ has been allocated or not. This leads to free_irq being called on -1 during device initialization. Fix this by using 0 as the uninitialized value everywhere. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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870571a5 |
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24-Feb-2016 |
Thierry Reding <treding@nvidia.com> |
drm/nouveau: platform: Fix deferred probe The error cleanup paths aren't quite correct and will crash upon deferred probe. Cc: stable@vger.kernel.org # v4.3+ Reviewed-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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#
e396ecd1 |
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04-Sep-2015 |
Alexandre Courbot <acourbot@nvidia.com> |
drm/nouveau/platform: allow to specify the IOMMU bit Current Tegra code taking advantage of the IOMMU assumes a hardcoded value for the IOMMU bit. Make it a platform property instead for flexibility. v2 (Ben Skeggs): remove nvkm dependence on drm structures Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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43a70661 |
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19-Aug-2015 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/tegra: merge platform setup from nouveau drm The copyright header in nvkm/engine/device/platform.c has been replaced with the NVIDIA one from drm/nouveau_platform.c, as most of the actual code is now theirs. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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26c9e8ef |
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19-Aug-2015 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/device: remove pci/platform_device from common struct Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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7e8820fe |
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19-Aug-2015 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/device: cleaner abstraction for device resource functions Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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2b700825 |
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19-Aug-2015 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/mc: move device irq handling to platform-specific code Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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#
7974dd1b |
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19-Aug-2015 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau/device: separate construction of pci/tegra devices Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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