#
e3b1f369 |
|
20-Feb-2024 |
Abel Vesa <abel.vesa@linaro.org> |
drm/msm/dpu: Add X1E80100 support Add definitions for the display hardware used on the Qualcomm X1E80100 platform. Co-developed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/579075/ Link: https://lore.kernel.org/r/20240220-x1e80100-display-v4-4-971afd9de861@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
7204df5e |
|
08-Feb-2024 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: add support for SDM660 and SDM630 platforms Bring in hardware support for the SDM660 and SDM630 platforms, which belong to the same DPU generation as MSM8998. Note, by default these platforms are still handled by the MDP5 driver unless the `msm.prefer_mdp5=false' parameter is provided. Co-developed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/577507/ Link: https://lore.kernel.org/r/20240208-fd-migrate-mdp5-v4-4-945d08ef3fa8@linaro.org
|
#
8c16b988 |
|
12-Dec-2023 |
Abhinav Kumar <quic_abhinavk@quicinc.com> |
drm/msm/dpu: introduce separate wb2_format arrays for rgb and yuv Lets rename the existing wb2_formats array wb2_formats_rgb to indicate that it has only RGB formats and can be used on any chipset having a WB block. Introduce a new wb2_formats_rgb_yuv array to the catalog to indicate support for YUV formats to writeback in addition to RGB. Chipsets which have support for CDM block will use the newly added wb2_formats_rgb_yuv array. changes in v3: - change type of wb2_formats_rgb/wb2_formats_rgb_yuv to u32 to fix checkpatch warnings Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/571837/ Link: https://lore.kernel.org/r/20231212205254.12422-15-quic_abhinavk@quicinc.com [DB: fixed newer catalog entries] Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
a5ec9a44 |
|
12-Dec-2023 |
Abhinav Kumar <quic_abhinavk@quicinc.com> |
drm/msm/dpu: add cdm blocks to sc7280 dpu_hw_catalog Add CDM blocks to the sc7280 dpu_hw_catalog to support YUV format output from writeback block. changes in v3: - change the comment from sub-blk to clk for CDM changes in v2: - remove explicit zero assignment for features - move sc7280_cdm to dpu_hw_catalog from the sc7280 catalog file as its definition can be re-used Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/571818/ Link: https://lore.kernel.org/r/20231212205254.12422-6-quic_abhinavk@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
b94747f7 |
|
30-Oct-2023 |
Neil Armstrong <neil.armstrong@linaro.org> |
drm/msm/dpu: add support for SM8650 DPU Add DPU version 10.0 support for the SM8650 platform. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/564975/ Link: https://lore.kernel.org/r/20231030-topic-sm8650-upstream-mdss-v2-5-43f1887c82b8@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
e140b7e4 |
|
16-Oct-2023 |
Richard Acayan <mailingradian@gmail.com> |
drm/msm/dpu: Add hw revision 4.1 (SDM670) The Snapdragon 670 uses similar clocks (with one frequency added) to the Snapdragon 845 but reports DPU revision 4.1. Add support for this DPU with configuration from the Pixel 3a downstream kernel. Since revision 4.0 is SDM845, reuse some configuration from its catalog entry. Link: https://android.googlesource.com/kernel/msm/+/368478b0ae76566927a2769a2bf24dfe7f38bb78/arch/arm64/boot/dts/qcom/sdm670-sde.dtsi Signed-off-by: Richard Acayan <mailingradian@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/562965/ Link: https://lore.kernel.org/r/20231017021805.1083350-14-mailingradian@gmail.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
223fb06f |
|
01-Dec-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/gpu: drop duplicating VIG feature masks After folding QSEED3LITE and QSEED4 feature bits into QSEED3_COMPATIBLE several VIG feature masks became equal. Drop these duplicates. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/570107/ Link: https://lore.kernel.org/r/20231201234234.2065610-11-dmitry.baryshkov@linaro.org
|
#
193838ac |
|
01-Dec-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: merge DPU_SSPP_SCALER_QSEED3, QSEED3LITE, QSEED4 Three different features, DPU_SSPP_SCALER_QSEED3, QSEED3LITE and QSEED4 are all related to different versions of the same HW scaling block. Corresponding driver parts use scaler_blk.version to identify the correct way to program the hardware. In order to simplify the driver codepath, merge these three feature bits into QSEED3_COMPATIBLE bin. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/570114/ Link: https://lore.kernel.org/r/20231201234234.2065610-10-dmitry.baryshkov@linaro.org
|
#
0fd20541 |
|
01-Dec-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: deduplicate some (most) of SSPP sub-blocks As we have dropped the variadic parts of SSPP sub-blocks declarations, deduplicate them now, reducing memory cruft. Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/570112/ Link: https://lore.kernel.org/r/20231201234234.2065610-7-dmitry.baryshkov@linaro.org
|
#
01fc6c01 |
|
01-Dec-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: drop the `smart_dma_priority' field from struct dpu_sspp_sub_blks In preparation to deduplicating SSPP subblocks, drop the (unused) `smart_dma_priority' field from struct dpu_sspp_sub_blks. If it is needed later (e.g. for SmartDMA v1), it should be added to the SSPP declarations themselves. Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/570103/ Link: https://lore.kernel.org/r/20231201234234.2065610-6-dmitry.baryshkov@linaro.org
|
#
6876059d |
|
01-Dec-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: drop the `id' field from DPU_HW_SUBBLK_INFO The field `id' is not used for subblocks. The handling code usually knows, which sub-block it is now looking at. Drop the field completely. Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/570100/ Link: https://lore.kernel.org/r/20231201234234.2065610-5-dmitry.baryshkov@linaro.org
|
#
46b1f1b8 |
|
01-Dec-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: populate SSPP scaler block version The function _dpu_hw_sspp_setup_scaler3() passes and dpu_hw_setup_scaler3() uses scaler_blk.version to determine in which way the scaler (QSEED3) block should be programmed. However up to now we were not setting this field. Set it now, splitting the vig_sblk data which has different version fields. Reported-by: Marijn Suijten <marijn.suijten@somainline.org> Fixes: 9b6f4fedaac2 ("drm/msm/dpu: Add SM6125 support") Fixes: 27f0df03f3ff ("drm/msm/dpu: Add SM6375 support") Fixes: 3186acba5cdc ("drm/msm/dpu: Add SM6350 support") Fixes: efcd0107727c ("drm/msm/dpu: add support for SM8550") Fixes: 4a352c2fc15a ("drm/msm/dpu: Introduce SC8280XP") Fixes: 0e91bcbb0016 ("drm/msm/dpu: Add SM8350 to hw catalog") Fixes: 100d7ef6995d ("drm/msm/dpu: add support for SM8450") Fixes: 3581b7062cec ("drm/msm/disp/dpu1: add support for display on SM6115") Fixes: dabfdd89eaa9 ("drm/msm/disp/dpu1: add inline rotation support for sc7280") Fixes: f3af2d6ee9ab ("drm/msm/dpu: Add SC8180x to hw catalog") Fixes: 94391a14fc27 ("drm/msm/dpu1: Add MSM8998 to hw catalog") Fixes: af776a3e1c30 ("drm/msm/dpu: add SM8250 to hw catalog") Fixes: 386fced3f76f ("drm/msm/dpu: add SM8150 to hw catalog") Fixes: b75ab05a3479 ("msm:disp:dpu1: add scaler support on SC7180 display") Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/570098/ Link: https://lore.kernel.org/r/20231201234234.2065610-2-dmitry.baryshkov@linaro.org
|
#
e48954ef |
|
03-Sep-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: drop DPU_INTF_TE feature flag Replace the only user of the DPU_INTF_TE feature flag with the direct DPU version comparison. Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Patchwork: https://patchwork.freedesktop.org/patch/555540/ Link: https://lore.kernel.org/r/20230904020454.2945667-7-dmitry.baryshkov@linaro.org
|
#
e5b1ec80 |
|
03-Sep-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: drop the DPU_PINGPONG_TE flag The DPU_PINGPONG_TE flag became unused, we can drop it now. Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Patchwork: https://patchwork.freedesktop.org/patch/555542/ Link: https://lore.kernel.org/r/20230904020454.2945667-4-dmitry.baryshkov@linaro.org
|
#
57a1ca6c |
|
02-Aug-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: fix DSC 1.2 enc subblock length Both struct dpu_dsc_sub_blks instances declare enc subblock length to be 0x100, while the actual length is 0x9c (last register having offset 0x98). Reduce subblock length to remove the empty register space from being dumped. Fixes: 0d1b10c63346 ("drm/msm/dpu: add DSC 1.2 hw blocks for relevant chipsets") Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/550999/ Link: https://lore.kernel.org/r/20230802183655.4188640-2-dmitry.baryshkov@linaro.org
|
#
42d0d253 |
|
02-Aug-2023 |
Jonathan Marek <jonathan@marek.ca> |
drm/msm/dpu: increase memtype count to 16 for sm8550 sm8550 has 16 vbif clients. This fixes the extra 2 clients (DMA4/DMA5) not having their memtype initialized. This fixes DMA4/DMA5 planes not displaying correctly. Fixes: efcd0107727c ("drm/msm/dpu: add support for SM8550") Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Patchwork: https://patchwork.freedesktop.org/patch/550968/ Link: https://lore.kernel.org/r/20230802134900.30435-1-jonathan@marek.ca [DB: fixed the Fixes tag] Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
9b6f4fed |
|
23-Jul-2023 |
Marijn Suijten <marijn.suijten@somainline.org> |
drm/msm/dpu: Add SM6125 support Add definitions for the display hardware used on the Qualcomm SM6125 platform. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Patchwork: https://patchwork.freedesktop.org/patch/548978/ Link: https://lore.kernel.org/r/20230723-sm6125-dpu-v4-10-a3f287dd6c07@somainline.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
78145228 |
|
11-Jul-2023 |
Abhinav Kumar <quic_abhinavk@quicinc.com> |
drm/msm/dpu: drop DPU_INTF_DATA_COMPRESS from dpu catalog Now that all usages of DPU_INTF_DATA_COMPRESS have been replaced with the dpu core's major revision lets drop DPU_INTF_DATA_COMPRESS from the catalog completely. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/546808/ Link: https://lore.kernel.org/r/20230712012003.2212-6-quic_abhinavk@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
274909a8 |
|
07-Jul-2023 |
Ryan McCann <quic_rmccann@quicinc.com> |
drm/msm/dpu: Remove redundant prefix/suffix in name of sub-blocks For a device core dump, the registers of sub-blocks are printed under a title formatted as <mainBlkName_sblkName>. For example, the csc sub-block for an SSPP main block "sspp_0" would be printed "sspp_0_sspp_csc0". The title is clearly redundant due to the duplicate "sspp" and "0" that exist in both the mainBlkName and sblkName. To eliminate this redundancy, remove the secondary "sspp" and "0" that exist in the sub-block name by elimanting the "sspp_" prefix and the concatenation of "num" that results in the redundant "0" suffix. Remove num parameter altogether from relevant macros as a consequence of it no longer being used. Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Ryan McCann <quic_rmccann@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/546198/ Link: https://lore.kernel.org/r/20230622-devcoredump_patch-v5-4-67e8b66c4723@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
46998bf8 |
|
07-Jul-2023 |
Ryan McCann <quic_rmccann@quicinc.com> |
drm/msm/dpu: Define names for unnamed sblks Some sub-blocks in the hw catalog have not been given a name, so when the registers from that block are dumped, there is no name to reference. Define names for relevant sub-blocks to fix this. Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Ryan McCann <quic_rmccann@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/546199/ Link: https://lore.kernel.org/r/20230622-devcoredump_patch-v5-3-67e8b66c4723@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
1071a22c |
|
07-Jul-2023 |
Ryan McCann <quic_rmccann@quicinc.com> |
drm/msm/dpu: Drop unused num argument from relevant macros Drop unused parameter "num" from VIG_SBLK_NOSCALE and DMA sub-block macros. Update calls to relevant macros to reflect change. Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Ryan McCann <quic_rmccann@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/546196/ Link: https://lore.kernel.org/r/20230622-devcoredump_patch-v5-2-67e8b66c4723@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
1fe519aa |
|
03-Jul-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: drop empty features mask INTF_SDM845_MASK The INTF_SDM845_MASK features mask is zero. Drop it completely. Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Tested-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/545386/ Link: https://lore.kernel.org/r/20230704022136.130522-20-dmitry.baryshkov@linaro.org
|
#
48cbbe7c |
|
03-Jul-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: drop empty features mask MERGE_3D_SM8150_MASK The MERGE_3D_SM8150_MASK features mask is zero. Drop it completely. Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Tested-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/545384/ Link: https://lore.kernel.org/r/20230704022136.130522-19-dmitry.baryshkov@linaro.org
|
#
ed4fa8c6 |
|
03-Jul-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: inline INTF_BLK and INTF_BLK_DSI_TE macros To simplify making changes to the hardware block definitions, expand corresponding macros. This way making all the changes are more obvious and visible in the source files. Tested-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/545378/ Link: https://lore.kernel.org/r/20230704022136.130522-18-dmitry.baryshkov@linaro.org
|
#
36e2ad1d |
|
03-Jul-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: inline WB_BLK macros To simplify making changes to the hardware block definitions, expand corresponding macros. This way making all the changes are more obvious and visible in the source files. Tested-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/545380/ Link: https://lore.kernel.org/r/20230704022136.130522-17-dmitry.baryshkov@linaro.org
|
#
35973be8 |
|
03-Jul-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: inline various PP_BLK_* macros To simplify making changes to the hardware block definitions, expand corresponding macros. This way making all the changes are more obvious and visible in the source files. Tested-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/545371/ Link: https://lore.kernel.org/r/20230704022136.130522-16-dmitry.baryshkov@linaro.org
|
#
4fe37d2d |
|
03-Jul-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: inline MERGE_3D_BLK macros To simplify making changes to the hardware block definitions, expand corresponding macros. This way making all the changes are more obvious and visible in the source files. Tested-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/545382/ Link: https://lore.kernel.org/r/20230704022136.130522-15-dmitry.baryshkov@linaro.org
|
#
194347df |
|
03-Jul-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: inline DSC_BLK and DSC_BLK_1_2 macros To simplify making changes to the hardware block definitions, expand corresponding macros. This way making all the changes are more obvious and visible in the source files. Tested-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/545370/ Link: https://lore.kernel.org/r/20230704022136.130522-14-dmitry.baryshkov@linaro.org
|
#
8d3e0dd0 |
|
03-Jul-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: inline LM_BLK macros To simplify making changes to the hardware block definitions, expand corresponding macros. This way making all the changes are more obvious and visible in the source files. Tested-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/545362/ Link: https://lore.kernel.org/r/20230704022136.130522-13-dmitry.baryshkov@linaro.org
|
#
e28db021 |
|
10-Jul-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: inline DSPP_BLK macros To simplify making changes to the hardware block definitions, expand corresponding macros. This way making all the changes are more obvious and visible in the source files. Tested-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/545359/ Link: https://lore.kernel.org/r/20230704022136.130522-12-dmitry.baryshkov@linaro.org
|
#
ef7d0e8d |
|
03-Jul-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: inline SSPP_BLK macros To simplify making changes to the hardware block definitions, expand corresponding macros. This way making all the changes are more obvious and visible in the source files. Tested-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/545377/ Link: https://lore.kernel.org/r/20230704022136.130522-11-dmitry.baryshkov@linaro.org
|
#
fdac4bc5 |
|
03-Jul-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: simplify peer LM handling For each LM there is at max 1 peer LM. Thus there is no need to have a mask for the peer LM enumeration. Change that to have an ID of the peer LM. Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Tested-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/545352/ Link: https://lore.kernel.org/r/20230704022136.130522-4-dmitry.baryshkov@linaro.org
|
#
9891b3df |
|
19-Apr-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
drm/msm/dpu1: Rename sm8150_dspp_blk to sdm845_dspp_blk SDM845 was the first SoC to include both PCC v4 and GC v1.8. We don't currently support any other blocks but the common config for these two can be reused for a large amount of SoCs. Rename it to indicate the origin of that combo. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/533003/ Link: https://lore.kernel.org/r/20230420-topic-dpu_gc-v1-1-d9d1a5e40917@linaro.org [DB: also applied to new catalog files] Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
9a6c13b8 |
|
12-Jun-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: correct MERGE_3D length Each MERGE_3D block has just two registers. Correct the block length accordingly. Fixes: 4369c93cf36b ("drm/msm/dpu: initial support for merge3D hardware block") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/542177/ Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Link: https://lore.kernel.org/r/20230613001004.3426676-3-dmitry.baryshkov@linaro.org
|
#
22598cfc |
|
09-Jun-2023 |
Jessica Zhang <quic_jesszhan@quicinc.com> |
drm/msm/dpu: Add DPU_INTF_DATA_COMPRESS feature flag for DPU >= 7.0 In DPU 7.x and later, DSC/DCE enablement registers have been moved from PINGPONG to INTF. Thus, add a DPU_INTF_DATA_COMPRESS feature flag that will be set if the DATA_COMPRESS register is in the INTF block. Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/541967/ Link: https://lore.kernel.org/r/20230405-add-dsc-support-v6-3-95eab864d1b6@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
0d1b10c6 |
|
25-May-2023 |
Abhinav Kumar <quic_abhinavk@quicinc.com> |
drm/msm/dpu: add DSC 1.2 hw blocks for relevant chipsets Add DSC 1.2 hardware blocks to the catalog with necessary sub-block and feature flag information. Each display compression engine (DCE) contains dual DSC encoders so both share same base address but with its own different sub block address. changes in v4: -- delete DPU_DSC_HW_REV_1_1 -- re arrange sc8280xp_dsc[] changes in v4: -- fix checkpatch warning changes in v10: -- remove hard slice from commit text -- replace DPU_DSC_NATIVE_422_EN with DPU_DSC_NATIVE_42x_EN -- change DSC_BLK_1_2 .len from 0x100 to 0x29c changes in v11: -- remove comment at DSC_BLK_1_2 marco Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Patchwork: https://patchwork.freedesktop.org/patch/539507/ Link: https://lore.kernel.org/r/1685036458-22683-10-git-send-email-quic_khsieh@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
27f0df03 |
|
06-Jun-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
drm/msm/dpu: Add SM6375 support Add basic SM6375 support to the DPU1 driver to enable display output. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/541293/ Link: https://lore.kernel.org/r/20230411-topic-straitlagoon_mdss-v6-8-dee6a882571b@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
3186acba |
|
06-Jun-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
drm/msm/dpu: Add SM6350 support Add SM6350 support to the DPU1 driver to enable display output. It's worth noting that one entry dpu_qos_lut_entry was trimmed off: {.fl = 0, .lut = 0x0011223344556677 }, due to the lack of support for selecting between portrait and landscape LUT settings (for danger and safe LUTs) and no full support for qseed/non-qseed usescases (for QoS LUT). Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/541287/ Link: https://lore.kernel.org/r/20230411-topic-straitlagoon_mdss-v6-6-dee6a882571b@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
c20c4440 |
|
25-May-2023 |
Kuogee Hsieh <quic_khsieh@quicinc.com> |
drm/msm/dpu: add DPU_PINGPONG_DSC feature bit for DPU < 7.0.0 DPU < 7.0.0 requires the PINGPONG block to be involved during DSC setting up. Since DPU >= 7.0.0, enabling and starting the DSC encoder engine was moved to INTF with the help of the flush mechanism. Add a DPU_PINGPONG_DSC feature bit to restrict the availability of dpu_hw_pp_setup_dsc() and dpu_hw_pp_dsc_{enable,disable}() on the PINGPONG block to DPU < 7.0.0 hardware, as the registers are not available on DPU 7.0.0 and higher anymore. Add DPU_PINGPONG_DSC to PINGPONG_SDM845_MASK, PINGPONG_SDM845_TE2_MASK and PINGPONG_SM8150_MASK which is used for all DPU < 7.0 chipsets. changes in v6: -- split patches and rearrange to keep catalog related files at this patch changes in v7: -- rewording commit text as suggested at review comments changes in v9: -- delete BIT(DPU_PINGPONG_DSC) from PINGPONG_SDM845_TE2_MASK changes in v10: -- correct order of commit text Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Patchwork: https://patchwork.freedesktop.org/patch/539502/ Link: https://lore.kernel.org/r/1685036458-22683-4-git-send-email-quic_khsieh@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
a7129231 |
|
19-May-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
drm/msm/dpu: Set DPU_DATA_HCTL_EN for in INTF_SC7180_MASK DPU5 and newer targets enable this unconditionally. Move it from the SC7280 mask to the SC7180 one. Fixes: 7e6ee55320f0 ("drm/msm/disp/dpu1: enable DATA_HCTL_EN for sc7280 target") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/538159/ Link: https://lore.kernel.org/r/20230508-topic-hctl_en-v2-1-e7bea9f1f5dd@linaro.org [DB: removed BIT(DPU_INTF_DATA_COMPRESS), which is not yet merged] Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
7e3d6c54 |
|
28-Apr-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: drop SSPP's SRC subblock The src_blk declares a lame copy of main SSPP register space. It's offset is always 0. It's length has been fixed to 0x150, while SSPP's length is now correct. Drop the src_blk and access SSPP registers without additional subblock lookup. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Patchwork: https://patchwork.freedesktop.org/patch/534745/ Link: https://lore.kernel.org/r/20230429012353.2569481-2-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
0272b9c3 |
|
26-Apr-2023 |
Marijn Suijten <marijn.suijten@somainline.org> |
drm/msm/dpu: Add TEAR-READ-pointer interrupt to INTF block All SoCs since DPU 5.0.0 have the tear interrupt registers moved out of the PINGPONG block and into the INTF block. The new interrupts are described in dpu_hw_interrupts.c, now wire them up in individual SoC catalog files by setting the intr_tear_rd_ptr to the IRQ index spcified in the offset table and enabling this set of DPU interrupts via the mdss_irqs bitmask. Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/534236/ Link: https://lore.kernel.org/r/20230411-dpu-intf-te-v4-19-27ce1a5ab5c6@somainline.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
a38a9949 |
|
26-Apr-2023 |
Marijn Suijten <marijn.suijten@somainline.org> |
drm/msm/dpu: Factor out shared interrupt register in INTF_BLK macro As the INTF block is going to attain more interrupts that don't share the same MDP_SSPP_TOP0_INTR register, factor out the _reg argument for the caller to construct the right interrupt index (register and bit index) to not make the interrupt bit arguments depend on one of multiple interrupt register indices. This brings us more in line with how PP_BLK specifies its interrupts and allows for better wrapping in the arrays. Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/534222/ Link: https://lore.kernel.org/r/20230411-dpu-intf-te-v4-17-27ce1a5ab5c6@somainline.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
fe9d66cf |
|
26-Apr-2023 |
Marijn Suijten <marijn.suijten@somainline.org> |
drm/msm/dpu: Disable pingpong TE on DPU 5.0.0 and above Since hardware revision 5.0.0 the TE configuration moved out of the PINGPONG block into the INTF block. Writing these registers has no effect, and is omitted downstream via the DPU/SDE_PINGPONG_TE feature flag. This flag is only added to PINGPONG blocks used by hardware prior to 5.0.0. The existing PP_BLK_TE macro has been removed in favour of directly passing this feature flag, which has thus far been the only difference with PP_BLK. PP_BLK_DITHER has been left in place as its embedded feature flag already excludes this DPU_PINGPONG_TE bit and differs by setting the block length to zero, as it only contains a DITHER subblock. The code that writes to these registers in the INTF block will follow in subsequent patches. Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/534240/ Link: https://lore.kernel.org/r/20230411-dpu-intf-te-v4-14-27ce1a5ab5c6@somainline.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
853b292b |
|
18-May-2023 |
Marijn Suijten <marijn.suijten@somainline.org> |
drm/msm/dpu: Use V4.0 PCC DSPP sub-block in SC7[12]80 According to various downstream sources the PCC sub-block inside DSPP is version 4.0 since DPU 4.0 and higher, including SC7[12]80 at DPU version 6.2 and 7.2 respectively. After correcting the version this struct becomes identical to sm8150_dspp_sblk which is used all across the catalog: replace uses of sc7180_dspp_sblk with that and remove the struct definition for sc7180_dspp_sblk entirely. Fixes: 4259ff7ae509e ("drm/msm/dpu: add support for pcc color block in dpu driver") Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/537899/ Link: https://lore.kernel.org/r/20230518-dpu-sc7180-pcc-version-v1-1-ec9ca4949e3e@somainline.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
732c2c52 |
|
28-Apr-2023 |
Abhinav Kumar <quic_abhinavk@quicinc.com> |
drm/msm/dpu: drop DSPP_MSM8998_MASK from hw catalog Since GC and IGC masks have now been dropped, DSPP_MSM8998_MASK is the same as DSPP_SC7180_MASK. Since DSPP_SC7180_MASK is used more than DSPP_MSM8998_MASK, lets drop the latter. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Patchwork: https://patchwork.freedesktop.org/patch/534726/ Link: https://lore.kernel.org/r/20230428223646.23595-4-quic_abhinavk@quicinc.com [DB: fixed typo in commit message] Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
9fd5aa5a |
|
28-Apr-2023 |
Abhinav Kumar <quic_abhinavk@quicinc.com> |
drm/msm/dpu: remove GC and IGC related code from dpu catalog Gamma Correction (GC) and Inverse Gamma Correction(IGC) is currently unused. In addition dpu_dspp_sub_blks didn't even have an igc member describing the block. Drop related code from the dpu hardware catalog otherwise this becomes a burden to carry across chipsets in the catalog. changes in v3: - drop IGC related code from dpu_hw_catalog too - update commit text accordingly Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Patchwork: https://patchwork.freedesktop.org/patch/534725/ Link: https://lore.kernel.org/r/20230428223646.23595-3-quic_abhinavk@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
078f766e |
|
20-Apr-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: drop the regdma configuration The regdma is currently not used by the current driver. We have no way to practically verify that the regdma is described correctly. Drop it now. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/533148/ Link: https://lore.kernel.org/r/20230420222558.1208887-1-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
701f6918 |
|
26-Apr-2023 |
Marijn Suijten <marijn.suijten@somainline.org> |
drm/msm/dpu: Fix PP_BLK_DIPHER -> DITHER typo SM8550 exclusively has a DITHER sub-block inside the PINGPONG block and no other registers, hence the DITHER name of the macro and a corresponding PINGPONG block length of zero. However, the PP_BLK_ macro name was typo'd to DIPHER rather than DITHER. Fixes: efcd0107727c ("drm/msm/dpu: add support for SM8550") Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/534214/ Link: https://lore.kernel.org/r/20230411-dpu-intf-te-v4-5-27ce1a5ab5c6@somainline.org Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
|
#
3f23a52f |
|
19-Apr-2023 |
Arnaud Vrac <avrac@freebox.fr> |
drm/msm/dpu: tweak msm8998 hw catalog values Match the values found in the downstream msm-4.4 kernel sde driver. Signed-off-by: Arnaud Vrac <avrac@freebox.fr> Fixes: 94391a14fc27 ("drm/msm/dpu1: Add MSM8998 to hw catalog") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/532900/ Link: https://lore.kernel.org/r/20230419-dpu-tweaks-v1-1-d1bac46db075@freebox.fr Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
|
#
dac76a01 |
|
04-Apr-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: fetch DPU configuration from match data In email discussion it was noted that there can be different SoC device having slightly different SoC features, but sharing the same DPU hw revision. Stop fetching catalog data using core_rev and use platform's match data instead. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/530891/ Link: https://lore.kernel.org/r/20230404130622.509628-42-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
e5edf654 |
|
04-Apr-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: inline IRQ_n_MASK defines IRQ masks are rarely shared between different DPU revisions. Inline them to the dpu_mdss_cfg intances and drop them from the dpu_hw_catalog.c Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/530875/ Link: https://lore.kernel.org/r/20230404130622.509628-36-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
d16b77dd |
|
04-Apr-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: drop duplicate vig_sblk instances After fixing scaler version we are sure that sm8450 and sc8280xp vig sblk's are duplicates of sm8250_vig_sblk and thus can be dropped. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/530876/ Link: https://lore.kernel.org/r/20230404130622.509628-34-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
5ce22484 |
|
04-Apr-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: expand sm6115 catalog Duplicate qcm2290 catalog entries to sm6115 to remove dependencies between DPU instances. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/530862/ Link: https://lore.kernel.org/r/20230404130622.509628-28-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
460c410f |
|
04-Apr-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: duplicate sdm845 catalog entries Duplicate some of sdm845 catalog entries to remove dependencies between DPU major generations. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/530849/ Link: https://lore.kernel.org/r/20230404130622.509628-21-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
9a4425f4 |
|
04-Apr-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: split SDM845 catalog entry to the separate file Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/530846/ Link: https://lore.kernel.org/r/20230404130622.509628-20-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
1c611c48 |
|
04-Apr-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: split MSM8998 catalog entry to the separate file Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/530839/ Link: https://lore.kernel.org/r/20230404130622.509628-19-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
25035306 |
|
04-Apr-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: split SM8150 catalog entry to the separate file Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/530844/ Link: https://lore.kernel.org/r/20230404130622.509628-18-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
97e2c803 |
|
04-Apr-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: split SC8180X catalog entry to the separate file Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/530842/ Link: https://lore.kernel.org/r/20230404130622.509628-17-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
2f36168e |
|
04-Apr-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: split SM8250 catalog entry to the separate file Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/530836/ Link: https://lore.kernel.org/r/20230404130622.509628-16-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
c9cd1552 |
|
04-Apr-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: split SC7180 catalog entry to the separate file Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/530835/ Link: https://lore.kernel.org/r/20230404130622.509628-15-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
c22a42bd |
|
04-Apr-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: split QCM2290 catalog entry to the separate file Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/530837/ Link: https://lore.kernel.org/r/20230404130622.509628-14-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
01f2e9a7 |
|
04-Apr-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: split SM6115 catalog entry to the separate file Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/530830/ Link: https://lore.kernel.org/r/20230404130622.509628-13-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
b8ece0c6 |
|
04-Apr-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: split SM8350 catalog entry to the separate file Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/530832/ Link: https://lore.kernel.org/r/20230404130622.509628-12-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
f0f2c32a |
|
04-Apr-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: split SC7280 catalog entry to the separate file Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/530828/ Link: https://lore.kernel.org/r/20230404130622.509628-11-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
225978f4 |
|
04-Apr-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: split SC8280XP catalog entry to the separate file Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/530825/ Link: https://lore.kernel.org/r/20230404130622.509628-10-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
9cc54793 |
|
04-Apr-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: split SM8550 catalog entry to the separate file Reviewed-by: Konrad DYbcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/530824/ Link: https://lore.kernel.org/r/20230404130622.509628-8-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
fbbd8cce |
|
04-Apr-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: move UBWC/memory configuration to separate struct UBWC and highest bank settings differ slightly between different DPU units of the same generation, while the dpu_caps and dpu_mdp_cfg are much more stable. To ease configuration reuse move ubwc_swizzle and highest_bank_bit data to separate structure. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/530820/ Link: https://lore.kernel.org/r/20230404130622.509628-7-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
ac1c5ed6 |
|
04-Apr-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: mark remaining pp data as const Fix several leftover _pp strutures and mark them as const, making all hw catalog fit into the rodata section. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/530821/ Link: https://lore.kernel.org/r/20230404130622.509628-6-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
fc4fcfb0 |
|
04-Apr-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: constify DSC data structures DSC hw catalog data is not supposed to be changed, so mark it as const data. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/530818/ Link: https://lore.kernel.org/r/20230404130622.509628-5-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
8399a5ff |
|
04-Apr-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
drm/msm/dpu: Allow variable INTF_BLK size These blocks are of variable length on different SoCs. Set the correct values where I was able to retrieve it from downstream DTs and leave the old defaults (0x280) otherwise. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> [DB: fixed some lengths, split the INTF changes away] Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/530816/ Link: https://lore.kernel.org/r/20230404130622.509628-4-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
8f940ddb |
|
04-Apr-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
drm/msm/dpu: Allow variable SSPP_BLK size These blocks are of variable length on different SoCs. Set the correct values where I was able to retrieve it from downstream DTs and leave the old defaults (0x1c8) otherwise. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> [DB: fixed some of lengths, split the INTF changes away] Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/530814/ Link: https://lore.kernel.org/r/20230404130622.509628-3-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
dcb3f7c9 |
|
16-Mar-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: drop smart_dma_rev from dpu_caps The code doesn't use dpu_caps::smart_dma_rev field. It checks if the corresponding feature is enabled in the SSPP features. Drop the smart_dma_rev field completely. Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/527369/ Link: https://lore.kernel.org/r/20230316161653.4106395-31-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
8b409996 |
|
16-Mar-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: populate SmartDMA features in hw catalog Downstream driver uses dpu->caps->smart_dma_rev to update sspp->cap->features with the bit corresponding to the supported SmartDMA version. Upstream driver does not do this, resulting in SSPP subdriver not enabling setup_multirect callback. Add corresponding SmartDMA SSPP feature bits to dpu hw catalog. Per Abhinav's request enable the SmartDMA features only on the platforms where the multirect was actually verified visually (sdm845 and sm8250). An (untested) enablement on the rest of the platforms comes in the next patch. Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/527362/ Link: https://lore.kernel.org/r/20230316161653.4106395-29-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
ffbbed63 |
|
20-Mar-2023 |
Leonard Lausen <leonard@lausen.nl> |
drm/msm/dpu: Add support for AR30 format Commit da7716a249b699978fb5 ("drm/msm/dpu: Add support for XR30 format") enabled support for the 10-bit XR30 color format but missed enabling support for the corresponding per-pixel alpha-blending AR30 color format. Declaring only XR30 but not AR30 color format support can trigger bugs in userspace. KDE KWin compositor versions prior to 5.27.3 for example prefer 10-bit color formats, rendering a 1cm^2 black box around the cursor due to missing per-pixel alpha-blending. Signed-off-by: Leonard Lausen <leonard@lausen.nl> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Tested-by: Jessica Zhang <quic_jesszhan@quicinc.com> # Trogdor (sc7180) Patchwork: https://patchwork.freedesktop.org/patch/527985/ Link: https://lore.kernel.org/r/6f33219dc848ccd7122bce6933338033aa18c33c@lausen.nl Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
83a58b20 |
|
27-Jan-2023 |
Kalyan Thota <quic_kalyant@quicinc.com> |
drm/msm/disp/dpu1: add support for dspp sub block flush in sc7280 Flush mechanism for DSPP blocks has changed in sc7280 family, it allows individual sub blocks to be flushed in coordination with master flush control. Representation: master_flush && (PCC_flush | IGC_flush .. etc ) This change adds necessary support for the above design. Changes in v1: - Few nits (Doug, Dmitry) - Restrict sub-block flush programming to dpu_hw_ctl file (Dmitry) Changes in v2: - Move the address offset to flush macro (Dmitry) - Separate ops for the sub block flush (Dmitry) Changes in v3: - Reuse the DPU_DSPP_xx enum instead of a new one (Dmitry) Changes in v4: - Use shorter version for unsigned int (Stephen) Changes in v5: - Spurious patch please ignore. Changes in v6: - Add SOB tag (Doug, Dmitry) Changes in v7: - Cache flush mask per dspp (Dmitry) - Few nits (Marijn) Changes in v8: - Few nits (Marijn) Changes in v9: - Use DSPP enum while accessing flush mask to make it readable (Dmitry) - Few nits (Dmitry) Changes in v10: - Fix white spaces in a separate patch (Dmitry) Changes in v11: - Define a macro for dspp flush selection (Marijn) - Few nits (Marijn) Changes in v12: - Minor comments (reorder macros and a condition) (Marijn) Signed-off-by: Kalyan Thota <quic_kalyant@quicinc.com> Tested-by: Douglas Anderson <dianders@chromium.org> Patchwork: https://patchwork.freedesktop.org/patch/520701/ Link: https://lore.kernel.org/r/1674814487-2112-1-git-send-email-quic_kalyant@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
e3969ead |
|
02-Mar-2023 |
Vinod Polimera <quic_vpolimer@quicinc.com> |
drm/msm/disp/dpu: get timing engine status from intf status register Recommended way of reading the interface timing gen status is via status register. Timing gen status register will give a reliable status of the interface especially during ON/OFF transitions. This support was added from DPU version 5.0.0. Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/524724/ Link: https://lore.kernel.org/r/1677774797-31063-6-git-send-email-quic_vpolimer@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
ce68153e |
|
27-Feb-2023 |
Kuogee Hsieh <quic_khsieh@quicinc.com> |
drm/msm/disp/dpu: fix sc7280_pp base offset At sc7280, pingpong block is used to management the dither effects to reduce distortion at panel. Currently pingpong-0 base offset is wrongly set at 0x59000. This mistake will not cause system to crash. However it will make dither not work. This patch correct sc7280 ping pong-0 block base offset. Changes in v2: -- add more details info n regrading of pingpong block at commit text Fixes: 591e34a091d1 ("drm/msm/disp/dpu1: add support for display for SC7280 target") Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/524332/ Link: https://lore.kernel.org/r/1677533800-3125-1-git-send-email-quic_khsieh@quicinc.com Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
|
#
d6181c18 |
|
11-Feb-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: don't use DPU_CLK_CTRL_CURSORn for DMA SSPP clocks DPU driver has been using the DPU_CLK_CTRL_CURSOR prefix for the DMA SSPP blocks used for the cursor planes. This has lead to the confusion at least for the MSM8998 platform. In preparation to supporting the cursor SSPP blocks, use proper enum values to index DMA SSPP clock controls. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550 on top of next-20230116 Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/522228/ Link: https://lore.kernel.org/r/20230211231259.1308718-14-dmitry.baryshkov@linaro.org Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
|
#
0abb6a24 |
|
11-Feb-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: fix clocks settings for msm8998 SSPP blocks DMA2 and DMA3 planes on msm8998 should use corresponding DMA2 and DMA3 clocks rather than CURSOR0/1 clocks (which are used for the CURSOR planes). Correct corresponding SSPP declarations. Fixes: 94391a14fc27 ("drm/msm/dpu1: Add MSM8998 to hw catalog") Cc: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Cc: Jami Kettunen <jami.kettunen@somainline.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/522230/ Link: https://lore.kernel.org/r/20230211231259.1308718-13-dmitry.baryshkov@linaro.org Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
|
#
a5045b00 |
|
11-Feb-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: drop DPU_DIM_LAYER from MIXER_MSM8998_MASK The msm8998 doesn't seem to support DIM_LAYER, so drop it from the supported features mask. Fixes: 2d8a4edb672d ("drm/msm/dpu: use feature bit for LM combined alpha check") Fixes: 94391a14fc27 ("drm/msm/dpu1: Add MSM8998 to hw catalog") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/522231/ Link: https://lore.kernel.org/r/20230211231259.1308718-12-dmitry.baryshkov@linaro.org Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
|
#
38164e99 |
|
11-Feb-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: correct sm6115 scaler QSEED4 is a newer variant of QSEED3LITE, which should be used on sm6115. Fix the used feature masks. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Fixes: 3581b7062cec ("drm/msm/disp/dpu1: add support for display on SM6115") Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/522219/ Link: https://lore.kernel.org/r/20230211231259.1308718-11-dmitry.baryshkov@linaro.org Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
|
#
03c0c3cb |
|
11-Feb-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: correct sm8250 and sm8350 scaler QSEED4 is a newer variant of QSEED3LITE, which should be used on sm8250 and sm8350. Fix the DPU caps structure and used feature masks. Fixes: d21fc5dfc3df ("drm/msm/dpu1: add support for qseed3lite used on sm8250") Fixes: 0e91bcbb0016 ("drm/msm/dpu: Add SM8350 to hw catalog") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/522229/ Link: https://lore.kernel.org/r/20230211231259.1308718-10-dmitry.baryshkov@linaro.org Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
|
#
c7da17b6 |
|
11-Feb-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: correct sm8450 scaler QSEED4 is a newer variant of QSEED3LITE, which should be used on sm8450. Fix the used feature masks. Fixes: 100d7ef6995d ("drm/msm/dpu: add support for SM8450") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/522215/ Link: https://lore.kernel.org/r/20230211231259.1308718-9-dmitry.baryshkov@linaro.org Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
|
#
b3587cb6 |
|
11-Feb-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: correct sc8280xp scaler QSEED4 is a newer variant of QSEED3LITE, which should be used on sc8280xp. Fix the DPU caps structure and used feature masks. Fixes: 4a352c2fc15a ("drm/msm/dpu: Introduce SC8280XP") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/522217/ Link: https://lore.kernel.org/r/20230211231259.1308718-8-dmitry.baryshkov@linaro.org Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
|
#
d113d267 |
|
11-Feb-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: correct sm8550 scaler QSEED4 is a newer variant of QSEED3LITE, which should be used on sm8550. Fix the DPU caps structure and used feature masks. Fixes: efcd0107727c ("drm/msm/dpu: add support for SM8550") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/522213/ Link: https://lore.kernel.org/r/20230211231259.1308718-7-dmitry.baryshkov@linaro.org Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
|
#
da06be8b |
|
11-Feb-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: fix sm6115 and qcm2290 mixer width limits According to vendor DTS files both sm6115 and qcm2290 should have max_mixer_width set to 2048 (DEFAULT_DPU_LINE_WIDTH). Correct it. Fixes: 3581b7062cec ("drm/msm/disp/dpu1: add support for display on SM6115") Fixes: 5334087ee743 ("drm/msm: add support for QCM2290 MDSS") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/522212/ Link: https://lore.kernel.org/r/20230211231259.1308718-6-dmitry.baryshkov@linaro.org [quic_abhinavk@quicinc.com: fix minor typo in commit message] Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
|
#
ce6bd00a |
|
11-Feb-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: fix len of sc7180 ctl blocks Change sc7180's ctl block len to 0x1dc. Fixes: 7bdc0c4b8126 ("msm:disp:dpu1: add support for display for SC7180 target") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/522210/ Link: https://lore.kernel.org/r/20230211231259.1308718-5-dmitry.baryshkov@linaro.org Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
|
#
e3011955 |
|
11-Feb-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: fix typo in in sm8550's dma_sblk_5 Fix typo in the name of the sblk structure for the sm8550's dma_sblk_5. Fixes: efcd0107727c ("drm/msm/dpu: add support for SM8550") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/522225/ Link: https://lore.kernel.org/r/20230211231259.1308718-4-dmitry.baryshkov@linaro.org [quic_abhinavk@quicinc.com: fix minor typo in commit message] Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
|
#
a2a448b4 |
|
11-Feb-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: disable features unsupported by QCM2290 QCM2290 doesn't seem to support reg-dma, UBWC and CSC. Drop corresponding features being incorrectly enabled for qcm2290. Cc: Loic Poulain <loic.poulain@linaro.org> Fixes: 5334087ee743 ("drm/msm: add support for QCM2290 MDSS") Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/522209/ Link: https://lore.kernel.org/r/20230211231259.1308718-3-dmitry.baryshkov@linaro.org Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
|
#
0df979f4 |
|
11-Feb-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: set DPU_MDP_PERIPH_0_REMOVED for sc8280xp The SC8280XP also has a black hole at the top of MDP_TOP region. Set corresponding bit to disable access to that region. Fixes: 4a352c2fc15a ("drm/msm/dpu: Introduce SC8280XP") Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/522207/ Link: https://lore.kernel.org/r/20230211231259.1308718-2-dmitry.baryshkov@linaro.org Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
|
#
0b5a8e81 |
|
07-Dec-2022 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: correct the UBWC version on sm6115 According to downstream (bengal-sde.dtsi), the sm6115 uses UBWC 1.0. Change the catalog entry accordingly. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/514337/ Link: https://lore.kernel.org/r/20221207142833.204193-3-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
6c021d77 |
|
23-Jan-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: fix sm8450 CTL configuration Correct the CTL size on sm8450 platform. This fixes the incorrect merge of sm8350 support, which unfortunately also touched the SM8450 setup. Fixes: 0e91bcbb0016 ("drm/msm/dpu: Add SM8350 to hw catalog") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/519671/ Link: https://lore.kernel.org/r/20230123080818.3069266-1-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
31c31805 |
|
22-Jan-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: add missing ubwc_swizzle setting to catalog Use the values from the vendor DTs to set ubwc_swizzle in the catalog. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/519662/ Link: https://lore.kernel.org/r/20230123062415.3027743-1-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
255f0561 |
|
15-Jan-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: sc7180: add missing WB2 clock control Add missing DPU_CLK_CTRL_WB2 to sc7180_mdp clocks array. Fixes: 51e4d60e6ba5 ("drm/msm/dpu: add writeback support for sc7180") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Tested-by: Jessica Zhang <quic_jesszhan@quicinc.com> # Trogdor (sc7180) Patchwork: https://patchwork.freedesktop.org/patch/518504/ Link: https://lore.kernel.org/r/20230116103055.780767-1-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
764b9481 |
|
17-Jan-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: use sm8350_regdma on SM8350 platform Correct sm8350_dpu_cfg.dma_cfg to point to sm8350_regdma rather than sm8250_regdma. Fixes: 0e91bcbb0016 ("drm/msm/dpu: Add SM8350 to hw catalog") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/518791/ Link: https://lore.kernel.org/r/20230118020455.1689929-2-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
83bb1f13 |
|
17-Jan-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: point sc8280xp_dpu_cfg to sc8280xp_regdma SC8280XP configuration missed the reg_dma configuration. We do not use regdma for now, but let's put the correct pointer anyway. Fixes: 4a352c2fc15a ("drm/msm/dpu: Introduce SC8280XP") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/518790/ Link: https://lore.kernel.org/r/20230118020455.1689929-1-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
10a88954 |
|
15-Jan-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: enable DPU_MDP_AUDIO_SELECT for sc8180x According to the discussion ([1]) on the mailing list, platforms before sm8250 (and derivatives) should program HDMI_DP_CORE_SELECT register to route audio to the DP ports. Enable DPU_MDP_AUDIO_SELECT on sc8180x to program correponding register. [1] https://lore.kernel.org/all/f86504ba-835a-6e30-6c30-8bb89b1359c4@quicinc.com/ Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/518461/ Link: https://lore.kernel.org/r/20230115140022.489881-1-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
e92a4ae1 |
|
15-Jan-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: fix blend setup for DMA4 and DMA5 layers SM8550 uses new register to map SSPP_DMA4 and SSPP_DMA5 units to blend stages. Add proper support for this register to allow using these two planes for image processing. Fixes: efcd0107727c ("drm/msm/dpu: add support for SM8550") Cc: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550 Patchwork: https://patchwork.freedesktop.org/patch/518481/ Link: https://lore.kernel.org/r/20230116063316.728496-1-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
00feff8f |
|
15-Jan-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: enable sourcesplit for sc7180/sc7280 According to the vendor dts files, both sc7180 and sc7280 support the source split mode (using two LMs for a single output). Change these two platforms to use MIXER_SDM845_MASK, which includes DPU_MIXER_SOURCESPLIT. Rename MIXER_SC7180_MASK to MIXER_QCM2290_MASK, since this platform doesn't seem to support source split mode. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/518479/ Link: https://lore.kernel.org/r/20230116034435.569512-1-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
9da5daa0 |
|
21-Dec-2022 |
Marijn Suijten <marijn.suijten@somainline.org> |
drm/msm/dpu: Add DSC configuration for SM8150 and SM8250 These DSC blocks on CTL V1 need to set its corresponding PINGPONG block index in a hardware register to configure where to send pixel output to, via the newly-added DPU_DSC_OUTPUT_CTRL feature flag. Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/515689/ Link: https://lore.kernel.org/r/20221221231943.1961117-9-marijn.suijten@somainline.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
efcd0107 |
|
09-Jan-2023 |
Neil Armstrong <neil.armstrong@linaro.org> |
drm/msm/dpu: add support for SM8550 Add definitions for the display hardware used on Qualcomm SM8550 platform. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/517512/ Link: https://lore.kernel.org/r/20230103-topic-sm8550-upstream-mdss-dsi-v3-4-660c3bcb127f@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
4a352c2f |
|
07-Dec-2022 |
Bjorn Andersson <andersson@kernel.org> |
drm/msm/dpu: Introduce SC8280XP The Qualcomm SC8280XP platform contains DPU version 8.0.0, has 9 interfaces, 2 DSI controllers and 4 DisplayPort controllers. Extend the necessary definitions and describe the DPU in the SC8280XP. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Kuogee Hsieh <quic_khsieh@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/514398/ Link: https://lore.kernel.org/r/20221207220012.16529-3-quic_bjorande@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
5dfc1b2e |
|
09-Jan-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: disable DSC blocks for SM8350 SM8350 has newer version of DSC blocks, which are not supported by the driver yet. Remove them for now until these blocks are supported by the driver. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/517629/ Link: https://lore.kernel.org/r/20230109214309.586130-1-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
7eb75dbd |
|
30-Dec-2022 |
Robert Foss <rfoss@kernel.org> |
drm/msm/dpu: Add support for SM8350 Add compatibles string, "qcom,sm8350-dpu", for the display processing unit used on Qualcomm SM8350 platform. Signed-off-by: Robert Foss <robert.foss@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/516342/ Link: https://lore.kernel.org/r/20221230153554.105856-5-robert.foss@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
0e91bcbb |
|
30-Dec-2022 |
Robert Foss <rfoss@kernel.org> |
drm/msm/dpu: Add SM8350 to hw catalog Add compatibility for SM8350 display subsystem, including required entries in DPU hw catalog. Signed-off-by: Robert Foss <robert.foss@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/516340/ Link: https://lore.kernel.org/r/20221230153554.105856-4-robert.foss@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
100d7ef6 |
|
06-Dec-2022 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: add support for SM8450 Add definitions for the display hardware used on Qualcomm SM8450 platform. Tested-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/514235/ Link: https://lore.kernel.org/r/20221207012231.112059-11-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
a685d27f |
|
07-Nov-2022 |
Konrad Dybcio <konrad.dybcio@somainline.org> |
drm/msm/dpu1: Remove INTF4 IRQ from SDM845 IRQ mask SDM845 only has INTF0-3 and has no business caring about the INTF4 irq. Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/510463/ Link: https://lore.kernel.org/r/20221107103739.8993-1-konrad.dybcio@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
3581b706 |
|
23-Nov-2022 |
Adam Skladowski <a39.skl@gmail.com> |
drm/msm/disp/dpu1: add support for display on SM6115 Add required display hw catalog changes for SM6115. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Adam Skladowski <a39.skl@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/512875/ Link: https://lore.kernel.org/r/20221124001708.25720-3-a39.skl@gmail.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
1a5b5372 |
|
28-Oct-2022 |
Robert Foss <robert.foss@linaro.org> |
drm/msm/dpu: Refactor sc7280_pp location The sc7280_pp declaration is not located by the other _pp declarations, but rather hidden around the _merge_3d declarations. Let's fix this to avoid confusion. Signed-off-by: Robert Foss <robert.foss@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/509153/ Link: https://lore.kernel.org/r/20221028120812.339100-3-robert.foss@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
f07c9946 |
|
01-Sep-2022 |
Jessica Zhang <quic_jesszhan@quicinc.com> |
drm/msm/dpu: Add support for P010 format Add support for P010 color format. This adds support for both linear and compressed formats. Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com> Reviewed-by: Rob Clark <robdclark@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/500822/ Link: https://lore.kernel.org/r/20220901203422.217-3-quic_jesszhan@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
da7716a2 |
|
01-Sep-2022 |
Jessica Zhang <quic_jesszhan@quicinc.com> |
drm/msm/dpu: Add support for XR30 format Add support for XR30 color format. This supports both linear and compressed formats. Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com> Reviewed-by: Rob Clark <robdclark@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/500820/ Link: https://lore.kernel.org/r/20220901203422.217-2-quic_jesszhan@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
1364a4ee |
|
22-Aug-2022 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: drop unused memory allocation Drop the dpu_cfg variable and corresponding kzalloc, which became unused after changing hw catalog to static configuration. Fixes: de7d480f5e8c ("drm/msm/dpu: make dpu hardware catalog static const") Reported-by: kernel test robot <lkp@intel.com> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/498738/ Link: https://lore.kernel.org/r/20220822172455.282923-1-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
|
#
606f015b |
|
15-Jun-2022 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: drop VBIF indices We do not expect to have other VBIFs. Drop VBIF_n indices and always use VBIF_RT and VBIF_NRT. Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/489571/ Link: https://lore.kernel.org/r/20220615125703.24647-3-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
|
#
fca5ad26 |
|
21-Jun-2022 |
Kalyan Thota <quic_kalyant@quicinc.com> |
drm/msm/disp/dpu1: add dspp support for sc7280 Add destination side post processing hw block support in sc7280. This hwblock enablement is necessary to support color features like CT Matix (Ex: Night Light feature) Signed-off-by: Kalyan Thota <quic_kalyant@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/490382/ Link: https://lore.kernel.org/r/1655802387-15275-1-git-send-email-quic_kalyant@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
a370cc39 |
|
16-Jun-2022 |
Abhinav Kumar <quic_abhinavk@quicinc.com> |
drm/msm/dpu: fix maxlinewidth for writeback block Writeback block for sm8250 was using the default maxlinewidth of 2048. But this is not right as it supports upto 4096. This should have no effect on most resolutions as we are still limiting upto maxlinewidth of SSPP for adding the modes. Fix the maxlinewidth for writeback block on sm8250. changes in v3: - correct the Fixes tag Fixes: 53324b99bd7b ("drm/msm/dpu: add writeback blocks to the sm8250 DPU catalog") Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/489887/ Link: https://lore.kernel.org/r/1655406084-17407-2-git-send-email-quic_abhinavk@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
de7d480f |
|
02-Jun-2022 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: make dpu hardware catalog static const Replace superfluous cfg_init functions, which just assign a static config to the struct dpu_mdss_cfg, with static instances of struct dpu_mdss_cfg. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/488166/ Link: https://lore.kernel.org/r/20220602202447.1755115-8-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
32084967 |
|
02-Jun-2022 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: constify struct dpu_mdss_cfg Mark struct dpu_mdss_cfg instance as a const pointer. This is mostly a preparation for the next patch. Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/488164/ Link: https://lore.kernel.org/r/20220602202447.1755115-7-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
481d5dbb |
|
02-Jun-2022 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: change catalog->dma_cfg to be a const pointer Change dpu_mdss_cfg::dma_cfg to be a const pointer rather than embedding the dpu_reg_dma_cfg struct into the struct dpu_mdss_cfg. Reported-by: kernel test robot <lkp@intel.com> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/488162/ Link: https://lore.kernel.org/r/20220602202447.1755115-6-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
477db4fe |
|
02-Jun-2022 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: change catalog->perf to be a const pointer Change dpu_mdss_cfg::perf to be a const pointer rather than embedding the dpu_perf_cfg struct into the struct dpu_mdss_cfg. Reported-by: kernel test robot <lkp@intel.com> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/488158/ Link: https://lore.kernel.org/r/20220602202447.1755115-5-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
129ae533 |
|
02-Jun-2022 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: remove hwversion field from data structures The driver should not depend on hw revision for detecting features. Instead it should use features from the hw catalog. Drop the hwversion field from struct dpu_mdss_cfg and struct dpu_hw_blk_reg_map. Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/488160/ Link: https://lore.kernel.org/r/20220602202447.1755115-4-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
c8744315 |
|
02-Jun-2022 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: move VBIF_XINL_QOS_LVL_REMAP size to hw_catalog Rather than detecting VBIF_XINL_QOS_LVL_REMAP_000 based on the hwversion, push the offset to the hw_catalog. Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/488156/ Link: https://lore.kernel.org/r/20220602202447.1755115-3-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
2d8a4edb |
|
02-Jun-2022 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: use feature bit for LM combined alpha check Rather than checking hwversion, follow the usual patter and add special bit to the lm->features to check whether the LM has combined or separate alpha registers. While we are at it, rename dpu_hw_lm_setup_blend_config_sdm845() to dpu_hw_lm_setup_blend_config_combined_alpha(). Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/488155/ Link: https://lore.kernel.org/r/20220602202447.1755115-2-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
51e4d60e |
|
10-May-2022 |
Abhinav Kumar <quic_abhinavk@quicinc.com> |
drm/msm/dpu: add writeback support for sc7180 Add writeback support for sc7180 devices. This has been validated on sc7180 chromebook using IGT writeback test suite. localhost /usr/local/libexec/igt-gpu-tools # ./kms_writeback Starting subtest: writeback-pixel-formats Subtest writeback-pixel-formats: SUCCESS (0.001s) Starting subtest: writeback-invalid-parameters Subtest writeback-invalid-parameters: SUCCESS (0.004s) Starting subtest: writeback-fb-id Subtest writeback-fb-id: SUCCESS (0.009s) Starting subtest: writeback-check-output Subtest writeback-check-output: SUCCESS (0.203s) Adding this will increase IGT coverage on chromebooks and also allow using writeback functionality for other use-cases as necessary. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/485787/ Link: https://lore.kernel.org/r/20220510235439.31916-1-quic_abhinavk@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
c162352e |
|
30-Apr-2022 |
Konrad Dybcio <konrad.dybcio@somainline.org> |
drm/msm/disp: dpu1: Properly sort qcm2290_dpu_caps Due to MSM8998 support having been stuck in review for so long, another struct was added nearby, which confused git and resulted in the definitions not being sorted alphabetically. Fix it. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/484296/ Link: https://lore.kernel.org/r/20220430161529.605843-3-konrad.dybcio@somainline.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
53324b99 |
|
26-Apr-2022 |
Abhinav Kumar <quic_abhinavk@quicinc.com> |
drm/msm/dpu: add writeback blocks to the sm8250 DPU catalog Add writeback blocks to the sm8250 DPU hardware catalog. Other chipsets support writeback too but add it to sm8250 to prototype the feature so that it can be easily extended to other chipsets. changes in v4: - fix the copyright year order Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/483510/ Link: https://lore.kernel.org/r/1650984096-9964-4-git-send-email-quic_abhinavk@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
dabfdd89 |
|
11-Apr-2022 |
Vinod Polimera <quic_vpolimer@quicinc.com> |
drm/msm/disp/dpu1: add inline rotation support for sc7280 - Some DPU versions support inline rot90. It is supported only for limited amount of UBWC formats. - There are two versions of inline rotators, v1 (present on sm8250 and sm7250) and v2 (sc7280). These versions differ in the list of supported formats and in the scaler possibilities. Co-developed-by: Kalyan Thota <quic_kalyant@quicinc.com> Signed-off-by: Kalyan Thota <quic_kalyant@quicinc.com> Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/481672/ Link: https://lore.kernel.org/r/1649695021-19132-3-git-send-email-quic_vpolimer@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
7c5ab05e |
|
06-Apr-2022 |
Vinod Koul <vkoul@kernel.org> |
drm/msm/disp/dpu1: Add DSC for SDM845 to hw_catalog This adds SDM845 DSC blocks into hw_catalog Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Vinod Koul <vkoul@kernel.org> Patchwork: https://patchwork.freedesktop.org/patch/480916/ Link: https://lore.kernel.org/r/20220406094031.1027376-6-vkoul@kernel.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
6452cbd6 |
|
21-Feb-2022 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: wire up MSM8998's DSPP blocks The commit adding msm8998 support didn't added msm8998's DSPP blocks configuration, but did not use them in msm8998_cfg_init(). Wire them up to be used for display post processing. Reported-by: kernel test robot <lkp@intel.com> Fixes: 94391a14fc27 ("drm/msm/dpu1: Add MSM8998 to hw catalog") Cc: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Cc: Jami Kettunen <jami.kettunen@somainline.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/475544/ Link: https://lore.kernel.org/r/20220222031948.228727-1-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
5334087e |
|
14-Feb-2022 |
Loic Poulain <loic.poulain@linaro.org> |
drm/msm: add support for QCM2290 MDSS Add compatibility for QCM2290 display subsystem, including required entries in DPU hw catalog. Signed-off-by: Loic Poulain <loic.poulain@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/474087/ Link: https://lore.kernel.org/r/1644852547-10067-1-git-send-email-loic.poulain@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
f3af2d6e |
|
16-Feb-2022 |
Rob Clark <robdclark@chromium.org> |
drm/msm/dpu: Add SC8180x to hw catalog Add SC8180x to the hardware catalog, for initial support for the platform. Due to limitations in the DP driver only one of the four DP interfaces is left enabled. The SC8180x platform supports the newly added DPU_INTF_WIDEBUS flag and the Windows-on-Snapdragon bootloader leaves the widebus bit set, so this is flagged appropriately to ensure widebus is disabled - for now. Signed-off-by: Rob Clark <robdclark@chromium.org> [bjorn: Reworked intf and irq definitions] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
03490e11 |
|
14-Feb-2022 |
Kuogee Hsieh <quic_khsieh@quicinc.com> |
drm/msm: populate intf_audio_select() base on hardware capability intf_audio_select() callback function use to configure HDMI_DP_CORE_SELECT to decide audio output routes to HDMI or DP interface. HDMI is obsoleted at newer chipset. To keep supporting legacy hdmi application, intf_audio_select call back function have to be populated base on hardware chip capability where legacy chipsets have has_audio_select flag set to true. Changes in V2: -- remove has_audio_select flag -- add BIT(DPU_MDP_AUDIO_SELECT) into dpu_mdp_cfg Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/1644875214-12944-1-git-send-email-quic_khsieh@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
94391a14 |
|
13-Jan-2022 |
AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> |
drm/msm/dpu1: Add MSM8998 to hw catalog Bringup functionality for MSM8998 in the DPU, driver which is mostly the same as SDM845 (just a few variations). Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Jami Kettunen <jami.kettunen@somainline.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220113145111.29984-3-jami.kettunen@somainline.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
#
44bf8704 |
|
29-Oct-2021 |
Kalyan Thota <quic_kalyant@quicinc.com> |
drm/msm/disp/dpu1: set default group ID for CTL. New required programming in CTL for SC7280. Group ID informs HW of which VM owns that CTL. Force this group ID to default/disabled until virtualization support is enabled in SW. Changes in v1: - Fix documentation and add descritpion for the change (Stephen) Signed-off-by: Kalyan Thota <quic_kalyant@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/1635510619-6715-1-git-send-email-quic_kalyant@quicinc.com Signed-off-by: Rob Clark <robdclark@chromium.org>
|
#
ef7837ff |
|
02-Nov-2021 |
Sankeerth Billakanti <quic_sbillaka@quicinc.com> |
drm/msm/dp: Add DP controllers for sc7280 The eDP controller on SC7280 is similar to the eDP/DP controllers supported by the current driver implementation. SC7280 supports one EDP and one DP controller which can operate concurrently. This change adds the support for eDP and DP controller on sc7280. Signed-off-by: Sankeerth Billakanti <quic_sbillaka@quicinc.com> changes in v3: - Split into patches according to function (Dmitry Baryshkov) - Use DP_CONTROLLER_1 for eDP controller intf (Dmitry Baryshkov) - Use DP_CONTROLLER_0 for sc7280-dp (Dmitry Baryshkov) - Add macro in drm_helper.h for checking ssc capability (Stephen Boyd) - Use existing macro to check assr capability (Stephen Boyd) - Add comment for HPD_INIT_SETUP delay (Stephen Boyd) changes in v2: - Don't initialize variables to 0 (Stephen Boyd) - Use const for read-only dpcd (Stephen Boyd) - Remove zero pixel clock check (Stephen Boyd) - Sort compatible strings alphabetically (Stephen Boyd) - Use pwm_bl.c for backlight instead of gpio (Stephen Boyd) - Change return type for functions returning always 0 (Matthias Kaehlcke) Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/1635839325-401-3-git-send-email-quic_sbillaka@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
|
#
bb3de286 |
|
16-Oct-2021 |
Bjorn Andersson <bjorn.andersson@linaro.org> |
drm/msm/dp: Support up to 3 DP controllers Based on the removal of the g_dp_display and the movement of the priv->dp lookup into the DP code it's now possible to have multiple DP instances. In line with the other controllers in the MSM driver, introduce a per-compatible list of base addresses which is used to resolve the "instance id" for the given DP controller. This instance id is used as index in the priv->dp[] array. Then extend the initialization code to initialize struct drm_encoder for each of the registered priv->dp[] and update the logic for associating each struct msm_dp with the struct dpu_encoder_virt. A new enum is introduced to document the connection between the instances referenced in the dpu_intf_cfg array and the controllers in the DP driver and sc7180 is updated. Lastly, bump the number of struct msm_dp instances carries by priv->dp to 3, the currently known maximum number of controllers found in a Qualcomm SoC. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20211016221843.2167329-6-bjorn.andersson@linaro.org Signed-off-by: Rob Clark <robdclark@chromium.org>
|
#
9960f7a8 |
|
28-Sep-2021 |
Rob Clark <robdclark@chromium.org> |
drm/msm/dpu: Remove some nonsense These aren't used. And if we add use for them later, we should probably do something a bit more structured than string parsing. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210928162903.1104847-1-robdclark@gmail.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
|
#
3431c17b |
|
19-Aug-2021 |
Robert Foss <robert.foss@linaro.org> |
drm/msm/dpu: Fix address of SM8150 PINGPONG5 IRQ register Both PINGPONG4 and PINGPONG5 IRQ registers are using the same address, which is incorrect. PINGPONG4 should use the register offset 30, and PINGPONG5 should use the register offset 31 according to the downstream driver. Fixes: 667e9985ee24 ("drm/msm/dpu: replace IRQ lookup with the data in hw catalog") Signed-off-by: Robert Foss <robert.foss@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210819133636.2045766-1-robert.foss@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
|
#
5bccb945 |
|
04-Aug-2021 |
Kalyan Thota <kalyan_t@codeaurora.org> |
drm/msm/disp/dpu1: add safe lut config in dpu driver Add safe lut configuration for all the targets in dpu driver as per QOS recommendation. Issue reported on SC7280: With wait-for-safe feature in smmu enabled, RT client buffer levels are checked to be safe before smmu invalidation. Since display was always set to unsafe it was delaying the invalidaiton process thus impacting the performance on NRT clients such as eMMC and NVMe. Validated this change on SC7280, With this change eMMC performance has improved significantly. Changes in v2: - Add fixes tag (Sai) - CC stable kernel (Dimtry) Changes in v3: - Correct fixes tag with appropriate hash (stephen) - Resend patch adding reviewed by tag - Resend patch adding correct format for pushing into stable tree (Greg) Fixes: 591e34a091d1 ("drm/msm/disp/dpu1: add support for display for SC7280 target") Cc: stable@vger.kernel.org Signed-off-by: Kalyan Thota <kalyan_t@codeaurora.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> (sc7280, sc7180) Link: https://lore.kernel.org/r/1628070028-2616-1-git-send-email-kalyan_t@codeaurora.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
|
#
b910a020 |
|
28-Jun-2021 |
Robert Foss <robert.foss@linaro.org> |
drm/msm/dpu: Fix sm8250_mdp register length The downstream dts lists this value as 0x494, and not 0x45c. Fixes: af776a3e1c30 ("drm/msm/dpu: add SM8250 to hw catalog") Signed-off-by: Robert Foss <robert.foss@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210628085033.9905-1-robert.foss@linaro.org Signed-off-by: Rob Clark <robdclark@chromium.org>
|
#
18b20ac0 |
|
16-May-2021 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: drop remains of old irq lookup subsystem There is no more need for the dpu_intr_type types, dpu_irq_map table, individual intr defines and obsolete_irq field. Drop all of them now. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Link: https://lore.kernel.org/r/20210516202910.2141079-6-dmitry.baryshkov@linaro.org Signed-off-by: Rob Clark <robdclark@chromium.org>
|
#
667e9985 |
|
16-May-2021 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: replace IRQ lookup with the data in hw catalog The IRQ table in the dpu_hw_interrupts.h is big, ugly, and hard to maintain. There are only few interrupts used from that table. Newer generations use different IRQ locations. Move this data to hw catalog. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Link: https://lore.kernel.org/r/20210516202910.2141079-5-dmitry.baryshkov@linaro.org [fixup tracepoint compile warns/err] Signed-off-by: Rob Clark <robdclark@chromium.org>
|
#
597762d5 |
|
16-May-2021 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: define interrupt register names In order to make mdss_irqs readable (and error-prone) define names for interrupt register indices. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Link: https://lore.kernel.org/r/20210516202910.2141079-4-dmitry.baryshkov@linaro.org Signed-off-by: Rob Clark <robdclark@chromium.org>
|
#
dc8a4973 |
|
06-Apr-2021 |
Krishna Manikandan <mkrishn@codeaurora.org> |
drm/msm/disp/dpu1: add flags to indicate obsolete irqs Some irqs which are applicable for sdm845 target are no longer applicable for sc7180 and sc7280 targets. Add a flag to indicate the irqs which are obsolete for a particular target so that these irqs are skipped while checking for matching irq lookup index. Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org> Link: https://lore.kernel.org/r/1617688895-26275-4-git-send-email-mkrishn@codeaurora.org Signed-off-by: Rob Clark <robdclark@chromium.org>
|
#
591e34a0 |
|
05-Apr-2021 |
Krishna Manikandan <mkrishn@codeaurora.org> |
drm/msm/disp/dpu1: add support for display for SC7280 target Add required display hw catalog changes for SC7280 target. Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org> Link: https://lore.kernel.org/r/1617685792-14376-2-git-send-email-mkrishn@codeaurora.org Signed-off-by: Rob Clark <robdclark@chromium.org>
|
#
4f2c9838 |
|
31-Mar-2021 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: fill missing details in hw catalog for sdm845 and sm8[12]50 Fill clk_inefficiency_factor, bw_inefficiency_factor and min_prefill_lines in hw catalog data for sdm845 and sm8[12]50. Efficiency factors are blindly copied from sc7180 data, while min_prefill_lines is based on downstream display driver. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210401020533.3956787-1-dmitry.baryshkov@linaro.org Signed-off-by: Rob Clark <robdclark@chromium.org>
|
#
095eed89 |
|
18-Mar-2021 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: enable DPU_SSPP_QOS_8LVL for SM8250 SM8250 platform has a 8-Levels VIG QoS setting. This setting was missed due to bad interaction with b8dab65b5ac3 ("drm/msm/dpu: Move DPU_SSPP_QOS_8LVL bit to SDM845 and SC7180 masks"), which was applied in parallel. Fixes: d21fc5dfc3df ("drm/msm/dpu1: add support for qseed3lite used on sm8250") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210318105435.2011222-1-dmitry.baryshkov@linaro.org Signed-off-by: Rob Clark <robdclark@chromium.org>
|
#
d21fc5df |
|
15-Jan-2021 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu1: add support for qseed3lite used on sm8250 SM8250 has quite unique qseed lut type: qseed3lite, which is a lightweight version of qseed3 scaler. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
|
#
862314bc |
|
12-Jan-2021 |
AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> |
drm/msm/dpu: Allow specifying features and sblk in DSPP_BLK macro The DSPP_BLK macro was ad-hoc made for SC7180, but this is wrong because not all of the DPU DSPP versions can use the same DSPP block configuration, and not all of them have got the same features. For this reason, add two more params to the DSPP_BLK macro, so that it is possible to specify the feature mask and the sblk config for each DSPP. Fixes: 4259ff7ae509 ("drm/msm/dpu: add support for pcc color block in dpu driver") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
|
#
731806da |
|
12-Jan-2021 |
AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> |
drm/msm/dpu: Add prog_fetch_lines_worst_case to INTF_BLK macro Not all DPU interface sub-block versions need the same value for prog_fetch_lines_worst_case: add this to the INTF_BLK macro, so that it becomes possible to vary it for other INTF versions. For example, this is needed to implement support for older SoCs, like MSM8998 and SDM630/660 and most probably will also be needed for future SoCs. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
|
#
b8dab65b |
|
12-Jan-2021 |
AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> |
drm/msm/dpu: Move DPU_SSPP_QOS_8LVL bit to SDM845 and SC7180 masks Not all DPU versions that are supported in this driver are supposed to have a 8-Levels VIG QoS setting. Move this flag to SDM845 and SC7180 specific masks. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
|
#
05ae91d9 |
|
02-Nov-2020 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: enable DSPP support on SM8[12]50 Add support for color correction sub block on SM8150 and SM8250. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
|
#
09c7e370 |
|
23-Nov-2020 |
Lee Jones <lee.jones@linaro.org> |
drm/msm/disp/dpu1/dpu_hw_catalog: Move definitions to the only place they are used These tables are not large or overbearing, so moving them into the source file seems like the right thing to do. The alternative is to use __maybe_unused, which is undesirable. Fixes the following W=1 kernel build warning(s): In file included from drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c:11: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog_format.h:7:23: warning: ‘qcom_compressed_supported_formats’ defined but not used [-Wunused-const-variable=] 7 | static const uint32_t qcom_compressed_supported_formats[] = { | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog_format.h:48:23: warning: ‘plane_formats_yuv’ defined but not used [-Wunused-const-variable=] 48 | static const uint32_t plane_formats_yuv[] = { | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog_format.h:17:23: warning: ‘plane_formats’ defined but not used [-Wunused-const-variable=] 17 | static const uint32_t plane_formats[] = { | ^~~~~~~~~~~~~ Cc: Rob Clark <robdclark@gmail.com> Cc: Sean Paul <sean@poorly.run> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: linux-arm-msm@vger.kernel.org Cc: dri-devel@lists.freedesktop.org Cc: freedreno@lists.freedesktop.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
|
#
14bcdfe4 |
|
23-Nov-2020 |
Lee Jones <lee.jones@linaro.org> |
drm/msm/disp/dpu1/dpu_hw_catalog: Remove duplicated initialisation of 'max_linewidth' Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c:124:19: warning: initialized field overwritten [-Woverride-init] drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c:124:19: note: (near initialization for ‘sm8250_dpu_caps.max_linewidth’) Cc: Rob Clark <robdclark@gmail.com> Cc: Sean Paul <sean@poorly.run> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: linux-arm-msm@vger.kernel.org Cc: dri-devel@lists.freedesktop.org Cc: freedreno@lists.freedesktop.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
|
#
4369c93c |
|
22-Oct-2020 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: initial support for merge3D hardware block Add initial support for merge3D hardware block on SM8[12]50. Merge3D is reposible for merging contents of two LMs (two PPs) into single interface. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
|
#
c33b7c03 |
|
16-Jul-2020 |
Kalyan Thota <kalyan_t@codeaurora.org> |
drm/msm/dpu: add support for clk and bw scaling for display This change adds support to scale src clk and bandwidth as per composition requirements. Interconnect registration for bw has been moved to mdp device node from mdss to facilitate the scaling. Changes in v1: - Address armv7 compilation issues with the patch (Rob) Signed-off-by: Kalyan Thota <kalyan_t@codeaurora.org> Reviewed-by: Rob Clark <robdclark@chromium.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
|
#
af776a3e |
|
10-Jul-2020 |
Jonathan Marek <jonathan@marek.ca> |
drm/msm/dpu: add SM8250 to hw catalog This brings up basic video mode functionality for SM8250 DPU. Command mode and dual mixer/intf configurations are not working, future patches will address this. Scaler functionality and multiple planes is also untested. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>
|
#
386fced3 |
|
10-Jul-2020 |
Jonathan Marek <jonathan@marek.ca> |
drm/msm/dpu: add SM8150 to hw catalog This brings up basic video mode functionality for SM8150 DPU. Command mode and dual mixer/intf configurations are not working, future patches will address this. Scaler functionality and multiple planes is also untested. Signed-off-by: Jonathan Marek <jonathan@marek.ca> [fixup max_linewidth warning] Signed-off-by: Rob Clark <robdclark@chromium.org>
|
#
cace3ac4 |
|
10-Jul-2020 |
Jonathan Marek <jonathan@marek.ca> |
drm/msm/dpu: don't use INTF_INPUT_CTRL feature on sdm845 The INTF_INPUT_CTRL feature is not available on sdm845, so don't set it. This also adds separate feature bits for INTF (based on downstream) instead of using CTL feature bit for it, and removes the unnecessary NULL check in the added bind_pingpong_blk function. Fixes: 73bfb790ac786ca55fa2786a06f59 ("msm:disp:dpu1: setup display datapath for SC7180 target") Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>
|
#
7e9d4cdd |
|
10-Jul-2020 |
Jonathan Marek <jonathan@marek.ca> |
drm/msm/dpu: move some sspp caps to dpu_caps This isn't something that ever changes between planes, so move it to dpu_caps struct. Making this change will allow more re-use in the "SSPP sub blocks config" part of the catalog, in particular when adding support for SM8150 and SM8250 which have different max_linewidth. This also sets max_hdeci_exp/max_vdeci_exp to 0 for sc7180, as decimation is not supported on the newest DPU versions. (note that decimation is not implemented, so this changes nothing) Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>
|
#
7b149f2b |
|
25-Jun-2020 |
Kalyan Thota <kalyan_t@codeaurora.org> |
drm/msm/dpu: enumerate second cursor pipe for external interface Setup an RGB HW pipe as cursor which can be used on secondary interface. For SC7180 2 HW pipes are enumerated as cursors 1 - primary interface 2 - secondary interface Signed-off-by: Kalyan Thota <kalyan_t@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
|
#
1cb2c4a2 |
|
01-Jun-2020 |
Rob Clark <robdclark@chromium.org> |
Revert "drm/msm/dpu: add support for clk and bw scaling for display" This is causing multiple armv7 missing do_div() errors, so lets drop it for now. This reverts commit 04d9044f6c577948609c03b4e33b8fbc8b87c4b1. Cc: Kalyan Thota <kalyan_t@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
|
#
71dc6c08 |
|
04-May-2020 |
Krishna Manikandan <mkrishn@codeaurora.org> |
drm/msm/dpu: update bandwidth threshold check Maximum allowed bandwidth has no dependency on the type of panel used. Hence, cleanup the code to use max_bw_high as the threshold value for bandwidth checks. Update the maximum allowed bandwidth as 6.8Gbps for SC7180 target. Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
|
#
04d9044f |
|
01-Apr-2020 |
Kalyan Thota <kalyan_t@codeaurora.org> |
drm/msm/dpu: add support for clk and bw scaling for display This change adds support to scale src clk and bandwidth as per composition requirements. Interconnect registration for bw has been moved to mdp device node from mdss to facilitate the scaling. Signed-off-by: Kalyan Thota <kalyan_t@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
|
#
4259ff7a |
|
24-Mar-2020 |
Kalyan Thota <kalyan_t@codeaurora.org> |
drm/msm/dpu: add support for pcc color block in dpu driver This change adds support for color correction sub block for SC7180 device. Signed-off-by: Kalyan Thota <kalyan_t@codeaurora.org> Tested-by: Fritz Koenig <frkoenig@google.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
|
#
e47616df |
|
24-Mar-2020 |
Kalyan Thota <kalyan_t@codeaurora.org> |
drm/msm/dpu: add support for color processing blocks in dpu driver This change adds support to configure dspp blocks in the dpu driver. Macro description of the changes coming in this patch. 1) Add dspp definitions in the hw catalog. 2) Add capability to reserve dspp blocks in the display data path. 3) Attach the reserved block to the encoder. Signed-off-by: Kalyan Thota <kalyan_t@codeaurora.org> Tested-by: Fritz Koenig <frkoenig@google.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
|
#
b75ab05a |
|
27-Nov-2019 |
Shubhashree Dhar <dhar@codeaurora.org> |
msm:disp:dpu1: add scaler support on SC7180 display Add scaler support for display driver. This patch has dependency on the below series https://patchwork.kernel.org/patch/11260267/ Co-developed-by: Raviteja Tamatam <travitej@codeaurora.org> Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org> Signed-off-by: Shubhashree Dhar <dhar@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
|
#
42a558b7 |
|
25-Nov-2019 |
Kalyan Thota <kalyan_t@codeaurora.org> |
msm:disp:dpu1: add mixer selection for display topology mixer selection in the display topology is based on multiple factors 1) mixers available in the hw 2) interfaces to be enabled 3) merge capability change will pickup mixer as per the topology need. Signed-off-by: Kalyan Thota <kalyan_t@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
|
#
73bfb790 |
|
25-Nov-2019 |
Kalyan Thota <kalyan_t@codeaurora.org> |
msm:disp:dpu1: setup display datapath for SC7180 target Add changes to setup display datapath on SC7180 target. Changes in v1: - Add changes to support ctl_active on SC7180 target. - While selecting the number of mixers in the topology consider the interface width. Changes in v2: - Spawn topology mixer selection into separate patch (Rob Clark). - Add co-developed-by tags in the commit msg (Stephen Boyd). Changes in v3: - Fix kernel checkpatch errors in v2. This patch has dependency on the below series https://patchwork.kernel.org/patch/11253747/ Co-developed-by: Shubhashree Dhar <dhar@codeaurora.org> Signed-off-by: Shubhashree Dhar <dhar@codeaurora.org> Co-developed-by: Raviteja Tamatam <travitej@codeaurora.org> Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org> Signed-off-by: Kalyan Thota <kalyan_t@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
|
#
7bdc0c4b |
|
25-Nov-2019 |
Kalyan Thota <kalyan_t@codeaurora.org> |
msm:disp:dpu1: add support for display for SC7180 target Add display hw catalog changes for SC7180 target. Changes in v1: - Configure register offsets and capabilities for the display hw blocks. Changes in v2: - mdss_irq data type has changed in the dependent patch, accommodate the necessary changes. - Add co-developed-by tags in the commit msg (Stephen Boyd). Changes in v3: - fix kernel checkpatch errors in v2 Changes in v4: - move documentation into seperate patch (Rob Herring). This patch has dependency on the below series https://patchwork.kernel.org/patch/11253647/ Co-developed-by: Shubhashree Dhar <dhar@codeaurora.org> Signed-off-by: Shubhashree Dhar <dhar@codeaurora.org> Co-developed-by: Raviteja Tamatam <travitej@codeaurora.org> Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org> Signed-off-by: Kalyan Thota <kalyan_t@codeaurora.org> [rebase on hw catalog const'ification, and add more const's] Signed-off-by: Rob Clark <robdclark@chromium.org>
|
#
0846cca3 |
|
20-Nov-2019 |
Shubhashree Dhar <dhar@codeaurora.org> |
msm: disp: dpu1: add support to access hw irqs regs depending on revision Current code assumes that all the irqs registers offsets can be accessed in all the hw revisions; this is not the case for some targets that should not access some of the irq registers. This change adds the support to selectively remove the irqs that are not supported in some of the hw revisions. Changes in v1: - Add support to selectively remove the hw irqs that are not not supported. Changes in v2: - Remove unrelated changes. Changes in v3: - Remove change-id (Stephen Boyd). - Add colon in variable description to match kernel-doc (Stephen Boyd). - Change macro-y way of variable description (Jordon Crouse). - Remove unnecessary if checks (Jordon Crouse). - Remove extra blank line (Jordon Crouse). Changes in v4: - Remove checkpatch errors. Signed-off-by: Shubhashree Dhar <dhar@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
|
#
abda0d92 |
|
19-Nov-2019 |
Stephen Boyd <swboyd@chromium.org> |
drm/msm/dpu: Mark various data tables as const These structures look like a bunch of data tables that aren't going to change after boot. Let's move them to the const RO section of memory so that they can't be modified at runtime on modern machines. Signed-off-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
|
#
97fb5e8d |
|
29-May-2019 |
Thomas Gleixner <tglx@linutronix.de> |
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 284 Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 and only version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 294 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141900.825281744@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
#
e6b63a7b |
|
11-Dec-2018 |
Fritz Koenig <frkoenig@google.com> |
drm/msm/dpu: Use simple list for plane format init Simplify the initilization of a list of formats by passing the list in directly instead of copying it from one structure to another. Signed-off-by: Fritz Koenig <frkoenig@google.com> Signed-off-by: Sean Paul <seanpaul@chromium.org>
|
#
9816b226 |
|
05-Sep-2018 |
Jeykumar Sankaran <jsanka@codeaurora.org> |
drm/msm/dpu: remove cdm block support from resource manager Support for CDM block is not present in DPU. Remove CDM handlers from resource manager. changes in v4: - Introduced in the series changes in v5: - Remove catalog references to CDM (Sean) Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
|
#
b033def8 |
|
05-Sep-2018 |
Jeykumar Sankaran <jsanka@codeaurora.org> |
drm/msm/dpu: clean up destination scaler residue Destination scaling(DS) is a Snapdragon hardware feature to scale up the display ROI after layer blending. DPU driver doesn't support programming of DS blocks yet. This change cleans up the residual code present in catalog and RM for DS block handling. Support for the same can be added back when the feature is formally implemented. changes in v5: - introduced in the series Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
|
#
07ca1fc0 |
|
22-Aug-2018 |
Sravanthi Kollukuduru <skolluku@codeaurora.org> |
drm/msm/dpu: enable cursor plane on dpu Reserve DMA pipe for cursor plane and attach it to the crtc during the initialization. Changes in V2: None Signed-off-by: Sravanthi Kollukuduru <skolluku@codeaurora.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
|
#
fba33cae |
|
26-Jul-2018 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm/disp/dpu: Mark a handful of functions as static Mark a number of static functions that are only unsed in the file that defines them and remove the prototypes from the headers where needed. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
|
#
25fdd593 |
|
27-Jun-2018 |
Jeykumar Sankaran <jsanka@codeaurora.org> |
drm/msm: Add SDM845 DPU support SDM845 SoC includes the Mobile Display Sub System (MDSS) which is a top level wrapper consisting of Display Processing Unit (DPU) and display peripheral modules such as Display Serial Interface (DSI) and DisplayPort (DP). MDSS functions essentially as a back-end composition engine. It blends video and graphic images stored in the frame buffers and scans out the composed image to a display sink (over DSI/DP). The following diagram represents hardware blocks for a simple pipeline (two planes are present on a given crtc which is connected to a DSI connector): MDSS +---------------------------------+ | +-----------------------------+ | | | DPU | | | | +--------+ +--------+ | | | | | SSPP | | SSPP | | | | | +----+---+ +----+---+ | | | | | | | | | | +----v-----------v---+ | | | | | Layer Mixer (LM) | | | | | +--------------------+ | | | | +--------------------+ | | | | | PingPong (PP) | | | | | +--------------------+ | | | | +--------------------+ | | | | | INTERFACE (VIDEO) | | | | | +---+----------------+ | | | +------|----------------------+ | | | | | +------|---------------------+ | | | | DISPLAY PERIPHERALS | | | | +---v-+ +-----+ | | | | | DSI | | DP | | | | | +-----+ +-----+ | | | +----------------------------+ | +---------------------------------+ The number of DPU sub-blocks (i.e. SSPPs, LMs, PP blocks and INTFs) depends on SoC capabilities. Overview of DPU sub-blocks: --------------------------- * Source Surface Processor (SSPP): Refers to any of hardware pipes like ViG, DMA etc. Only ViG pipes are capable of performing format conversion, scaling and quality improvement for source surfaces. * Layer Mixer (LM): Blend source surfaces together (in requested zorder) * PingPong (PP): This block controls frame done interrupt output, EOL and EOF generation, overflow/underflow control. * Display interface (INTF): Timing generator and interface connecting the display peripherals. DRM components mapping to DPU architecture: ------------------------------------------ PLANEs maps to SSPPs CRTC maps to LMs Encoder maps to PPs, INTFs Data flow setup: --------------- MDSS hardware can support various data flows (e.g.): - Dual pipe: Output from two LMs combined to single display. - Split display: Output from two LMs connected to two separate interfaces. The hardware capabilities determine the number of concurrent data paths possible. Any control path (i.e. pipeline w/i DPU) can be routed to any of the hardware data paths. A given control path can be triggered, flushed and controlled independently. Changes in v3: - Move msm_media_info.h from uapi to dpu/ subdir - Remove preclose callback dpu (it's handled in core) - Fix kbuild warnings with parent_ops - Remove unused functions from dpu_core_irq - Rename mdss_phys to mdss - Rename mdp_phys address space to mdp - Drop _phys from vbif and regdma binding names Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org> Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org> Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rajesh Yadav <ryadav@codeaurora.org> Signed-off-by: Sravanthi Kollukuduru <skolluku@codeaurora.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> [robclark minor rebase] Signed-off-by: Rob Clark <robdclark@gmail.com>
|