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59be9024 |
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09-Nov-2023 |
Mika Kahola <mika.kahola@intel.com> |
drm/i915/mtl: C20 state verification Add state verification for C20 as we have one for C10. V2: Use abstractation of HW readout (Gustavo) Drop MPLLA/B from message for TX and CMN parameters (Gustavo) Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> (v1,v2) Signed-off-by: Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231109112148.309669-1-mika.kahola@intel.com
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0a0f7935 |
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18-Oct-2023 |
Lucas De Marchi <lucas.demarchi@intel.com> |
drm/i915/display: Abstract C10/C20 pll calculation As done with the hw readout, properly abstract the C10/C20 phy details inside intel_cx0_phy.c. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231018222831.4132968-3-lucas.demarchi@intel.com
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685a4fff |
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18-Oct-2023 |
Lucas De Marchi <lucas.demarchi@intel.com> |
drm/i915/display: Abstract C10/C20 pll hw readout intel_cx0_phy.[ch] should contain the details about C10/C20, not leaking it to the rest of the driver. Start abstracting this by exporting a single PLL hw readout that handles the differences between C20 and C10 internally to that compilation unit. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231018222831.4132968-2-lucas.demarchi@intel.com
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335aa752 |
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04-Oct-2023 |
Ville Syrjälä <ville.syrjala@linux.intel.com> |
drm/i915: Simplify snps/c10x DPLL state checker calling convetion Passing in the atomic state + crtc state is a bit weird. The latter can be just the crtc (which is the normal calling convention used in a lot of other places). Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231004155607.7719-9-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
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c788479a |
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04-Oct-2023 |
Ville Syrjälä <ville.syrjala@linux.intel.com> |
drm/i915: Constify the snps/c10x PLL state checkers State checkers should never modify the crtc states, so make them const. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231004155607.7719-8-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
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f067976e |
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21-Sep-2023 |
Jani Nikula <jani.nikula@intel.com> |
drm/i915/cx0: prefer forward declarations over includes Avoid including the world from headers when forward declarations suffice. Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230921155325.3851197-1-jani.nikula@intel.com
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9124f2b7 |
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13-Jun-2023 |
Gustavo Sousa <gustavo.sousa@intel.com> |
drm/i915: Remove prototype for intel_cx0_phy_ddi_vswing_sequence() That function is not defined anywhere. Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> Reviewed-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230613214658.1099759-1-gustavo.sousa@intel.com
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6f0423b0 |
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27-Apr-2023 |
Mika Kahola <mika.kahola@intel.com> |
drm/i915/mtl: Power up TCSS Add register writes to enable powering up Type-C subsystem i.e. TCSS. For MeteorLake we need to request TCSS to power up and check the TCSS power state after 500 us. In addition, for PICA we need to set/clear the Type-C PHY ownnership bit when Type-C device is connected/disconnected. Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230428095433.4109054-11-mika.kahola@intel.com
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7dee06bc |
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27-Apr-2023 |
Mika Kahola <mika.kahola@intel.com> |
drm/i915/mtl: Readout Thunderbolt HW state Readout hw state for Thunderbolt. Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230428095433.4109054-9-mika.kahola@intel.com
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73fc3abc |
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27-Apr-2023 |
Mika Kahola <mika.kahola@intel.com> |
drm/i915/mtl: Enabling/disabling sequence Thunderbolt pll Enabling and disabling sequence for Thunderbolt PLL. Bspec: 64568 v2: Use intel_de_wait_for_register() (RK) Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230428095433.4109054-8-mika.kahola@intel.com
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f1f9e627 |
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27-Apr-2023 |
Mika Kahola <mika.kahola@intel.com> |
drm/i915/mtl: C20 port clock calculation Calculate port clock with C20 phy. BSpec: 64568 Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230428095433.4109054-5-mika.kahola@intel.com
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f968a253 |
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27-Apr-2023 |
Mika Kahola <mika.kahola@intel.com> |
drm/i915/mtl: Dump C20 pll hw state As we already do with C10 chip, let's dump the pll hw state for C20 as well. Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230428095433.4109054-4-mika.kahola@intel.com
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929f527a |
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27-Apr-2023 |
Mika Kahola <mika.kahola@intel.com> |
drm/i915/mtl: C20 HW readout Create a table for C20 DP1.4, DP2.0 and HDMI2.1 rates. The PLL settings are based on table, not for algorithmic alternative. For DP 1.4 only MPLLB is in use. Once register settings are done, we read back C20 HW state. BSpec: 64568 v2: Updated pll tables (RK) MPLLB selection fix (RK) Signed-off-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230428095433.4109054-3-mika.kahola@intel.com
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5836bc5f |
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13-Apr-2023 |
Radhakrishna Sripada <radhakrishna.sripada@intel.com> |
drm/i915/mtl: Add C10 phy programming for HDMI Like DG2, we still don't have a proper algorithm that can be used for calculating PHY settings, but we do have tables of register values for a handful of the more common link rates. Some support is better than none, so let's go ahead and add/use these tables when we can, and also add some logic to hdmi_port_clock_valid() to filter the modelist to just the modes we can actually support with these link rates. Hopefully we'll have a proper / non-encumbered algorithm to calculate these registers by the time we upstream and we'll be able to replace this patch with something more general purpose. Bspec: 64568 v2: Rebasing with Clint's HDMI C10 PLL tables (Mika) v3: Remove the extra hdmi clock check pruning. Cc: Imre Deak <imre.deak@intel.com> Cc: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by: Clint Taylor <Clinton.A.Taylor@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230413212443.1504245-8-radhakrishna.sripada@intel.com
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ea8af87a |
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13-Apr-2023 |
Mika Kahola <mika.kahola@intel.com> |
drm/i915/mtl: Add vswing programming for C10 phys C10 phys uses direct mapping internally for voltage and pre-emphasis levels. Program the levels directly to the fields in the VDR Registers. Bspec: 65449 v2: From table "C10: Tx EQ settings for DP 1.4x" it shows level 1 and preemphasis 1 instead of two times of level 1 preemphasis 0. Fix this in the driver code as well. v3: VSwing update (Clint) v4: Add vboost termination ctl programming(Imre) Fix tx llogic and other nits Restrict C10 vdr ctl register access for C10 phy(RK) v5: Program vboots, termination ctl for both lanes(Imre) Cc: Imre Deak <imre.deak@intel.com> Cc: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Clint Taylor <Clinton.A.Taylor@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com>(v3) Link: https://patchwork.freedesktop.org/patch/msgid/20230413212443.1504245-5-radhakrishna.sripada@intel.com
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51390cc0 |
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13-Apr-2023 |
Radhakrishna Sripada <radhakrishna.sripada@intel.com> |
drm/i915/mtl: Add Support for C10 PHY message bus and pll programming XELPDP has C10 and C20 phys from Synopsys to drive displays. Each phy has a dedicated PIPE 5.2 Message bus for configuration. This message bus is used to configure the phy internal registers. XELPDP has C10 phys to drive output to the EDP and the native output from the display engine. Add structures, programming hardware state readout logic. Port clock calculations are similar to DG2. Use the DG2 formulae to calculate the port clock but use the relevant pll signals. Note: PHY lane 0 is always used for PLL programming. Add sequences for C10 phy enable/disable phy lane reset, powerdown change sequence and phy lane programming. Bspec: 64539, 64568, 64599, 65100, 65101, 65450, 65451, 67610, 67636 v2: Squash patches related to C10 phy message bus and pll programming support (Jani) Move register definitions to a new file i.e. intel_cx0_reg_defs.h (Jani) Move macro definitions (Jani) DP rates as separate patch (Jani) Spin out xelpdp register definitions into a separate file (Jani) Replace macro to select registers based on phy lane with function calls (Jani) Fix styling issues (Jani) Call XELPDP_PORT_P2M_MSGBUS_STATUS() with port instead of phy (Lucas) v3: Move clear request flag into try-loop v4: On PHY idle change drm_err_once() as drm_dbg_kms() (Jani) use __intel_de_wait_for_register() instead of __intel_wait_for_register and uncomment intel_uncore.h (Jani) Add DP-alt support for PHY lane programming (Khaled) v4: Add tx and cmn on c10mpllb_state (Imre) Add missing waits for pending transactions between two message bus writes (Imre) General cleanups and simplifications (Imre) v5: Few nit cleanups from rev4 (imre) s/dev_priv/i915/ , s/c10mpllb/c10pll/ (RK) Rebase v6: Move the mtl code from intel_c10pll_calc_port_clock to mtl function Fix typo in comment for REG_FIELD_PREP8 definition(Imre) Cc: Mika Kahola <mika.kahola@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Uma Shankar <uma.shankar@intel.com> Cc: Gustavo Sousa <gustavo.sousa@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> (v4) Link: https://patchwork.freedesktop.org/patch/msgid/20230413212443.1504245-4-radhakrishna.sripada@intel.com
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