drm/i915/gen12: Update combo PHY init sequence

The bspec was updated with a minor change to the 'DCC mode select'
setting to be programmed during combo PHY initialization.

v2:
- Keep the opencoded rmw behavior instead of switching to
intel_de_rmw(). We need to read from a _LN register, but write to
the _GRP register to update all lanes.

Bspec: 49291
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230221201836.2886794-1-matthew.d.roper@intel.com

drm/i915: Move combo PHY registers to their own header

These registers are only needed in a couple files and on specific
platforms; let's keep them separate from the general register pool.

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220111051600.3429104-10-matthew.d.roper@intel.com