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ca5c636d |
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17-Sep-2021 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: add poison mode query for DF (v2) Add ras poison mode query interface for DF. v2: replace RREG32_PCIE with RREG32_SOC15. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1f625659 |
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18-May-2021 |
Mukul Joshi <mukul.joshi@amd.com> |
drm/amdgpu: Query correct register for DF hashing on Aldebaran For Aldebaran, driver needs to query DramMegaBaseAddress to check if DF hashing is enabled. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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a6c44d25 |
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16-Jan-2020 |
John Clements <john.clements@amd.com> |
drm/amdgpu: added support to get mGPU DRAM base resolves issue with RAS error injection in mGPU configuration Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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ae99fc35 |
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09-Jan-2020 |
Joseph Greathouse <Joseph.Greathouse@amd.com> |
drm/amdgpu: add defines for DF and TCP Hashing On Arcturus, we need TC channel hashing, which is set by the driver, to match DF hashing, which is set by VBIOS. To match these, we plan to query the DF information and then properly set the TC configuration bits to match them. This patch adds the required fields to register definitions in preparation for a future patch which will use them. Signed-off-by: Joseph Greathouse <Joseph.Greathouse@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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5e9eec07 |
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12-Dec-2019 |
Jonathan Kim <jonathan.kim@amd.com> |
drm/amdgpu: add perfmons accessible during df c-states During DF C-State, Perfmon counters outside of range 1D700-1D7FF will encounter SLVERR affecting xGMI performance monitoring. PerfmonCtr[7:4] is being added to avoid SLVERR during read since it falls within this range. PerfmonCtl[7:4] is being added in order to arm PerfmonCtr[7:4]. Since PerfmonCtl[7:4] exists outside of range 1D700-1D7FF, DF routines will be enabled to opportunistically re-arm PerfmonCtl[7:4] on retry after SLVERR. Signed-off-by: Jonathan Kim <Jonathan.Kim@amd.com> Acked-by: Alex Deucher <Alexander.Deucher@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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c52e7ebc |
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10-Jul-2019 |
Jonathan Kim <jonathan.kim@amd.com> |
drm/amdgpu: exposing fica registers to df offsets exposing fica registers to poll df pie data for xgmi error counters for vega20. Signed-off-by: Jonathan Kim <Jonathan.Kim@amd.com> Reviewed-by: Alexander Deucher <Alexander.Deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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992af942 |
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02-May-2019 |
Jonathan Kim <jonathan.kim@amd.com> |
drm/amdgpu: add df perfmon regs and funcs for xgmi v6: Squash in warning fix (Colin Ian King) v5: Fix warnings (Alex) v4: fixed mixed delaration and code warnings and minor errors v3: exposing df funcs in amdgpu_df_funcs in amdgpu.h v2: moving permonctl/perfmonctr from default to offset - adding df perfmonctl and perfmonctr registers for df counters - adding df funcs to set perfmonctl and get perfmonctr for df and xgmi counters - exposing df funcs in amdgpu_df_funcs Signed-off-by: Jonathan Kim <jonathan.kim@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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9883e9d7 |
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14-May-2018 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add df 3.6 headers Needed for vega20. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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