#
ddc23e6e |
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08-Feb-2024 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/psp: update define to better align with its meaning MEM_TRAINING_ENCROACHED_SIZE is for BIST training data. It's not memory type specific. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4e8303cf |
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11-Sep-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Use function for IP version check Use an inline function for version check. Gives more flexibility to handle any format changes. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2d39c7ae |
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03-Jan-2023 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: Load PSP microcode during early_init Simplifies the code so that all PSP versions will get the firmware name from `amdgpu_ucode_ip_version_decode` and then use this filename to load microcode as part of the early_init process. Any failures will cause the driver to fail to probe before the firmware framebuffer has been removed. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
994a9744 |
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03-Jan-2023 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: Parse both v1 and v2 TA microcode headers using same function Several IP versions duplicate code and can't use the common helpers. Move this code into a single function so that the helpers can be used. v2: squash in fix from Mario to remove duplicate ta parsing Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
aec3bb3a |
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16-Nov-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: make psp_ring_init common All of the IP specific versions are the same now, so we can just use a common function. Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c4381d0e |
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12-Jan-2022 |
Bokun Zhang <Bokun.Zhang@amd.com> |
drm/amdgpu: Add interface to load SRIOV cap FW - Add interface to load SRIOV cap FW. If the FW does not exist, simply skip this FW loading routine. This FW will only be loaded under SRIOV. Other driver configuration will not be affected. By adding this interface, it will make us easier to prepare SRIOV Linux guest driver for different users. - Update sysfs interface to read cap FW version. - Refactor PSP FW loading routine under SRIOV to use a unified SWITCH statement instead of using IF statement - Remove redundant amdgpu_sriov_vf() check in FW loading routine Acked-by: Monk Liu <monk.liu@amd.com> Acked-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Bokun Zhang <Bokun.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
fd5256cb |
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08-Dec-2021 |
yipechai <YiPeng.Chai@amd.com> |
drm/amdgpu: Remove the redundant code of psp bootloader functions The psp bootloader functions code of psp_v13_0.c had been optimized before. According the code style of psp_v13_0.c to remove the redundant code of psp_v11_0.c. v2: squash in drop unused variable (Alex) Signed-off-by: yipechai <YiPeng.Chai@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4320e6f8 |
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21-Oct-2021 |
Candice Li <candice.li@amd.com> |
drm/amdgpu: Update TA version output in driver TA version should only be displayed in firmware version column. Signed-off-by: Candice Li <candice.li@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c58a863b |
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08-Oct-2021 |
Guchun Chen <guchun.chen@amd.com> |
drm/amdgpu: use adev_to_drm for consistency when accessing drm_device adev_to_drm is used everywhere, so improve recent changes when accessing drm_device pointer from amdgpu_device. Signed-off-by: Guchun Chen <guchun.chen@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4b3a624c |
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28-Sep-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: consolidate case statements IP_VERSION(11, 0, 13) does the exact same thing as IP_VERSION(11, 0, 12) so squash them together. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1d789535 |
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04-Oct-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: convert IP version array to include instances Allow us to query instances versions more cleanly. Instancing support is not consistent unfortunately. SDMA is a good example. Sienna cichlid has 4 total SDMA instances, each enumerated separately (HWIDs 42, 43, 68, 69). Arcturus has 8 total SDMA instances, but they are enumerated as multiple instances of the same HWIDs (4x HWID 42, 4x HWID 43). UMC is another example. On most chips there are multiple instances with the same HWID. This allows us to support both forms. v2: rebase v3: clarify instancing support Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e47868ea |
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04-Aug-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/psp_v11.0: convert to IP version checking Use IP versions rather than asic_type to differentiate IP version specific features. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
de3a1e33 |
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08-Sep-2021 |
Candice Li <candice.li@amd.com> |
drm/amdgpu: Unify PSP TA context Remove all TA binary structures and add the specific binary structure in struct ta_context. Signed-off-by: Candice Li <candice.li@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
6457205c |
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12-Aug-2021 |
Candice Li <candice.li@amd.com> |
drm/amd/amdgpu: consolidate PSP TA context Signed-off-by: Candice Li <candice.li@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
222e0a71 |
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21-Jul-2021 |
Candice Li <candice.li@amd.com> |
drm/amd/amdgpu: add consistent PSP FW loading size checking Signed-off-by: Candice Li <candice.li@amd.com> Reviewed-by: John Clements <John.Clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
25a3e8ac |
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16-Jul-2021 |
Andrey Grodzovsky <andrey.grodzovsky@amd.com> |
drm/amdgpu: Switch to VRAM buffer for USBC PD FW. System memory-based implementation for updating the USBCPD is deprecated for so switching to LFB based implementation for all the ASICs. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Alexander Deucher <Alexander.Deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
29b4ac0e |
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08-Jun-2021 |
YuBiao Wang <YuBiao.Wang@amd.com> |
drm/amdgpu: reset psp ring wptr during ring_create [Why] psp ring wptr is not initialized properly in ring_create, which would lead to psp failure after several gpu reset. [How] Set ring_wptr to zero in psp_ring_create. Signed-off-by: YuBiao Wang <YuBiao.Wang@amd.com> Reviewed-by: Horace Chen <horace.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f1688bd6 |
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17-Mar-2021 |
Victor Zhao <Victor.Zhao@amd.com> |
drm/amd/amdgpu:save psp ring wptr to avoid attack [Why] When some tools performing psp mailbox attack, the readback value of register can be a random value which may break psp. [How] Use a psp wptr cache machanism to aovid the change made by attack. v2: unify change and add detailed reason Signed-off-by: Victor Zhao <Victor.Zhao@amd.com> Signed-off-by: Jingwen Chen <Jingwen.Chen2@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f89f8c6b |
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12-May-2021 |
Andrey Grodzovsky <andrey.grodzovsky@amd.com> |
drm/amdgpu: Guard against write accesses after device removal This should prevent writing to memory or IO ranges possibly already allocated for other uses after our device is removed. v5: Protect more places wher memcopy_to/form_io takes place Protect IB submissions v6: Switch to !drm_dev_enter instead of scoping entire code with brackets. v7: Drop guard of HW ring commands emission protection since they are in GART and not in MMIO. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210512142648.666476-10-andrey.grodzovsky@amd.com
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#
ac87f942 |
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07-May-2021 |
Aurabindo Pillai <aurabindo.pillai@amd.com> |
drm/amd/display: Enable HDCP for Beige Goby [Why&How] Add beige_goby_ta.bin to module firmware table and call psp init for TA Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c0729819 |
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10-Nov-2020 |
Chengming Gui <Jack.Gui@amd.com> |
drm/amd/amdgpu: add psp support for beige_goby add general PSP support for beige_goby Signed-off-by: Chengming Gui <Jack.Gui@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2370eba9 |
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17-Mar-2021 |
Victor Zhao <Victor.Zhao@amd.com> |
drm/amd/amdgpu:save psp ring wptr to avoid attack [Why] When some tools performing psp mailbox attack, the readback value of register can be a random value which may break psp. [How] Use a psp wptr cache machanism to aovid the change made by attack. v2: unify change and add detailed reason Signed-off-by: Victor Zhao <Victor.Zhao@amd.com> Signed-off-by: Jingwen Chen <Jingwen.Chen2@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4a497510 |
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18-Mar-2021 |
Bhaskar Chowdhury <unixbhaskar@gmail.com> |
drm/amdgpu: Fix a typo s/proces/process/ Signed-off-by: Bhaskar Chowdhury <unixbhaskar@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
7c4f2b23 |
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18-Mar-2021 |
Bhaskar Chowdhury <unixbhaskar@gmail.com> |
drm/amdgpu: Fix a typo s/traing/training/ ...Plus the entire sentence construction for better readability. Signed-off-by: Bhaskar Chowdhury <unixbhaskar@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
bf087285 |
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28-Dec-2020 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: switch hdp callback functions for hdp v5 Switch to use the HDP functions which unified on hdp structure instead of the scattered hdp callback functions. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
26f2daa4 |
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12-Dec-2020 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: drop ih reroute function from psp v11 For all the ASICs that integrate psp v11, vega20 doesn't support ih reroute. arcturus and later will allow kernel driver to program ih_cfg_index/data through mmio directly. navi1x and onwards will only support grb_ih_set command in sriov configuration. psp_v11_0_reroute_ih is not needed any more. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
3fdd2da0 |
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24-Nov-2020 |
Lee Jones <lee.jones@linaro.org> |
drm/amd/amdgpu/psp_v11_0: Make local function 'psp_v11_0_wait_for_bootloader()' static Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/psp_v11_0.c:223:5: warning: no previous prototype for ‘psp_v11_0_wait_for_bootloader’ [-Wmissing-prototypes] Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Hawking Zhang <Hawking.Zhang@amd.com> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2bdb8302 |
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11-Nov-2020 |
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> |
drm/amdgpu: Enable TA firmware loading for dimgrey_cavefish Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
8acedab0 |
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02-Nov-2020 |
Deepak R Varma <mh12gx2825@gmail.com> |
drm/amdgpu: use "*" adjacent to data name When declaring pointer data, the "*" symbol should be used adjacent to the data name as per the coding standards. This resolves following issues reported by checkpatch script: ERROR: "foo * bar" should be "foo *bar" ERROR: "foo * bar" should be "foo *bar" ERROR: "foo* bar" should be "foo *bar" ERROR: "(foo*)" should be "(foo *)" Signed-off-by: Deepak R Varma <mh12gx2825@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
78aafee7 |
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10-Oct-2020 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: remove ASD ucode init for dimgrey_cavefish dimgrey_cavefish has no ASD ucode currently, remove its initialization. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Jack Gui <Jack.Gui@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
aeec0744 |
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27-Jul-2020 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: skip reroute ih for some ASICs Add check before reroute ih setting, it's not supported by some ASICs. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
462c272b |
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02-Oct-2020 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: add psp support for dimgrey_cavefish(v2) General psp support for dimgrey_cavefish. v2: remove the checks for asd load and reroute ih. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
0a305e34 |
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23-Jul-2020 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: increase size of psp fw_name string(v2) Increase fw_name string size so longer chip name can be stored. v2: define macro for the length of psp fw name. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ed3b7353 |
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16-Sep-2020 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: enable psp support for vangogh This patch is to enable psp support for vangogh Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5120cb54 |
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27-Aug-2020 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: add TOC firmware support for apu (v3) APU needs load toc firmware for gfx10 series on psp front door loading. v2: rebase against latest code v3: clarify error message Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
24b763d0 |
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16-Sep-2020 |
Jiansong Chen <Jiansong.Chen@amd.com> |
drm/amdgpu: declare ta firmware for navy_flounder The firmware provided via MODULE_FIRMWARE appears in the module information. External tools(eg. dracut) may use the list of fw files to include them as appropriate in an initramfs, thus missing declaration will lead to request firmware failure in boot time. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tianci Yin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e60c27f1 |
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16-Sep-2020 |
Jiansong Chen <Jiansong.Chen@amd.com> |
drm/amdgpu: declare ta firmware for navy_flounder The firmware provided via MODULE_FIRMWARE appears in the module information. External tools(eg. dracut) may use the list of fw files to include them as appropriate in an initramfs, thus missing declaration will lead to request firmware failure in boot time. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tianci Yin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
0a668aee |
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28-Jul-2020 |
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> |
drm/amdgpu: parse ta firmware for navy_flounder Use the same case as sienna_cichlid Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
31e726ca |
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28-Jul-2020 |
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> |
drm/amdgpu: parse ta firmware for navy_flounder Use the same case as sienna_cichlid Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
6ece96a1 |
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16-Jul-2020 |
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> |
drm/amdgpu: load ta firmware for sienna cichlid call psp_int_ta_microcode() to parse the ta firmware. Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: John Clements <John.Clements@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c82b38ec |
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15-Apr-2020 |
Jiansong Chen <Jiansong.Chen@amd.com> |
drm/amdgpu: add psp support for navy_flounder Currently skip ASD FW loading and ih reroute per sienna_cichlid. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
70509057 |
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06-May-2020 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu/psp: support for loading PSP SPL fw Add support for loading SPL firmware. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
64f2d805 |
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05-Aug-2019 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: skip for reroute ih for sienna_cichlid psp ring init currently Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
344fed0b |
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22-Jul-2019 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu/psp: add psp support for sienna_cichlid Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
bfdb68ec |
|
23-Apr-2020 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: skip ASD fw load for sienna_cichlid Skip ASD FW load for sienna_cichlid currently. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
963cee55 |
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21-May-2020 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: change memory training to common function Change memory training init and finit a common function, as it only have software behavior do not relay on the IP version of PSP. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
999a69e2 |
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04-May-2020 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: switch to common rlc_autoload helper drop IP specific psp function for rlc autoload since the autoload_supported was introduced to mark ASICs that support rlc_autoload Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c797c583 |
|
04-May-2020 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: drop unused ras ta helper function cure posion command was replaced by ras recovery solution and was not a formal command supported by ras ta anymore Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
001a0a95 |
|
04-May-2020 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: switch to common ras ta helper TRIGGER_ERROR is common ras ta command for all the ASICs that support RAS feature. switch to common helper to avoid duplicate implementation per IP generation Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
35ccba4e |
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04-May-2020 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: switch to common xgmi ta helpers get_hive_id/get_node_id/get_topology_info/set_topology_info are common xgmi command supported by TA for all the ASICs that support xgmi link. They should be implemented as common helper functions to avoid duplicated code per IP generation Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1a0f3667 |
|
21-Apr-2020 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu: ignore TA ucode for SRIOV Signed-off-by: Monk Liu <Monk.Liu@amd.com> Acked-by: Yintian Tao <yttao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
893d14cb |
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20-Apr-2020 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: switch to helper function to init sos ucode call common helper function to init sos ucode, instead of duplicate codes per ip version Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f4503f9e |
|
20-Apr-2020 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: switch to helper function to init asd ucode call common helper function to initialize asd ucode Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
bc9fb7e9 |
|
20-Apr-2020 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: retire unused check_fw_loading status The driver can't access UCODE_DATA/ADDR registers on production boards. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d4d27897 |
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20-Apr-2020 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: remove unnecessary tOS version check tOS version is available through debugfs interface Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a2676149 |
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20-Apr-2020 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: retire support_vmr_ring interface vmr ring is dedicated for sriov vf (i.e.guest driver in sriov), which is general communication interface between driver and psp fw accross all ip version. it is not correct to make it as ip specific callback. it is even worse to check specific tOS version per IP version (like psp_v11/v12). Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c2c6f816 |
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10-Mar-2020 |
John Clements <john.clements@amd.com> |
drm/amdgpu: resolve failed error inject msg invoking an error injection successfully will cause an at_event intterrupt that will occur before the invoke sequence can complete causing an invalid error Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0dc93fd1 |
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19-Dec-2019 |
Andrey Grodzovsky <andrey.grodzovsky@amd.com> |
drm/amdgpu: Add USBC PD FW load to PSP 11 Add the programming sequence. v2: Change donwload wait loop to more efficient. Move C2PMSG_CMD_GFX_USB_PD_FW_VER defintion v3: Fix lack of loop counter increment typo v4: Remove superflous status reg read Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f77a9c92 |
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23-Jan-2020 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu: cleanup some incorrect reg access for SRIOV 1) we shouldn't load PSP kdb and sys/sos for VF, they are supposed to be handled by hypervisor 2) ih reroute doesn't work on VF thus we should avoid calling it, besides VF should not use those PSP register sets for PF 3) shouldn't load SMU ucode under SRIOV, otherwise PSP would report error Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7044cb6c |
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27-Jan-2020 |
Stephen Rothwell <sfr@canb.auug.org.au> |
amdgpu: using vmalloc requires includeing vmalloc.h Fixes: 240c811ccde4 ("drm/amdgpu: fix VRAM partially encroached issue in GDDR6 memory training(V2)") Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
240c811c |
|
20-Jan-2020 |
Tianci.Yin <tianci.yin@amd.com> |
drm/amdgpu: fix VRAM partially encroached issue in GDDR6 memory training(V2) [why] In GDDR6 BIST training, a certain mount of bottom VRAM will be encroached by UMC, that causes problems(like GTT corrupted and page fault observed). [how] Saving the content of this bottom VRAM to system memory before training, and restoring it after training to avoid VRAM corruption. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Tianci.Yin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a2e4b418 |
|
09-Jan-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/psp: declare navi1x ta firmware So that it gets included in the initrd. At the moment this is optional firmware that contains support for HDCP. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
097dc53e |
|
03-Jan-2020 |
John Clements <john.clements@amd.com> |
drm/amdgpu: added function to wait for PSP BL availability reduced duplicate code increased wait time for PSP BL readiness Signed-off-by: John Clements <john.clements@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a7f4ba7a |
|
08-Nov-2019 |
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> |
drm/amd/display: Load TA firmware for navi10/12/14 load the ta firmware for navi10/12/14. This is already being done for raven/picasso and is needed for supporting hdcp on navi Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5bdd0b72 |
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18-Nov-2019 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: switch to common helper func for psp cmd submission Drop all the IP specific cmd_submit callback function and use the common helper instead Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
13a390a6 |
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18-Nov-2019 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: add psp funcs for ring write pointer read/write The ring write pointer regsiter update is the only part that is IP specific ones in psp_cmd_submit function. Add two callbacks for wptr read/write so that we unify the psp_cmd_submit function for all the ASICs. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
73469970 |
|
18-Oct-2019 |
Xiaojie Yuan <xiaojie.yuan@amd.com> |
drm/amdgpu/psp11: fix typo in comment Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d7e7f1ea |
|
18-Oct-2019 |
Xiaojie Yuan <xiaojie.yuan@amd.com> |
drm/amdgpu/psp11: wait for sOS ready for ring creation Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
367039bf |
|
30-Sep-2019 |
Tianci.Yin <tianci.yin@amd.com> |
drm/amdgpu/psp: add psp memory training implementation(v3) add memory training implementation code to save resume time. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> Signed-off-by: Tianci.Yin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a7d4c920 |
|
30-Sep-2019 |
Tianci.Yin <tianci.yin@amd.com> |
drm/amdgpu: introduce psp_v11_0_is_sos_alive interface(v2) introduce psp_v11_0_is_sos_alive func for common use. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> Signed-off-by: Tianci.Yin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e8186eec |
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17-Sep-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/psp: flush HDP write fifo after submitting cmds to the psp We need to make sure the fifo is flushed before we ask the psp to process the commands. Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
51c0f58e |
|
09-Sep-2019 |
Jack Zhang <Jack.Zhang1@amd.com> |
drm/amdgpu/sriov: add ring_stop before ring_create in psp v11 code psp v11 code missed ring stop in ring create function(VMR) while psp v3.1 code had the code. This will cause VM destroy1 fail and psp ring create fail. For SIOV-VF, ring_stop should not be deleted in ring_create function. Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
4fb60b02 |
|
04-Sep-2019 |
John Clements <john.clements@amd.com> |
drm/amdgpu: enable TA load support in Arcturus Add support for loading XGMI/RAS FW Signed-off-by: John Clements <john.clements@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
50e275e8 |
|
16-Aug-2019 |
Xiaojie Yuan <xiaojie.yuan@amd.com> |
drm/amdgpu: remove redundant argument for psp_funcs::cmd_submit callback Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
739cdbd6 |
|
02-Aug-2019 |
Xiaojie Yuan <xiaojie.yuan@amd.com> |
drm/amdgpu/psp11: add psp support for navi12 Same as other navi asics. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
dc0d9622 |
|
22-Jul-2019 |
John Clements <John.Clements@amd.com> |
drm/amdgpu: add PSP KDB loading support for Arcturus Add support for the arcturus specific psp metadata to the amdgpu firmware and properly parse it when loading it. Signed-off-by: John Clements <john.clements@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f36d9ab9 |
|
01-Aug-2019 |
John Clements <John.Clements@amd.com> |
drm/amdgpu: add PSP SW init support for Arcturus Add arcturus cases to psp init sewquence. Signed-off-by: John Clements <john.clements@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
8687b47e |
|
19-Mar-2019 |
Xiaojie Yuan <xiaojie.yuan@amd.com> |
drm/amdgpu: declare asd firmware for navi14 So the dependency gets properly tracked. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Snow Zhang <snow.zhang@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e470d287 |
|
15-Mar-2019 |
Xiaojie Yuan <xiaojie.yuan@amd.com> |
drm/amdgpu: skip to load ta firmware for navi14 Not relevant on navi14. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
82522b2d |
|
08-Jul-2019 |
Xiaojie Yuan <xiaojie.yuan@amd.com> |
drm/amdgpu/psp: add psp support for navi14 (v3) Same as navi10. v2: squash in logic fix (Colin Ian King) v3: squash in logic simplification (Alex) Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Snow Zhang <Snow.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
42989359 |
|
10-Jul-2019 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: support key database loading for navi10 Starting from navi10, driver should send Key Database Load command to bootloader before loading sys_drv and sos Signed-off-by: John Clements <John.Clements@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3840fe25 |
|
11-Jul-2019 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: switch to macro for psp bootloader command The command will be sent to psp bootloader from driver to ask psp bootloader to exerise tOS, sys_drv and kdb loading Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
173da95d |
|
08-Jul-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/psp11: simplify the ucode register logic Split it between navi10 and newer and everything before navi10. Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a954f3ff |
|
16-Feb-2019 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu/psp11: skip ta firmware for navi10 Not used on Navi10. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a698faf8 |
|
16-Feb-2019 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: declare navi10 asd firmware So the dependencies are properly handled. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5160709d |
|
09-Nov-2018 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu/psp: switch to use sos_offset_bytes member as sys_bin_size Navi10 will have toc built-in sos binary so that using header.ucode_size_bytes minus sos_size_bytes actually is not sys_bin_size. Using sos_offset_bytes works for both vega20 (psp_firmware_header_v1_0) and navi10 (psp_firmware_header_v1_1) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1a5b4cca |
|
24-Oct-2018 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu/psp: start rlc autoload after psp recieved all gfx firmware RLC handles firmware loading for gfx to support vddgfx feature. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
37e91918 |
|
23-Oct-2018 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu/psp: print out psp v11 ucode hdr in drm debug mode Print the psp header data if requested. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
93d8f222 |
|
22-Oct-2018 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu/psp: support init psp sos microcode with build-in toc psp_firmware_header_v1_1 is used for psp sos with build-in toc Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
bc290fe5 |
|
21-May-2018 |
Tao Zhou <Tao.Zhou1@amd.com> |
drm/amdgpu: Add psp 11.0 support for navi10. Add psp 11.0 code for navi10. psp 11.0 is not enabled for now. Will enable it when psp 11.0 firmware is available. Signed-off-by: Tao Zhou <Tao.Zhou1@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f867723b |
|
09-Jun-2019 |
Sam Ravnborg <sam@ravnborg.org> |
drm/amd: drop use of drmP.h in amdgpu.h Delete the unused drmP.h from amdgpu.h. Fix fallout in various files. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: "David (ChunMing) Zhou" <David1.Zhou@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20190609220757.10862-5-sam@ravnborg.org
|
#
b0960c35 |
|
08-Apr-2019 |
shaoyunl <shaoyun.liu@amd.com> |
drm/amdgpu: Always enable memory sharing within same XGMI hive XGMI Memory sharing will be disbaled by default for security reason after boot up, it depends on driver to enable the memory sharing Signed-off-by: shaoyunl <shaoyun.liu@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3ea8fb8c |
|
14-Nov-2018 |
xinhui pan <xinhui.pan@amd.com> |
drm/amdgpu: add psp v11 ras callback Add trigger_error and cure_posion. Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: xinhui pan <xinhui.pan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c6eec902 |
|
19-Nov-2018 |
xinhui pan <xinhui.pan@amd.com> |
drm/amdgpu: add ta ras fw info (v2) Add ras fw part, xgmi and ras fw are combined together in ta binary. Reading the data from the info is not implemented yet. v2: squash in "drm/amdgpu: fix NULL pointer when ta is missing" Signed-off-by: xinhui pan <xinhui.pan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b849aaa4 |
|
04-Mar-2019 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: also reroute VMC and UMD to IH ring 1 on Vega 20 Same patch we alredy did for Vega10. Just re-route page faults to a separate ring to avoid drowning in interrupts. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1d69511e |
|
12-Feb-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/psp11: TA firmware is optional (v3) Don't warn or fail if it's missing. v2: handle xgmi case more gracefully. v3: handle older kernels properly Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Tested-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
be4630d9 |
|
03-Jan-2019 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu/psp: make get_fw_type and prep_cmd_buf to be common interfaces get_fw_type and prep_cmd_buf should be common interface instead of IP specific ones Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
06d6370e |
|
20-Dec-2018 |
Evan Quan <evan.quan@amd.com> |
drm/amdgpu: add Vega20 PSP ASD firmware loading Add PSP ASD firmware loading on Vega20. Not sure why this was missing before. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
|
#
379c237e |
|
17-Dec-2018 |
Evan Quan <evan.quan@amd.com> |
drm/amdgpu: correct the return value for error case It should not return 0 for error case as '0' is actually a special value for index. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e27a73d1 |
|
12-Dec-2018 |
Emily Deng <Emily.Deng@amd.com> |
drm/amdgpu/psp: Correct and refine the vmr support. (v2) Currently driver only psp v11 support vmr. v2: squash in unused variable removal (Alex) Signed-off-by: Emily Deng <Emily.Deng@amd.com> Reviewed-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5ec996df |
|
04-Dec-2018 |
Xiangliang Yu <Xiangliang.Yu@amd.com> |
drm/amdgpu/psp: Add support VMR ring for VF PSP only support VMR ring for SRIOV vf since v45 and all commands will be send to VMR ring for executing. VMR ring use C2PMSG 101 ~ 103 instead of C2PMSG 64 ~ 71. Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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d63cda5b |
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04-Dec-2018 |
Xiangliang Yu <Xiangliang.Yu@amd.com> |
drm/amdgpu/psp: Get psp fw version through reading register If PSP FW is running already, driver will not load PSP FW again and skip it. So psp fw version is not correct if reading it from FW binary file, need to get right version from register. Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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38cd8a28 |
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29-Nov-2018 |
Andrey Grodzovsky <andrey.grodzovsky@amd.com> |
drm/amdgpu/psp: Update waiting in psp mode1 reset. No point in use mdelay unless running from interrupt context (which we are not) This is busy wait which will block the CPU for the entirety of the wait time. Also, reduce wait time to 500ms as it is done in refernce code because 1s might cause PSP FW TO issues during XGMI hive reset. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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bb8310cc |
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29-Sep-2018 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu/psp: add set_topology_info function set_topology_info is used for driver to set current topology info to xgmi ta Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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ec1a975e |
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29-Sep-2018 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu/psp: add get_topology_info function get_topology_info function is used for driver to query topology_info for current device from xgmi ta Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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4b93151f |
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28-Sep-2018 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu/psp: add get_hive_id function get_hive_id is used for driver to query hive_id for current device from xgmi ta Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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dd3c45d3 |
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28-Sep-2018 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu/psp: add get_node_id function get_node_id function is used for driver to get node_id for current device from xgmi ta Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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51e7177f |
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11-Oct-2018 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu/psp: init/de-init xgmi ta microcode Add ucode handling for psp xgmi ta firmware. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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548f2ecc |
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16-Oct-2018 |
John Clements <clements.jm@gmail.com> |
drm/amdgpu: Revised PSP comments Revised comments in PSP SOS/Sysdriver loading sequence Signed-off-by: John Clements <clements.jm@gmail.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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50325c0b |
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29-Sep-2018 |
YueHaibing <yuehaibing@huawei.com> |
drm/amdgpu: remove set but not used variable 'ring' in psp_v11_0_ring_stop Fixes gcc '-Wunused-but-set-variable' warning: drivers/gpu/drm/amd/amdgpu/psp_v11_0.c: In function 'psp_v11_0_ring_stop': drivers/gpu/drm/amd/amdgpu/psp_v11_0.c:309:19: warning: variable 'ring' set but not used [-Wunused-but-set-variable] Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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78122127 |
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14-Aug-2018 |
Shaoyun Liu <Shaoyun.Liu@amd.com> |
drm/amdgpu: Add place holder functions for xgmi topology interface with psp Add dummy function for xgmi function interface with psp Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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d4e83843 |
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14-Aug-2018 |
Evan Quan <evan.quan@amd.com> |
drm/amdgpu: added support 2nd UVD instance Added psp fw loading support for vega20 2nd UVD instance. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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654f761c |
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11-May-2018 |
Feifei Xu <Feifei.Xu@amd.com> |
drm/amdgpu: Add psp 11.0 support for vega20. (v2) Add psp 11.0 code for vega20 and enable it. PSP is the security processor for the GPU. It handles firmware loading and GPU resets among other things. v2: whitespace fix, enable support, adjust reg includes (Alex) Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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