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92508e7f |
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13-Dec-2023 |
Srujana Challa <schalla@marvell.com> |
crypto: octeontx2 - add SGv2 support for CN10KB or CN10KA B0 Scatter Gather input format for CPT has changed on CN10KB/CN10KA B0 HW to make it compatible with NIX Scatter Gather format to support SG mode for inline IPsec. This patch modifies the code to make the driver works for the same. This patch also enables CPT firmware load for these chips. Signed-off-by: Srujana Challa <schalla@marvell.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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4ad28689 |
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27-May-2022 |
Shijith Thotton <sthotton@marvell.com> |
crypto: octeontx2 - add firmware version in devlink info Added running firmware version information of AE, SE and IE components in devlink info. Signed-off-by: Shijith Thotton <sthotton@marvell.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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d9d77497 |
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01-Dec-2021 |
Srujana Challa <schalla@marvell.com> |
crypto: octeontx2 - add apis for custom engine groups Octeon TX2 CPT has three type of engines to handle symmetric, asymmetric and ipsec specific workload. For better utilization, these engines can be grouped to custom groups at runtime. This patch adds APIs to create and delete custom CPT engine groups. Signed-off-by: Srujana Challa <schalla@marvell.com> Signed-off-by: Shijith Thotton <sthotton@marvell.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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40a645f7 |
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25-May-2021 |
Srujana Challa <schalla@marvell.com> |
crypto: octeontx2 - add support for CPT operations on CN10K CPT result format had changed for CN10K HW to accommodate more fields. This patch adds support to use new result format and new LMTST lines for CPT operations on CN10K platform. Signed-off-by: Srujana Challa <schalla@marvell.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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78506c2a |
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15-Jan-2021 |
Srujana Challa <schalla@marvell.com> |
crypto: octeontx2 - add support to get engine capabilities Adds support to get engine capabilities and adds a new mailbox to share capabilities with VF driver. Signed-off-by: Suheil Chandran <schandran@marvell.com> Signed-off-by: Srujana Challa <schalla@marvell.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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43ac0b82 |
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15-Jan-2021 |
Srujana Challa <schalla@marvell.com> |
crypto: octeontx2 - load microcode and create engine groups CPT includes microcoded GigaCypher symmetric engines(SEs), IPsec symmetric engines(IEs), and asymmetric engines (AEs). Each engine receives CPT instructions from the engine groups it has subscribed to. This patch loads microcode, configures three engine groups(one for SEs, one for IEs and one for AEs), and configures all engines. Signed-off-by: Suheil Chandran <schandran@marvell.com> Signed-off-by: Lukasz Bartosik <lbartosik@marvell.com> Signed-off-by: Srujana Challa <schalla@marvell.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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