clk: ti: Drop legacy compatibility clocks for dra7

We no longer have users for the compatibility clocks and we can drop them.
These are old duplicate clocks for what we using.

Depends-on: 31aa7056bbec ("ARM: dts: Don't use legacy clock defines for dra7 clkctrl")
Depends-on: 9206a3af4fc0 ("clk: ti: Move dra7 clock devices out of the legacy section")
Cc: devicetree@vger.kernel.org
Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20220203085618.16043-4-tony@atomide.com
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: ti: dra7: Drop idlest polling from IVA clkctrl clocks

Similar to what we've done for IPU and DSP let's ignore the status bit
for the IVA clkctrl register.

The clkctrl status won't change unless the related rstctrl is deasserted,
and the rstctrl status won't change unless the clkctrl is enabled.

Cc: linux-clk@vger.kernel.org
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Suman Anna <s-anna@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

clk: ti: dra7: add missing clkctrl register for SHA2 instance

DRA7 SoC has two SHA instances. Add the clkctrl entry for the second
one.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Link: https://lore.kernel.org/r/20200907082600.454-4-t-kristo@ti.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: ti: dra7: remove two unused symbols

Fix the following gcc warning:

drivers/clk/ti/clk-7xx.c:320:43: warning: ‘dra7_gpu_sys_clk_data’
defined but not used [-Wunused-const-variable=]
static const struct omap_clkctrl_div_data dra7_gpu_sys_clk_data
__initconst = {
^~~~~~~~~~~~~~~~~~~~~
drivers/clk/ti/clk-7xx.c:315:27: warning: ‘dra7_gpu_sys_clk_parents’
defined but not used [-Wunused-const-variable=]
static const char * const dra7_gpu_sys_clk_parents[] __initconst = {
^~~~~~~~~~~~~~~~~~~~~~~~

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Jason Yan <yanaijie@huawei.com>
Link: https://lkml.kernel.org/r/20200417073523.42520-1-yanaijie@huawei.com
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: ti: dra7xx: fix RNG clock parent

RNG is sourced from L4 clock. Add info for this for proper parenting of
the clock.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Link: https://lkml.kernel.org/r/20200430083640.8621-4-t-kristo@ti.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: ti: dra7xx: mark MCAN clock as DRA76x only

This clock entry does not exist on any other devices except DRA76,
so mark it as specific to that SoC only.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Link: https://lkml.kernel.org/r/20200430083640.8621-3-t-kristo@ti.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: ti: dra7xx: fix gpu clkctrl parent

gpu_cm:* parent clock name is wrong, replace this with correct
gpu-clkctrl:* clock. Otherwise the clock ends up in the orphaned list.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Link: https://lkml.kernel.org/r/20200430083640.8621-2-t-kristo@ti.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: ti: add clkctrl data dra7 sgx

This is similar to what we have for omap5 except the gpu_cm address is
different, the mux clocks have one more source option, and there's no
divider clock.

Note that because of the current dts node name dependency for mapping to
clock domain, we must still use "gpu-clkctrl@" naming instead of generic
"clock@" naming for the node. And because of this, it's probably best to
apply the dts node addition together along with the other clock changes.

For accessing the GPU, we also need to configure the interconnect target
module for GPU similar to what we have for omap5, I'll send that change
separately.

Cc: Benoit Parrot <bparrot@ti.com>
Cc: "H. Nikolaus Schaller" <hns@goldelico.com>
Cc: Robert Nelson <robertcnelson@gmail.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Tero Kristo <t-kristo@ti.com>

clk: ti: dra7: fix parent for gmac_clkctrl

The parent clk for gmac clk ctrl has to be gmac_main_clk (125MHz) instead
of dpll_gmac_ck (1GHz). This is caused incorrect CPSW MDIO operation.
Hence, fix it.

Fixes: dffa9051d546 ('clk: ti: dra7: add new clkctrl data')
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>

clk: ti: dra7: add vpe clkctrl data

Add clkctrl data for VPE.

Signed-off-by: Benoit Parrot <bparrot@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Tero Kristo <t-kristo@ti.com>

clk: ti: dra7: add cam clkctrl data

Add clkctrl data for CAM domain.

Signed-off-by: Benoit Parrot <bparrot@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Tero Kristo <t-kristo@ti.com>

clk: ti: dra7xx: Drop idlest polling from IPU & DSP clkctrl clocks

The IPU and DSP remote processor cores and their corresponding MMUs on
DRA7 SoCs have hardreset lines associated with them and are controlled
by a PRCM reset line each. Any clkctrl enable/disable operations cannot
be checked for module enabled/disabled status independent of the reset
operation, and this causes some unwanted timeouts in the kernel and
unbalanced states for these clocks. These details should be handled by
the driver integration code itself.

Add the CLKF_NO_IDLEST flag to both the IPU and DSP clkctrl clocks so
that these module status checks are skipped.

Signed-off-by: Tero Kristo <t-kristo@ti.com>

clk: ti: dra7: Fix mcasp8 clock bits

There's a typo for dra7 mcasp clkctrl bit, it should be 22 like the other
macasp instances, and not 24. And in dra7xx_clks[] we have the bits wrong
way around.

Fixes: dffa9051d546 ("clk: ti: dra7: add new clkctrl data")
Cc: linux-clk@vger.kernel.org
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Suman Anna <s-anna@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500

Based on 2 normalized pattern(s):

this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation

this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation #

extracted by the scancode license scanner the SPDX license identifier

GPL-2.0-only

has been chosen to replace the boilerplate/reference in 4122 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Enrico Weigelt <info@metux.net>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

clk: ti: dra7: disable the RNG and TIMER12 clkctrl clocks on HS devices

RNG and TIMER12 are reserved for secure side usage only on HS devices,
so disable their clkctrl clocks on HS SoCs also.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: ti: dra7x: prevent non-existing clkctrl clocks from registering

Certain clkctrl clocks (like the USB_OTG_SS4) do not exist on some
variants of the dra7x SoC. Append a flag for these clocks and skip
the registration in cases where the clocks do not exist.

Reported-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: ti: dra7: add new clkctrl data

The new clkctrl data layout for dra7xx is split based on clockdomain
boundaries. Previously the split was based on CM boundaries. This patch
adds the new data as separate data entity, retaining the compatibility
data also for now. The compatibility data can be removed once no longer
needed.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>

clk: ti: dra7xx: rename existing clkctrl data as compat data

Rename the existing clkctrl data in preparation of upcoming clkdm
based split for it. Once the DT data has transitioned also, the
compat data can be removed.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>

clk: ti: dra7: Add clkctrl clock data for the mcan clocks

Add clkctrl data for the m_can clocks and register it within the
clkctrl driver

Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
CC: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

clk: ti: dra7: add clkctrl clock data

Add data for dra7 clkctrl clocks, and register it within the clkctrl
driver.

Signed-off-by: Tero Kristo <t-kristo@ti.com>

clk: ti: dra7: drop unnecessary clock aliases

Most of the clock aliases are no longer needed, only leave the ones
required by OMAP timer handling in place.

Signed-off-by: Tero Kristo <t-kristo@ti.com>

clk: ti: dra7: fix "failed to lookup clock node gmac_gmii_ref_clk_div" boot message

Prevent creating clk alias for non existing gmac_gmii_ref_clk_div clock and,
this way, eliminate excessive error message during boot:

"ti_dt_clocks_register: failed to lookup clock node gmac_gmii_ref_clk_div"

Fixes: c097338ebd3f ("ARM: dts: dra7: cpsw: fix clocks tree")
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

clk: ti: dra7: fix kernel boot with arg 'clocksource=gp_timer'

The OMAP Platform code provides possibility to select GP Timer as
default clocksource instead of counter_32K by using bootcmd parameter
'clocksource', but the system will crash during early boot when this
option is used on dra7 or omap5 platforms, because it will hit BUG()
statement:

omap2_gptimer_clocksource_init
->BUG_ON(res);

This happens because clk_dev alias "sys_clkin_ck" is not registered.
Hence, fix it by adding missing "sys_clkin_ck" clk_dev aliases
definitions for omap5 and dra7.

Acked-by: Tero Kristo <t-kristo@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

ARM: dts: dra7xx: Correct mcasp8_ahclkx_mux name

rename the mcasp8_ahclk_mux to mcasp8_ahclkx_mux.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
[tony@atomide.com: updated for the unit offsets]
Signed-off-by: Tony Lindgren <tony@atomide.com>

clk: ti: clk-7xx: Remove hardwired ABE clock configuration

The ABE related clocks should be configured via DT and not have it wired
inside of the kernel.

Fixes: a74c52def9ab ("clk: ti: clk-7xx: Correct ABE DPLL configuration")
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>

CLK: TI: always enable DESHDCP clock

DESHDCP clock is needed on DRA7 based SoCs to enable the DSS IP. That
clock is an odd one, as it is not supposed to be any kind of core clock
for DSS, and we don't even support HDCP, but the clock is still needed
even for the HWMOD framework to be able to reset the DSS IP.

As there's no support for multiple core clocks in the HWMOD framework,
we don't have any obvious place to enable this clock when DSS IP is
being enabled.

Furthermore, the HDMI on OMAP5 DSS is the same as on DRA7, and OMAP5
does not have any such clock configuration bit. This suggests that on
OMAP5 the DESHDCP clock is always enabled, and for DRA7 we have the
possibility to gate it.

So, as we don't have any clean way to enable and disable the clock
based on the need, this patch enables the clock at boot time, making it
work similarly to OMAP5.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Michael Turquette <mturquette@linaro.org>

arm: dra7: add DESHDCP clock

Add a new Linux clock for DRA7 based SoCs to control DESHDCP clock.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Tero Kristo <t-kristo@ti.com>

clk: ti: move some public definitions to private header

Several exported TI clock driver features are no longer needed outside
the clock driver itself, thus move all of these to the driver private
header file. Also, update some of the driver files to actually include
this header.

Signed-off-by: Tero Kristo <t-kristo@ti.com>

clk: ti: DRA7: Add timer_sys_ck aliases for Timers 13 through 16

The OMAP DMTimer API, omap_dm_timer_set_source(), uses the clock name
timer_sys_ck for setting a timer's clock source for the source index
OMAP_TIMER_SRC_SYS_CLK. There is currently no clock alias data for
the Timers 13 through 16 for this clock name, so add the same.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>

clk: ti: DRA7: Correct timer_sys_ck clock aliases for Timers

The OMAP DMTimer API, omap_dm_timer_set_source(), can set the parent
of a timer node using 3 different values that use fixed parent names
for the clocks. The parent name, timer_sys_ck, is used for setting the
parent when used with the source index OMAP_TIMER_SRC_SYS_CLK. This
should point to the TIMER_SYS_CLK and not the SYSCLKIN2, so correct
the clock aliases appropriately. SYSCLKIN2 is not a mandatory clock
input.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>

clk: ti: Drop use of clk-private.h

These modules don't need to include clk-private.h. Replace the
include with clk.h because these modules are clock consumers and
also include clk-provider.h in clk/ti.h because struct
clk_hw_omap has a struct clk_hw embedded in it.

Cc: Tero Kristo <t-kristo@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>

clk: ti: clk-7xx: Correct ABE DPLL configuration

ABE DPLL frequency need to be lowered from 361267200
to 180633600 to facilitate the ATL requironments.
The dpll_abe_m2x2_ck clock need to be set to double
of ABE DPLL rate in order to have correct clocks
for audio.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

CLK: ti: dra7: Initialize USB_DPLL

USB_DPLL must be initialized and locked at boot so that
USB modules can work.

Also program USB_DLL_M2 output to half rate.

CC: Mike Turquette <mturquette@linaro.org>
CC: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>

ARM: dts: dra7xx-clocks: Correct name for atl clkin3 clock

To allign the name with the other atl clock names:
atlclkin3_ck -> atl_clkin3_ck

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>

CLK: TI: OMAP4/5/DRA7: Remove gpmc_fck from dummy clocks

When arch/arm/mach-omap2/gpmc.c calls clk_get(..., "fck"), it will
get a dummy clock and try to use it. As the rate is configured to zero,
this will result in several divisions by zero, and misconfigured
timings, with devices on the bus being lost in the La La Land.

It is better to remove gpmc_fck from the dummy clocks, so that gpmc.c
can fail gracefully.

Cc: stable@vger.kernel.org # v3.14+
Signed-off-by: Florian Vaussard <florian.vaussard@epfl.ch>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

CLK: TI: add dra7 clock init file

clk-7xx.c now contains the clock init functionality for dra7, including
DT clock registration and adding of static clkdev entries.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>