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52e6676e |
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07-Jun-2022 |
Thomas Gleixner <tglx@linutronix.de> |
treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_30.RULE (part 1) Based on the normalized pattern: this program is free software you can redistribute it and/or modify it under the terms of the gnu general public license as published by the free software foundation version 2 this program is distributed as is without any warranty of any kind whether express or implied without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference. Reviewed-by: Allison Randal <allison@lohutok.net> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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e65eb2ef |
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03-Feb-2022 |
Tony Lindgren <tony@atomide.com> |
clk: ti: Drop legacy compatibility clocks for am4 We no longer have users for the compatibility clocks and we can drop them. These are old duplicate clocks for what we using. Cc: devicetree@vger.kernel.org Cc: Rob Herring <robh+dt@kernel.org> Signed-off-by: Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/r/20220203085618.16043-3-tony@atomide.com Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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59139ada |
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15-Oct-2021 |
Miquel Raynal <miquel.raynal@bootlin.com> |
clk: ti: am43xx: Add clkctrl data for am43xx ADC1 Declare ADC1 clkctrl which feeds the magnetic-reader/ADC1 hardware module. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20211015081506.933180-2-miquel.raynal@bootlin.com
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d36edb04 |
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15-Nov-2020 |
Tony Lindgren <tony@atomide.com> |
clk: ti: am437x: Keep am4 l3 main clock always on for genpd In order for suspend and resume to work with genpd on am4, we must keep l3 main clock always on. Otherwise prm_omap driver will shut down the l3 main clock on suspend when simple-pm-bus and GENPD_FLAG_PM_CLK are used. Note that we already keep the l3 main clock always on with the legacy platform code. Later on we may want to start managing the l3 main clock with a dedicated interconnect driver instead of using simple-pm-bus and GENPD_FLAG_PM_CLK. Cc: linux-clk@vger.kernel.org Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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5f3d9b07 |
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21-Feb-2020 |
Tony Lindgren <tony@atomide.com> |
clk: ti: am43xx: Fix clock parent for RTC clock Currently enabling clkctrl clock on am4 can fail for RTC as the clock parent is wrong for RTC. Fixes: 76a1049b84dd ("clk: ti: am43xx: add new clkctrl data for am43xx") Signed-off-by: Tony Lindgren <tony@atomide.com> Link: https://lkml.kernel.org/r/20200221171030.39326-1-tony@atomide.com Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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ece3e465 |
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07-Oct-2019 |
Tero Kristo <t-kristo@ti.com> |
clk: ti: am43xx: drop idlest polling from gfx clock Due to the way ti sysc and hardreset line control is now implemented, it is not possible to poll the clock status for gfx clock independent of hardreset line control. Thus, add a flag to prevent handling this status bit from clock driver. Correct sequencing of events is guaranteed by ti-sysc bus driver. Signed-off-by: Tero Kristo <t-kristo@ti.com>
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caf00b53 |
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12-Sep-2019 |
Tero Kristo <t-kristo@ti.com> |
clk: ti: am43xx: drop idlest polling from pruss clkctrl clock The PRUSS modules on AM43xx SoCs have a hardreset line and are controlled by a PRCM reset line. Any clkctrl enable/disable operations cannot be checked for module enabled/disabled status independent of the reset operation, and this causes some unwanted timeouts in the kernel and unbalanced states for the PRUSS clocks. These details should be handled by the driver integration code itself. Add the CLKF_NO_IDLEST flag to the PRUSS clkctrl clock so that these module status checks are skipped. Signed-off-by: Tero Kristo <t-kristo@ti.com>
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76a1049b |
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13-Aug-2018 |
Tero Kristo <t-kristo@ti.com> |
clk: ti: am43xx: add new clkctrl data for am43xx The new clkctrl data layout for am43xx is split based on clockdomain boundaries. Previously the split was based on CM boundaries. This patch adds the new data as separate data entity, retaining the compatibility data also for now. The compatibility data can be removed once no longer needed. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Tony Lindgren <tony@atomide.com>
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131ee08f |
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13-Aug-2018 |
Tero Kristo <t-kristo@ti.com> |
clk: ti: am43xx: rename existing clkctrl data as compat data Rename the existing clkctrl data in preparation of upcoming clkdm based split for it. Once the DT data has transitioned also, the compat data can be removed. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Tony Lindgren <tony@atomide.com>
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762790b7 |
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26-Feb-2018 |
Tero Kristo <t-kristo@ti.com> |
clk: ti: am43xx: add set-rate-parent support for display clkctrl clock Display driver assumes it can use clk_set_rate for the display clock via set-rate-parent mechanism, so add the flag for this to id. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com>
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a3da10b7 |
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10-Aug-2017 |
Tero Kristo <t-kristo@ti.com> |
clk: ti: am43xx: add clkctrl clock data Add data for am43xx clkctrl clocks, and register it within the clkctrl driver. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
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78aac800 |
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24-Aug-2017 |
Tero Kristo <t-kristo@ti.com> |
clk: ti: am43xx: cleanup unnecessary clock aliases Most of the clock aliases are no longer needed, only leave the ones required by OMAP timer code in place. Signed-off-by: Tero Kristo <t-kristo@ti.com>
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8ed607a7 |
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31-May-2016 |
Lokesh Vutla <lokeshvutla@ti.com> |
ARM: dts: AM43xx: clk: Add RNG clk node Add clk node for RNG module. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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22a15e6f |
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03-May-2016 |
Franklin S Cooper Jr <fcooper@ti.com> |
clk: ti: am335x/am4372: Add tbclk to pwm node Add tblck to the pwm nodes. This insures that the ehrpwm driver has access to the time-based clk. Do not remove similar entries for ehrpwm node. Later patches will switch from using ehrpwm node name to pwm. But to maintain ABI compatibility we shouldn't remove the old entries. Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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93c03a2c |
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18-Jun-2015 |
Keerthy <j-keerthy@ti.com> |
ARM: dts: AM437X: add dpll_clksel_mac_clk node The patch adds the missing dpll_clksel_mac_clk clock node. Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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1b29e601 |
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19-Jun-2015 |
Stephen Boyd <sboyd@codeaurora.org> |
clk: ti: Include clk.h This clock provider uses the consumer API, so include clk.h explicitly. Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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a3314e9c |
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04-Mar-2015 |
Tero Kristo <t-kristo@ti.com> |
clk: ti: move some public definitions to private header Several exported TI clock driver features are no longer needed outside the clock driver itself, thus move all of these to the driver private header file. Also, update some of the driver files to actually include this header. Signed-off-by: Tero Kristo <t-kristo@ti.com>
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4da1c677 |
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29-Apr-2014 |
Poddar, Sourav <sourav.poddar@ti.com> |
ARM: dts: am43x-clock: add tbclk data for ehrpwm We need "tbclk" clock data for the functioning of ehrpwm module. Hence, populating the required clock information in clock dts file. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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f9786f41 |
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01-May-2014 |
George Cherian <george.cherian@ti.com> |
ARM: AM43xx: clk: Change the cpts ref clock source to dpll_core_m5 clk cpsw_cpts_rft_clk has got the choice of 3 clocksources -dpll_core_m4_ck -dpll_core_m5_ck -dpll_disp_m2_ck By default dpll_core_m4_ck is selected, witn this as clock source the CPTS doesnot work properly. It gives clockcheck errors while running PTP. clockcheck: clock jumped backward or running slower than expected! By selecting dpll_core_m5_ck as the clocksource fixes this issue. In AM335x dpll_core_m5_ck is the default clocksource. Signed-off-by: George Cherian <george.cherian@ti.com> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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ffab2399 |
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20-Sep-2013 |
Tero Kristo <t-kristo@ti.com> |
CLK: TI: add am43xx clock init file clk-43xx.c now contains the clock init functionality for am43xx, including DT clock registration and adding of static clkdev entries. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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