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88ddf98a |
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16-Feb-2023 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: r8a77970: Add Z2 clock Add support for the Z2 (Cortex-A53 System CPU) clock on R-Car V3M, which uses a fixed SYS-CPU divider. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/6a9169e5bc92c2b9549292769a0814e04b9147cf.1676560357.git.geert+renesas@glider.be
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f23f1101 |
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16-Jun-2020 |
Ulrich Hecht <uli+renesas@fpond.eu> |
clk: renesas: rcar-gen3: Mark RWDT clocks as critical Ensures RWDT remains alert throughout the boot process if enabled. This patch applies the change to the following SoCs: r8a77950, r8a77951, r8a77960, r8a77961, r8a77965, r8a77970, r8a77980, r8a77990 and r8a77995. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Link: https://lore.kernel.org/r/20200616162626.27944-3-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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396bc9d4 |
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21-Nov-2018 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: r8a77970: Add CPEX clock Implement support for the CPEX clock on R-Car V3M. This clock can be selected as a clock source for CMT1 (Compare Match Timer Type 1). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@kernel.org>
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6f44610c |
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02-Nov-2018 |
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> |
clk: renesas: r8a77970: Add RPC clocks On R-Car V3M (R8A77970), the RPC/RPCD2 clocks are output by the common divider. Describe them, as well as the RPC-IF module clock. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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9e288cef |
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25-Sep-2018 |
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> |
clk: renesas: Convert to SPDX identifiers This patch updates license to use SPDX-License-Identifier instead of verbose license text. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> [rebased against clk-spdx] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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9ef5e037 |
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19-Sep-2018 |
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> |
clk: renesas: r8a77970: Add TPU clock The TPU0 clock wasn't present in the original R8A77970 patch by Daisuke Matsushita, it was added in a later BSP version... Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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6207ba04 |
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06-Sep-2018 |
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> |
clk: renesas: r8a77970: Add TMU clocks The TMU clocks weren't present in the original R8A77970 patch by Daisuke Matsushita, they were added in a later BSP version... Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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5986b503 |
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05-Sep-2018 |
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> |
clk: renesas: r8a77970: Add CMT clocks Add the R8A77970 CMT module clocks. Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Chris Paterson <chris.paterson2@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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381081ff |
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01-Sep-2018 |
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> |
clk: renesas: r8a77970: Add SD0H/SD0 clocks for SDHI On R-Car V3M (AKA R8A77970), the SD0CKCR is laid out differently than on the other R-Car gen3 SoCs. In fact, the layout is the same as on R-Car gen2 SoCs, so we'll need to copy the divisor tables from the R-Car gen2 driver. We'll also need to support the SoC specific clock types, thus we're adding CLK_TYPE_GEN3_SOC_BASE at the end of 'enum rcar_gen3_clk_types', declare SD0H/SDH clocks in 'enum r8a77970_clk_types', and handle those clocks in the overridden cpg_clk_register() method; then, finally, add the SD-IF module clock (derived from the SD0 clock). Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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64082568 |
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05-Dec-2017 |
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> |
clk: renesas: r8a77970: Add LVDS clock I seem to have omitted the LVDS clock from the R8A77970 CPG/MSSR support patch for some reason -- add it back... Based on the original (and large) patch by Daisuke Matsushita <daisuke.matsushita.ns@hitachi.com>. Fixes: 8d46e28fb5081b49 ("clk: renesas: cpg-mssr: Add R8A77970 support") Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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8d46e28f |
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08-Sep-2017 |
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> |
clk: renesas: cpg-mssr: Add R8A77970 support Add R-Car V3M (R8A77970) Clock Pulse Generator / Module Standby and Software Reset support, using the CPG/MSSR driver core and the common R-Car Gen3 code. Based on the original (and large) patch by Daisuke Matsushita <daisuke.matsushita.ns@hitachi.com>. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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