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e41cb217 |
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31-Aug-2020 |
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> |
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r) VSP1 instances VSPS (which stands for "VSP Standard") and VSPR (which stands for "VSP for Resizing") were wrongly named as "vsp1-sy" and "vsp1-rt". The clock section in the SoC datasheets misunderstood the abbreviations as meaning VSP System and VSP Realtime, and named the corresponding clocks VSP1(SY) and VSP1(RT). This mistake has been carried over to the kernel code. This patch fixes this by renaming the clock names to "vsps" and "vspr". Inspired from commit 79ea9934b8df ("ARM: shmobile: r8a7790: Rename VSP1_(SY|RT) clocks to VSP1_(S|R)") Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20200831183722.8165-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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9e288cef |
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25-Sep-2018 |
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> |
clk: renesas: Convert to SPDX identifiers This patch updates license to use SPDX-License-Identifier instead of verbose license text. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> [rebased against clk-spdx] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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83fab8ea |
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29-Mar-2018 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: r8a7745: Fix LB clock divider The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where the LB clock divider depends on the value of the MD18 pin. On RZ/G1E, the LB clock divider is fixed to 24. Hence model the clock as a fixed factor clock instead. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
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e0c0a2c4 |
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12-Feb-2018 |
Fabrizio Castro <fabrizio.castro@bp.renesas.com> |
clk: renesas: r8a7745: Add rwdt clock Add "rwdt" clock to r8a7745_mod_clks. Also, since we may need to access the watchdog registers at any time, declare the clock as critical. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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9dc0ddee |
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13-Oct-2017 |
Fabrizio Castro <fabrizio.castro@bp.renesas.com> |
clk: renesas: cpg-mssr: Add du1 clock to R8A7745 Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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5ed793b3 |
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31-Mar-2017 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: r8a7745: Remove PLL configs for MD19=0 According to tables 7.5b and 7.6b of the RZ/G Series Hardware User's Manual Rev.1.00, MD19=0 is a prohibited setting. Hence stop looking at MD19, and remove all PLL configurations for MD19=0. Fixes: 9127d54bb8947159 ("clk: renesas: cpg-mssr: Add R8A7745 support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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b93e7eb5 |
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29-Mar-2017 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: r8a7745: Remove nonexisting scu-src[0789] clocks RZ/G1E does not have the SCU-SRC[0789] modules and module clocks. Fixes: 9127d54bb8947159 ("clk: renesas: cpg-mssr: Add R8A7745 support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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9127d54b |
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08-Nov-2016 |
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> |
clk: renesas: cpg-mssr: Add R8A7745 support Add RZ/G1E (R8A7745) Clock Pulse Generator / Module Standby and Software Reset support, using the CPG/MSSR driver core and the common R-Car Gen2 (and RZ/G) code. Based on the proof-of-concept R8A7791 CPG/MSSR patch by Geert Uytterhoeven <geert+renesas@glider.be>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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