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c90847bc |
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26-Mar-2024 |
Samuel Holland <samuel.holland@sifive.com> |
cache: sifive_ccache: Partially convert to a platform driver Commit 8ec99b033147 ("irqchip/sifive-plic: Convert PLIC driver into a platform driver") broke ccache initialization because the PLIC IRQ domain is no longer available during an arch_initcall: [ 0.087229] irq: no irq domain found for interrupt-controller@c000000 ! [ 0.087255] CCACHE: Could not request IRQ 0 Fix this by moving the IRQ handling code to a platform driver. Fixes: 8ec99b033147 ("irqchip/sifive-plic: Convert PLIC driver into a platform driver") Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Tested-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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0d5701dc |
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31-Oct-2023 |
Emil Renner Berthing <kernel@esmil.dk> |
soc: sifive: ccache: Add StarFive JH7100 support This adds support for the StarFive JH7100 SoC which also features this SiFive cache controller. The JH7100 has non-coherent DMAs but predate the standard RISC-V Zicbom exension, so instead we need to use this cache controller for non-standard cache management operations. Unfortunately the interrupt for uncorrected data is broken on the JH7100 and fires continuously, so add a quirk to not register a handler for it. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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971f128b |
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12-Oct-2023 |
Conor Dooley <conor.dooley@microchip.com> |
soc: sifive: shunt ccache driver to drivers/cache Move the ccache driver over to drivers/cache, out of the drivers/soc dumping ground, to this new collection point for cache controller drivers. Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Tested-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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