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9e1e41c4 |
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30-Aug-2019 |
Max Filippov <jcmvbkbc@gmail.com> |
xtensa: clean up PS_WOE_BIT usage PS_WOE_BIT is mainly used to generate PS.WOE mask in the code. Introduce PS_WOE_MASK macro and use it instead. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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f21a79ca |
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15-Dec-2017 |
Max Filippov <jcmvbkbc@gmail.com> |
xtensa: clean up exception handling structure Instead of using flat array of longs use normal C structure and generate EXC_TABLE_* constants in the asm-offsets.c Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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c91e02bd |
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24-Jan-2016 |
Max Filippov <jcmvbkbc@gmail.com> |
xtensa: support hardware breakpoints/watchpoints Use perf framework to manage hardware instruction and data breakpoints. Add two new ptrace calls: PTRACE_GETHBPREGS and PTRACE_SETHBPREGS to query and set instruction and data breakpoints. Address bit 0 choose instruction (0) or data (1) break register, bits 31..1 are the register number. Both calls transfer two 32-bit words: address (0) and control (1). Instruction breakpoint contorl word is 0 to clear breakpoint, 1 to set. Data breakpoint control word bit 31 is 'trigger on store', bit 30 is 'trigger on load, bits 29..0 are length. Length 0 is used to clear a breakpoint. To set a breakpoint length must be a power of 2 in the range 1..64 and the address must be length-aligned. Introduce new thread_info flag: TIF_DB_DISABLED. Set it if debug exception is raised by the kernel code accessing watched userspace address and disable corresponding data breakpoint. On exit to userspace check that flag and, if set, restore all data breakpoints. Handle debug exceptions raised with PS.EXCM set. This may happen when window overflow/underflow handler or fast exception handler hits data breakpoint, in which case save and disable all data breakpoints, single-step faulting instruction and restore data breakpoints. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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99d5040e |
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03-Jul-2013 |
Max Filippov <jcmvbkbc@gmail.com> |
xtensa: keep a3 and excsave1 on entry to exception handlers Based on the SMP patch by Joe Taylor and subsequent fixes. Preserve exception table pointer (normally stored in excsave1 SR) as it cannot be easily restored in SMP environment. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
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2d1c645c |
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04-Jan-2013 |
Marc Gauthier <marc@tensilica.com> |
xtensa: dispatch medium-priority interrupts Add support for dispatching medium-priority interrupts, that is, interrupts of priority levels 2 to EXCM_LEVEL. IRQ handling may be preempted by higher priority IRQ. Signed-off-by: Marc Gauthier <marc@tensilica.com> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
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c4c4594b |
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28-Nov-2012 |
Chris Zankel <chris@zankel.net> |
xtensa: clean up files to make them code-style compliant Remove heading and trailing spaces, trim trailing lines, and wrap lines that are longer than 80 characters. Signed-off-by: Chris Zankel <chris@zankel.net>
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00273125 |
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28-Nov-2012 |
Max Filippov <jcmvbkbc@gmail.com> |
xtensa: add s32c1i sanity check Add a brief sanity test of S32C1I functionality. This instruction is needed by the kernel and userland as part of the base ABI (including GCC atomic builtins, certain threading packages, future atomic support in the C++ standard, etc). However, correct operation of this instruction requires some cooperation by hardware external to the processor (such as bus bridge, bus fabric, or memory controller). Minimally exercising this mechanism and reporting explicit status early in the boot process is helpful to chip vendors using the Linux kernel as a benchmark of correctness of hardware. As it turns out, S32C1I is not exercised by the kernel and by uClibc based userland as of early June 2008. This is expected to change soon as both incorporate more recent open source developments. Signed-off-by: Marc Gauthier <marc@tensilica.com> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
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bc5378fc |
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14-Oct-2012 |
Max Filippov <jcmvbkbc@gmail.com> |
xtensa: reorganize SR referencing - reference SRs by names where possible, not by numbers; - get rid of __stringify around SR names where possible; - remove unneeded SR names from asm/regs.h; - add SREG_ prefix to remaining SR names; Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
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eb9a63a1 |
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16-Sep-2012 |
Max Filippov <jcmvbkbc@gmail.com> |
xtensa: rename MISC SR definition to avoid name clashes There are other special register that cause build warnings and may as well need renaming as well. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
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367b8112 |
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06-Nov-2008 |
Chris Zankel <chris@zankel.net> |
xtensa: move headers files to arch/xtensa/include Move all header files for xtensa to arch/xtensa/include and platform and variant header files to the appropriate arch/xtensa/platforms/ and arch/xtensa/variants/ directories. Moving the files gets also rid of all uses of symlinks in the Makefile. This has been completed already for the majority of the architectures and xtensa is one out of six missing. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Chris Zankel <chris@zankel.net>
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