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87670c57 |
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23-Mar-2023 |
Jonathan Corbet <corbet@lwn.net> |
docs: move xtensa documentation under Documentation/arch/ Architecture-specific documentation is being moved into Documentation/arch/ as a way of cleaning up the top-level documentation directory and making the docs hierarchy more closely match the source hierarchy. Move Documentation/xtensa into arch/ and fix all in-tree references. Cc: Chris Zankel <chris@zankel.net> Reviewed-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Jonathan Corbet <corbet@lwn.net>
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f96c4ad6 |
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14-Mar-2021 |
Max Filippov <jcmvbkbc@gmail.com> |
xtensa: drop extraneous register load from initialize_mmu Commit a9f2fc628e3a ("xtensa: cleanup MMU setup and kernel layout macros") removed the use of a2 in the beginning of the initialize_mmu macro, but left the register load that is no longer used. Remove it as well. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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10b60595 |
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21-Jul-2020 |
Randy Dunlap <rdunlap@infradead.org> |
xtensa: initialize_mmu.h: fix a duplicated word Change "The the" to "For the". Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Cc: Chris Zankel <chris@zankel.net> Cc: Max Filippov <jcmvbkbc@gmail.com> Cc: linux-xtensa@linux-xtensa.org Message-Id: <20200721210044.15458-1-rdunlap@infradead.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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ca5999fd |
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08-Jun-2020 |
Mike Rapoport <rppt@kernel.org> |
mm: introduce include/linux/pgtable.h The include/linux/pgtable.h is going to be the home of generic page table manipulation functions. Start with moving asm-generic/pgtable.h to include/linux/pgtable.h and make the latter include asm/pgtable.h. Signed-off-by: Mike Rapoport <rppt@linux.ibm.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Borislav Petkov <bp@alien8.de> Cc: Brian Cain <bcain@codeaurora.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Chris Zankel <chris@zankel.net> Cc: "David S. Miller" <davem@davemloft.net> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Greentime Hu <green.hu@gmail.com> Cc: Greg Ungerer <gerg@linux-m68k.org> Cc: Guan Xuetao <gxt@pku.edu.cn> Cc: Guo Ren <guoren@kernel.org> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: Helge Deller <deller@gmx.de> Cc: Ingo Molnar <mingo@redhat.com> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Mark Salter <msalter@redhat.com> Cc: Matthew Wilcox <willy@infradead.org> Cc: Matt Turner <mattst88@gmail.com> Cc: Max Filippov <jcmvbkbc@gmail.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Michal Simek <monstr@monstr.eu> Cc: Nick Hu <nickhu@andestech.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: Richard Weinberger <richard@nod.at> Cc: Rich Felker <dalias@libc.org> Cc: Russell King <linux@armlinux.org.uk> Cc: Stafford Horne <shorne@gmail.com> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Tony Luck <tony.luck@intel.com> Cc: Vincent Chen <deanbo422@gmail.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Will Deacon <will@kernel.org> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Link: http://lkml.kernel.org/r/20200514170327.31389-3-rppt@kernel.org Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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6af4ab57 |
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29-Sep-2019 |
Max Filippov <jcmvbkbc@gmail.com> |
xtensa: move MPU constants from .data to .ref.rodata MPU attribute mapping table is R/O, move it from .data to __REFCONST (as the rest of the _startup code where initialize_cacheattr is used is in the __REF section). This allows executing initialize_cacheattr before the data section of the XIP kernel is relocated to its place. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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8ea0afa3 |
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18-Apr-2019 |
Mauro Carvalho Chehab <mchehab+samsung@kernel.org> |
docs: xtensa: convert to ReST Rename the xtensa documentation files to ReST, add an index for them and adjust in order to produce a nice html output via the Sphinx build system. At its new index.rst, let's add a :orphan: while this is not linked to the main index.rst file, in order to avoid build warnings. Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
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a5944195 |
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06-May-2019 |
Max Filippov <jcmvbkbc@gmail.com> |
xtensa: implement initialize_cacheattr for MPU cores Use CONFIG_MEMMAP_CACHEATTR to initialize MPU as described in the Xtensa LSP RM document. Coalesce adjacent regions with the same cacheattr. Update Kconfig help text. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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8f8d5745 |
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01-Jan-2019 |
Max Filippov <jcmvbkbc@gmail.com> |
xtensa: replace variant/core.h with asm/core.h Introduce the header arch/xtensa/include/asm/core.h that provides definitions for XCHAL macros missing in older xtensa releases. Use this header instead of variant/core.h Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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7bb516ca |
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12-Aug-2018 |
Max Filippov <jcmvbkbc@gmail.com> |
xtensa: rework noMMU cache attributes initialization Marking default memory region as cached is not always sufficient and is not flexible. Allow specifying cache attributes for the whole memory address space with new config entry MEMMAP_CACHEATTR. Apply it after cache initialization. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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a9f2fc62 |
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12-Apr-2016 |
Max Filippov <jcmvbkbc@gmail.com> |
xtensa: cleanup MMU setup and kernel layout macros Make kernel load address explicit, independent of the selected MMU configuration and configurable from Kconfig. Do not restrict it to the first 512MB of the physical address space. Cleanup kernel memory layout macros: - rename VECBASE_RESET_VADDR to VECBASE_VADDR, XC_VADDR to VECTOR_VADDR; - drop VIRTUAL_MEMORY_ADDRESS and LOAD_MEMORY_ADDRESS; - introduce PHYS_OFFSET and use it in __va and __pa definitions; - synchronize MMU/noMMU vectors, drop unused NMI vector; - replace hardcoded vectors offset of 0x3000 with Kconfig symbol. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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d39af902 |
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11-Apr-2016 |
Max Filippov <jcmvbkbc@gmail.com> |
xtensa: add alternative kernel memory layouts MMUv3 is able to support low memory bigger than 128MB. Implement 256MB and 512MB KSEG layouts: - add Kconfig selector for KSEG layout; - add KSEG base address, size and alignment definitions to arch/xtensa/include/asm/kmem_layout.h; - use new definitions in TLB initialization; - add build time memory map consistency checks. See Documentation/xtensa/mmu.txt for the details of new memory layouts. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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01618bde |
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24-Sep-2015 |
Max Filippov <jcmvbkbc@gmail.com> |
xtensa: fix build for configs without cache options - make cache-related assembly macros empty if core doesn't have corresponding cache type; - don't initialize cache attributes in instruction/data TLB entries if there's no corresponding cache type. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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2eabc180 |
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04-Oct-2014 |
Max Filippov <jcmvbkbc@gmail.com> |
xtensa: nommu: set up cache and atomctl in initialize_mmu initialize_mmu sets up atomctl SR which is needed for s32c1i to function correctly even in noMMU configurations. It's also a good place to set up caching attributes of physical memory. Allow enabling INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX in noMMU configurations for setting up atomctl and cache attributes. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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53490121 |
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03-Oct-2014 |
Max Filippov <jcmvbkbc@gmail.com> |
xtensa: move vecbase SR initialization to _startup Instead of initializing vecbase in initialize_mmu macro, which may be expanded either in Image.elf reset vector hadler or in the kernel head.S, both times only when CONFIG_MMU is enabled, do this initialization once in _startup function. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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6cb97111 |
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29-Dec-2013 |
Baruch Siach <baruch@tkos.co.il> |
xtensa: remap io area defined in device tree Use the simple-bus node to discover the io area, and remap the cached and bypass io ranges. The parent-bus-address value of the first triplet in the "ranges" property is used. This value is rounded down to the nearest 256MB boundary. The length of the io area is fixed at 256MB; the "ranges" property length value is ignored. Other limitations: (1) only the first simple-bus node is considered, and (2) only the first triplet of the "ranges" property is considered. See ePAPR 1.1 §6.5 for the simple-bus node description, and §2.3.8 for the "ranges" property description. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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4809bb46 |
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16-Nov-2013 |
Baruch Siach <baruch@tkos.co.il> |
xtensa: avoid duplicate of IO range definitions Define IO addresses in a single place, to make it easier to change for non-standard memory maps. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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e85e335f |
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03-Dec-2012 |
Max Filippov <jcmvbkbc@gmail.com> |
xtensa: add MMU v3 support MMUv3 comes out of reset with identity vaddr -> paddr mapping in the TLB way 6: Way 6 (512 MB) Vaddr Paddr ASID Attr RWX Cache ---------- ---------- ---- ---- --- ------- 0x00000000 0x00000000 0x01 0x03 RWX Bypass 0x20000000 0x20000000 0x01 0x03 RWX Bypass 0x40000000 0x40000000 0x01 0x03 RWX Bypass 0x60000000 0x60000000 0x01 0x03 RWX Bypass 0x80000000 0x80000000 0x01 0x03 RWX Bypass 0xa0000000 0xa0000000 0x01 0x03 RWX Bypass 0xc0000000 0xc0000000 0x01 0x03 RWX Bypass 0xe0000000 0xe0000000 0x01 0x03 RWX Bypass This patch adds remapping code at the reset vector or at the kernel _start (depending on CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX) that reconfigures MMUv3 as MMUv2: Way 5 (128 MB) Vaddr Paddr ASID Attr RWX Cache ---------- ---------- ---- ---- --- ------- 0xd0000000 0x00000000 0x01 0x07 RWX WB 0xd8000000 0x00000000 0x01 0x03 RWX Bypass Way 6 (256 MB) Vaddr Paddr ASID Attr RWX Cache ---------- ---------- ---- ---- --- ------- 0xe0000000 0xf0000000 0x01 0x07 RWX WB 0xf0000000 0xf0000000 0x01 0x03 RWX Bypass Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
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c622b29d |
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18-Nov-2012 |
Max Filippov <jcmvbkbc@gmail.com> |
xtensa: initialize atomctl SR In order to use S32C1I instruction on cores with ATOMCTL SR the register must be properly initialized. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
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