xtensa: add default definition for XCHAL_HAVE_DIV32

When variant FSF is set, XCHAL_HAVE_DIV32 is not defined. Add default
definition for that macro to prevent build warnings:

arch/xtensa/lib/divsi3.S:9:5: warning: "XCHAL_HAVE_DIV32" is not defined, evaluates to 0 [-Wundef]
9 | #if XCHAL_HAVE_DIV32
arch/xtensa/lib/modsi3.S:9:5: warning: "XCHAL_HAVE_DIV32" is not defined, evaluates to 0 [-Wundef]
9 | #if XCHAL_HAVE_DIV32

Fixes: 173d6681380a ("xtensa: remove extra header files")
Suggested-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reported-by: kernel test robot <lkp@intel.com>
Closes: lore.kernel.org/r/202309150556.t0yCdv3g-lkp@intel.com

xtensa: PMU: fix base address for the newer hardware

With introduction of ERI access control in RG.0 base address of the PMU
unit registers has changed. Add support for the new PMU configuration.

Cc: stable@vger.kernel.org
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

xtensa: report trax and perf counters in cpuinfo

Add 'trax' to the list of CPU features when xtensa core is configured
with TRAX.
Add 'perf' to the list of CPU features when xtensa core is configured
with perf counters and show the number of configured perf counters.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

xtensa: merge stack alignment definitions

xtensa currently has two different definitions for stack alignment.
Replace it with single definition usable in both C and assembly.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

xtensa: definitions for call0 ABI

Add assembly macros for calls, call arguments, preserved registers,
function entry and return for windowed and call0 ABIs.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

xtensa: clean up optional XCHAL_* definitions

Simplify users of XCHAL_HAVE_EXTERN_REGS and XCHAL_HAVE_VECBASE and
always define them as 0 if they're not defined in the variant/core.h

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

xtensa: implement initialize_cacheattr for MPU cores

Use CONFIG_MEMMAP_CACHEATTR to initialize MPU as described in the Xtensa
LSP RM document. Coalesce adjacent regions with the same cacheattr.
Update Kconfig help text.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

xtensa: add exclusive atomics support

Implement atomic primitives using exclusive access opcodes available in
the recent xtensa cores.
Since l32ex/s32ex don't have any memory ordering guarantees don't define
__smp_mb__before_atomic/__smp_mb__after_atomic to make them use memw.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

xtensa: replace variant/core.h with asm/core.h

Introduce the header arch/xtensa/include/asm/core.h that provides
definitions for XCHAL macros missing in older xtensa releases. Use this
header instead of variant/core.h

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>