riscv: dts: starfive: add 'cpus' label to jh7110 and jh7100 soc dtsi

Add the 'cpus' label so that we can reference it in board dts files.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

riscv: dts: starfive: jh7110: Add camera subsystem nodes

Add camera subsystem nodes for the StarFive JH7110 SoC. They contain the
dphy-rx, csi2rx, camss nodes.

Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

riscv: dts: starfive: jh7110: Add PWM node and pins configuration

Add OpenCores PWM controller node and add PWM pins configuration
on VisionFive 2 board.

Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

riscv: dts: starfive: replace underscores in node names

Underscores should not be used in node names (dtc with W=2 warns about
them), so replace them with hyphens.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

riscv: dts: starfive: convert isa detection to new properties

Convert the jh7100 and jh7110 devicetrees to use the new properties
"riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

riscv: dts: starfive: Add JH7110 PWM-DAC support

Add PWM-DAC support for StarFive JH7110 SoC.

Reviewed-by: Walker Chen <walker.chen@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

riscv: dts: starfive: Add the nodes and pins of I2Srx/I2Stx0/I2Stx1

Add I2Srx/I2Stx0/I2Stx1 nodes and pins configuration for the
StarFive JH7110 SoC.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: Walker Chen <walker.chen@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

riscv: dts: starfive: fix jh7110 qspi sort order

Emil pointed out that "13010000 sorts after 12070000". Reshuffle the
entries to be in-order.

Reported-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

riscv: dts: starfive: jh7110: Fix GMAC configuration

Fixed configuration to improve the speed of TCP RX.

Before:
# iperf3 -s
-----------------------------------------------------------
Server listening on 5201 (test #1)
-----------------------------------------------------------
Accepted connection from 192.168.1.4, port 47604
[ 5] local 192.168.1.3 port 5201 connected to 192.168.1.4 port 47612
[ ID] Interval Transfer Bitrate
[ 5] 0.00-1.00 sec 36.3 MBytes 305 Mbits/sec
[ 5] 1.00-2.00 sec 35.6 MBytes 299 Mbits/sec
[ 5] 2.00-3.00 sec 36.5 MBytes 306 Mbits/sec
[ 5] 3.00-4.00 sec 36.5 MBytes 306 Mbits/sec
[ 5] 4.00-5.00 sec 35.7 MBytes 300 Mbits/sec
[ 5] 5.00-6.00 sec 35.4 MBytes 297 Mbits/sec
[ 5] 6.00-7.00 sec 37.1 MBytes 311 Mbits/sec
[ 5] 7.00-8.00 sec 35.6 MBytes 298 Mbits/sec
[ 5] 8.00-9.00 sec 36.4 MBytes 305 Mbits/sec
[ 5] 9.00-10.00 sec 36.3 MBytes 304 Mbits/sec
- - - - - - - - - - - - - - - - - - - - - - - - -
[ ID] Interval Transfer Bitrate
[ 5] 0.00-10.00 sec 361 MBytes 303 Mbits/sec receiver

After:
# iperf3 -s
-----------------------------------------------------------
Server listening on 5201 (test #1)
-----------------------------------------------------------
Accepted connection from 192.168.1.4, port 47710
[ 5] local 192.168.1.3 port 5201 connected to 192.168.1.4 port 47720
[ ID] Interval Transfer Bitrate
[ 5] 0.00-1.00 sec 111 MBytes 932 Mbits/sec
[ 5] 1.00-2.00 sec 111 MBytes 934 Mbits/sec
[ 5] 2.00-3.00 sec 111 MBytes 934 Mbits/sec
[ 5] 3.00-4.00 sec 111 MBytes 934 Mbits/sec
[ 5] 4.00-5.00 sec 111 MBytes 934 Mbits/sec
[ 5] 5.00-6.00 sec 111 MBytes 935 Mbits/sec
[ 5] 6.00-7.00 sec 111 MBytes 934 Mbits/sec
[ 5] 7.00-8.00 sec 111 MBytes 935 Mbits/sec
[ 5] 8.00-9.00 sec 111 MBytes 934 Mbits/sec
[ 5] 9.00-10.00 sec 111 MBytes 934 Mbits/sec
[ 5] 10.00-10.00 sec 167 KBytes 933 Mbits/sec
- - - - - - - - - - - - - - - - - - - - - - - - -
[ ID] Interval Transfer Bitrate
[ 5] 0.00-10.00 sec 1.09 GBytes 934 Mbits/sec receiver

Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
Fixes: 1ff166c97972 ("riscv: dts: starfive: jh7110: Add ethernet device nodes")
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
[conor: converted to decimal per emil's request]
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

riscv: dts: starfive - Add hwrng node for JH7110 SoC

Add hardware rng controller node for StarFive JH7110 SoC.

Co-developed-by: Jenny Zhang <jenny.zhang@starfivetech.com>
Signed-off-by: Jenny Zhang <jenny.zhang@starfivetech.com>
Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

riscv: dts: starfive - Add crypto and DMA node for JH7110

Add hardware crypto module and dedicated dma controller node to StarFive
JH7110 SoC.

Co-developed-by: Huan Feng <huan.feng@starfivetech.com>
Signed-off-by: Huan Feng <huan.feng@starfivetech.com>
Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

riscv: dts: starfive: Add mmc nodes on VisionFive 2 board

Add the mmc nodes for the StarFive JH7110 SoC.
Set mmc0 node to emmc and set mmc1 node to sd.

Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoC

Add the quad spi controller node for the StarFive JH7110 SoC.

Co-developed-by: Ziv Xu <ziv.xu@starfivetech.com>
Signed-off-by: Ziv Xu <ziv.xu@starfivetech.com>
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

riscv: dts: starfive: jh7110: add the node and pins configuration for tdm

Add the tdm controller node and pins configuration of tdm for the
StarFive JH7110 SoC.

Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

riscv: dts: starfive: jh7110: add dma controller node

Add the dma controller node for the Starfive JH7110 SoC.

Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

riscv: dts: starfive: Add spi node and pins configuration

Add StarFive JH7110 SPI controller node and pins configuration on
VisionFive 2 board.

Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

riscv: dts: starfive: Add USB dts node for JH7110

Add USB wrapper layer and Cadence USB3 controller dts
configuration for StarFive JH7110 SoC and VisionFive2
Board.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

riscv: dts: starfive: Add USB and PCIe PHY nodes for JH7110

Add USB and PCIe PHY dts nodes for the StarFive JH7110 SoC.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

riscv: dts: starfive: jh7110: Add temperature sensor node and thermal-zones

Add temperature sensor and thermal-zones support for
the StarFive JH7110 SoC. CPUFreq cooling is supported
in thermal-zones.

Co-developed-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

riscv: dts: starfive: jh7110: Add ethernet device nodes

Add JH7110 ethernet device node to support gmac driver for the JH7110
RISC-V SoC.

Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

riscv: dts: starfive: jh7110: Add PLL clocks source in SYSCRG node

Add PLL clocks input from PLL clocks driver in SYSCRG node.

Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

riscv: dts: starfive: jh7110: Add syscon nodes

Add stg_syscon/sys_syscon/aon_syscon/PLL nodes for JH7110 SoC.

Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Co-developed-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

riscv: dts: starfive: jh7110: Add STGCRG/ISPCRG/VOUTCRG nodes

Add STGCRG/ISPCRG/VOUTCRG new node to support JH7110
System-Top-Group, Image-Signal-Process and Video-Output
clock and reset drivers for the JH7110 RISC-V SoC.

Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

riscv: dts: starfive: jh7110: Add DVP and HDMI TX pixel external clocks

Add DVP and HDMI TX pixel external fixed clocks and the rates are
74.25MHz and 297MHz.

Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

riscv: dts: starfive: Add cpu scaling for JH7110 SoC

Add the operating-points-v2 to support cpu scaling on StarFive JH7110 SoC.
It supports up to 4 cpu frequency loads.

Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

riscv: dts: starfive: jh7110: Add watchdog node

Add the watchdog node for the Starfive JH7110 SoC.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: Walker Chen <walker.chen@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

riscv: dts: starfive: Add PMU controller node

Add the pmu controller node for the StarFive JH7110 SoC. The PMU needs
to be used by other modules, e.g. VPU,ISP,etc.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

riscv: dts: starfive: Add initial StarFive JH7110 device tree

Add initial device tree for the JH7110 RISC-V SoC by StarFive
Technology Ltd.

Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
[conor: squashed in the removal of the S7's non-existent mmu]
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>