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98eb30fe |
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24-Oct-2023 |
Michael Ellerman <mpe@ellerman.id.au> |
powerpc: Make cpu_spec __ro_after_init The cpu_spec is a struct holding various information about the CPU the kernel is executing on. It's populated early in boot and must not change after that. In particular the cpu_features and mmu_features hold the set of discovered CPU/MMU features and are used to set static keys for each feature, and do binary patching of assembly. So any change to the cpu_features/mmu_features later in boot will not be reflected in the state of the static keys or patched code. There is already logic to check that cpu_features/mmu_features don't change, see check_features() in feature-fixups.c. But as another layer of protection the entire cpu_spec should be read only after init, annotate it as such. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20231025012452.1985680-1-mpe@ellerman.id.au
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26e04120 |
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11-Jul-2023 |
Christophe Leroy <christophe.leroy@csgroup.eu> |
powerpc/kuap: Use MMU_FTR_KUAP on all and refactor disabling kuap All but book3s/64 use a static branch key for disabling kuap. book3s/64 uses an mmu feature. Refactor all targets to use MMU_FTR_KUAP like book3s/64. For PPC32 that implies updating mmu features fixups once KUAP has been initialised. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/6b3d7c977bad73378ea368bc6818e9c94ea95ab0.1689091022.git.christophe.leroy@csgroup.eu
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e320a76d |
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19-Sep-2022 |
Christophe Leroy <christophe.leroy@csgroup.eu> |
powerpc/cputable: Split cpu_specs[] out of cputable.h cpu_specs[] is full of #ifdefs depending on the different types of CPU. CPUs are mutually exclusive, it is therefore possible to split cpu_specs[] into smaller more readable pieces. Create cpu_specs_XXX.h that will each be dedicated on one of the following mutually exclusive families: - 40x - 44x - 47x - 8xx - e500 - book3s/32 - book3s/64 In book3s/32, the block for 603 has been moved in front in order to not have two 604 blocks. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> [mpe: Fix CONFIG_47x to be CONFIG_PPC_47x, tweak some formatting] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/a44b865e0318286155273b10cdf524ab697928c1.1663606875.git.christophe.leroy@csgroup.eu
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76b71988 |
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19-Sep-2022 |
Christophe Leroy <christophe.leroy@csgroup.eu> |
powerpc/cputable: Move __cpu_setup() prototypes out of cputable.h Move all prototypes out of cputable.h For that rename cpu_setup_power.h to cpu_setup.h and move all prototypes in it. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> [mpe: Standardise cpu_spec *spec formatting] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/f45118489ee450db654db8bbcdfd8f5907337c22.1663606875.git.christophe.leroy@csgroup.eu
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afd2288a |
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19-Sep-2022 |
Christophe Leroy <christophe.leroy@csgroup.eu> |
powerpc/cputable: Remove __machine_check_early_realmode_p{7/8/9} prototypes __machine_check_early_realmode_p{7/8/9} are already in mce.h which is included. Remove them from cputable.c Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/b77fc0f90e3a9c065324cbff549b718ccf0809f8.1663606875.git.christophe.leroy@csgroup.eu
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0069f3d1 |
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19-Sep-2022 |
Christophe Leroy <christophe.leroy@csgroup.eu> |
powerpc/64e: Tie PPC_BOOK3E_64 to PPC_E500MC The only 64-bit Book3E CPUs we support require the selection of CONFIG_PPC_E500MC. However our Kconfig allows configurating a kernel that has 64-bit Book3E support, but without CONFIG_PPC_E500MC enabled. Such a kernel would never boot, it doesn't know about any CPUs. To fix this, force CONFIG_PPC_E500MC to be selected whenever we are building a 64-bit Book3E kernel. And add a test to detect future situations where cpu_specs is empty. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/ae5d8b8b3ccc346e61d2ec729767f92766273f0b.1663606875.git.christophe.leroy@csgroup.eu
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62ccae78 |
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07-Jul-2022 |
Christophe Leroy <christophe.leroy@csgroup.eu> |
powerpc: Remove remaining parts of oprofile Commit 9850b6c69356 ("arch: powerpc: Remove oprofile") removed oprofile. Remove all remaining parts of it. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/298432fe1a14c0a415760011d72c3f0999efd5e2.1657204631.git.christophe.leroy@csgroup.eu
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26b78c81 |
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02-May-2022 |
Reza Arbab <arbab@linux.ibm.com> |
powerpc: Enable the DAWR on POWER9 DD2.3 and above The hardware bug in POWER9 preventing use of the DAWR was fixed in DD2.3. Set the CPU_FTR_DAWR feature bit on these newer systems to start using it again, and update the documentation accordingly. The CPU features for DD2.3 are currently determined by "DD2.2 or later" logic. In adding DD2.3 as a discrete case for the first time here, I'm carrying the quirks of DD2.2 forward to keep all behavior outside of this DAWR change the same. This leaves the assessment and potential removal of those quirks on DD2.3 for later. Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220503170152.23412-1-arbab@linux.ibm.com
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d9e5c3e9 |
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29-Mar-2022 |
Kevin Hao <haokexin@gmail.com> |
powerpc: Export mmu_feature_keys[] as non-GPL When the mmu_feature_keys[] was introduced in the commit c12e6f24d413 ("powerpc: Add option to use jump label for mmu_has_feature()"), it is unlikely that it would be used either directly or indirectly in the out of tree modules. So we exported it as GPL only. But with the evolution of the codes, especially the PPC_KUAP support, it may be indirectly referenced by some primitive macro or inline functions such as get_user() or __copy_from_user_inatomic(), this will make it impossible to build many non GPL modules (such as ZFS) on ppc architecture. Fix this by exposing the mmu_feature_keys[] to the non-GPL modules too. Fixes: 7613f5a66bec ("powerpc/64s/kuap: Use mmu_has_feature()") Reported-by: Nathaniel Filardo <nwfilardo@gmail.com> Signed-off-by: Kevin Hao <haokexin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220329085709.4132729-1-haokexin@gmail.com
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e6f6390a |
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08-Mar-2022 |
Christophe Leroy <christophe.leroy@csgroup.eu> |
powerpc: Add missing headers Don't inherit headers "by chances" from asm/prom.h, asm/mpc52xx.h, asm/pci.h etc... Include the needed headers, and remove asm/prom.h when it was needed exclusively for pulling necessary headers. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/be8bdc934d152a7d8ee8d1a840d5596e2f7d85e0.1646767214.git.christophe.leroy@csgroup.eu
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1fd02f66 |
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30-Apr-2022 |
Julia Lawall <Julia.Lawall@inria.fr> |
powerpc: fix typos in comments Various spelling mistakes in comments. Detected with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220430185654.5855-1-Julia.Lawall@inria.fr
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7a3c90df |
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14-Jan-2021 |
Viresh Kumar <viresh.kumar@linaro.org> |
arch: powerpc: Stop building and using oprofile The "oprofile" user-space tools don't use the kernel OPROFILE support any more, and haven't in a long time. User-space has been converted to the perf interfaces. This commits stops building oprofile for powerpc and removes any reference to it from directories in arch/powerpc/ apart from arch/powerpc/oprofile, which will be removed in the next commit (this is broken into two commits as the size of the commit became very big, ~5k lines). Note that the member "oprofile_cpu_type" in "struct cpu_spec" isn't removed as it was also used by other parts of the code. Suggested-by: Christoph Hellwig <hch@infradead.org> Suggested-by: Linus Torvalds <torvalds@linux-foundation.org> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Robert Richter <rric@kernel.org> Acked-by: William Cohen <wcohen@redhat.com> Acked-by: Al Viro <viro@zeniv.linux.org.uk> Acked-by: Thomas Gleixner <tglx@linutronix.de>
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44e9754d |
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22-Oct-2020 |
Christophe Leroy <christophe.leroy@csgroup.eu> |
powerpc/32s: Make support for 603 and 604+ selectable book3s/32 has two main families: - CPU with 603 cores that don't have HASH PTE table and perform SW TLB loading. - Other CPUs based on 604+ cores that have HASH PTE table. This leads to some complex logic and additionnal code to support both. This makes sense for distribution kernels that aim at running on any CPU, but when you are fine tuning a kernel for an embedded 603 based board you don't need all the HASH logic. Allow selection of support for each family, in order to opt out unneeded parts of code. At least one must be selected. Note that some of the CPU supporting HASH also support SW TLB loading, however it is not supported by Linux kernel at the time being, because they do not have alternate registers in the TLB miss exception handlers. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/8dde0cdb629a71abc29b0d85a52a86e920376cb6.1603348103.git.christophe.leroy@csgroup.eu
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ad510e37 |
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22-Oct-2020 |
Christophe Leroy <christophe.leroy@csgroup.eu> |
powerpc/32s: Regroup 603 based CPUs in cputable In order to selectively build the kernel for 603 SW TLB handling, regroup all 603 based CPUs together. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/45065263fdb9f5cc2a2d210ec2a762ac8bf5b2bc.1603348103.git.christophe.leroy@csgroup.eu
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a6a50d84 |
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22-Oct-2020 |
Christophe Leroy <christophe.leroy@csgroup.eu> |
powerpc/32s: Remove CONFIG_PPC_BOOK3S_6xx As 601 is gone, CONFIG_PPC_BOO3S_6xx and CONFIG_PPC_BOOK3S_32 are dedundant. Remove CONFIG_PPC_BOOK3S_6xx. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/f18c16af37f6f77b577bed8d9e12831b695617ae.1603348103.git.christophe.leroy@csgroup.eu
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39c8bf2b |
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16-Nov-2020 |
Christophe Leroy <christophe.leroy@csgroup.eu> |
powerpc: Retire e200 core (mpc555x processor) There is no defconfig selecting CONFIG_E200, and no platform. e200 is an earlier version of booke, a predecessor of e500, with some particularities like an unified cache instead of both an instruction cache and a data cache. Remove it. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Acked-by: Scott Wood <oss@buserror.net> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/34ebc3ba2c768d97f363bd5f2deea2356e9ae127.1605589460.git.christophe.leroy@csgroup.eu
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8b8319b1 |
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18-Oct-2020 |
Christophe Leroy <christophe.leroy@csgroup.eu> |
powerpc/44x: Don't support 440 when CONFIG_PPC_47x is set As stated in platform/44x/Kconfig, CONFIG_PPC_47x is not compatible with 440 and 460 variants. This is confirmed in asm/cache.h as L1_CACHE_SHIFT is different for 47x, meaning a kernel built for 47x will not run correctly on a 440. In cputable, opt out all 440 and 460 variants when CONFIG_PPC_47x is set. Also add a default match dedicated to 470. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/822833ce3dc10634339818f7d1ab616edf63b0c6.1603041883.git.christophe.leroy@csgroup.eu
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344fbab9 |
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14-Oct-2020 |
Jordan Niethe <jniethe5@gmail.com> |
powerpc/64s: Convert some cpu_setup() and cpu_restore() functions to C The only thing keeping the cpu_setup() and cpu_restore() functions used in the cputable entries for Power7, Power8, Power9 and Power10 in assembly was cpu_restore() being called before there was a stack in generic_secondary_smp_init(). Commit ("powerpc/64: Set up a kernel stack for secondaries before cpu_restore()") means that it is now possible to use C. Rewrite the functions in C so they are a little bit easier to read. This is not changing their functionality. Signed-off-by: Jordan Niethe <jniethe5@gmail.com> [mpe: Tweak copyright and authorship notes] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20201014072837.24539-2-jniethe5@gmail.com
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ec613a57 |
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26-Aug-2020 |
Jordan Niethe <jniethe5@gmail.com> |
powerpc/64s: Remove TM from Power10 features ISA v3.1 removes transactional memory and hence it should not be present in cpu_features or cpu_user_features2. Remove CPU_FTR_TM_COMP from CPU_FTRS_POWER10. Remove PPC_FEATURE2_HTM_COMP and PPC_FEATURE2_HTM_NOSC_COMP from COMMON_USER2_POWER10. Fixes: a3ea40d5c736 ("powerpc: Add POWER10 architected mode") Signed-off-by: Jordan Niethe <jniethe5@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20200827035529.900-1-jniethe5@gmail.com
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f0ed73f3 |
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29-Sep-2020 |
Christophe Leroy <christophe.leroy@csgroup.eu> |
powerpc: Remove PowerPC 601 Powerpc 601 is 25 years old. It is not selected by any defconfig. It requires a lot of special handling as it deviates from the standard 6xx. Retire it. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/00a6948d659e017f8ca63437d1384222c3aede57.1601362098.git.christophe.leroy@csgroup.eu
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9983efa8 |
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15-Sep-2020 |
Nicholas Piggin <npiggin@gmail.com> |
powerpc: untangle cputable mce include Having cputable.h include mce.h means it pulls in a bunch of low level headers (e.g., synch.h) which then can't use CPU_FTR_ definitions. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20200916030234.4110379-1-npiggin@gmail.com
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388692e9 |
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16-Aug-2020 |
Madhavan Srinivasan <maddy@linux.ibm.com> |
powerpc/kernel: Cleanup machine check function declarations __machine_check_early_realmode_p*() are currently declared as extern in cputable.c and because of this when compiled with "C=1" (which enables semantic checker) produces these warnings. CHECK arch/powerpc/kernel/mce_power.c arch/powerpc/kernel/mce_power.c:709:6: warning: symbol '__machine_check_early_realmode_p7' was not declared. Should it be static? arch/powerpc/kernel/mce_power.c:717:6: warning: symbol '__machine_check_early_realmode_p8' was not declared. Should it be static? arch/powerpc/kernel/mce_power.c:722:6: warning: symbol '__machine_check_early_realmode_p9' was not declared. Should it be static? arch/powerpc/kernel/mce_power.c:740:6: warning: symbol '__machine_check_early_realmode_p10' was not declared. Should it be static? Patch here moves the declaration to asm/mce.h and includes the same in cputable.c Fixes: ae744f3432d3 ("powerpc/book3s: Flush SLB/TLBs if we get SLB/TLB machine check errors on power8") Fixes: 7b9f71f974a1 ("powerpc/64s: POWER9 machine check handler") Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20200817005618.3305028-1-maddy@linux.ibm.com
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327da008 |
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16-Aug-2020 |
Madhavan Srinivasan <maddy@linux.ibm.com> |
powerpc: Add POWER10 raw mode cputable entry Add a raw mode cputable entry for POWER10. Copies most of the fields from commit a3ea40d5c736 ("powerpc: Add POWER10 architected mode") except for oprofile_cpu_type, machine_check_early, pvr_mask and pvr_mask fields. On bare metal systems we use DT CPU features, which doesn't need a cputable entry. But in VMs we still rely on the raw cputable entry to set the correct values for the PMU related fields. Fixes: a3ea40d5c736 ("powerpc: Add POWER10 architected mode") Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com> [mpe: Reorder vs cleanup patch and add Fixes tag] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20200817005618.3305028-2-maddy@linux.ibm.com
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7fa95f9a |
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11-Jun-2020 |
Nicholas Piggin <npiggin@gmail.com> |
powerpc/64s: system call support for scv/rfscv instructions Add support for the scv instruction on POWER9 and later CPUs. For now this implements the zeroth scv vector 'scv 0', as identical to 'sc' system calls, with the exception that LR is not preserved, nor are volatile CR registers, and error is not indicated with CR0[SO], but by returning a negative errno. rfscv is implemented to return from scv type system calls. It can not be used to return from sc system calls because those are defined to preserve LR. getpid syscall throughput on POWER9 is improved by 26% (428 to 318 cycles), largely due to reducing mtmsr and mtspr. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> [mpe: Fix ppc64e build] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20200611081203.995112-3-npiggin@gmail.com
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a3ea40d5 |
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20-May-2020 |
Alistair Popple <alistair@popple.id.au> |
powerpc: Add POWER10 architected mode PVR value of 0x0F000006 means we are arch v3.1 compliant (i.e. POWER10). This is used by phyp and kvm when booting as a pseries guest to detect the presence of new P10 features and to enable the appropriate hwcap and facility bits. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> [mpe: Fall through to __init_FSCR rather than duplicating it, drop hack to set current->thread.fscr now that is handled elsewhere.] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20200521014341.29095-8-alistair@popple.id.au
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7d372d4c |
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21-May-2020 |
Christophe Leroy <christophe.leroy@c-s.fr> |
powerpc/40x: Remove support for IBM 405GP All platforms selecting the obsolete processor are gone now. Remove support for it. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/906c6a6df710f2826e332b8a0cd5d2859a913a1c.1590079969.git.christophe.leroy@csgroup.eu
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7583b63c |
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21-May-2020 |
Christophe Leroy <christophe.leroy@c-s.fr> |
powerpc/40x: Remove STB03xxx CONFIG_STB03xxx is not user selectable and is not selected by any config. Remove it. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/d7d73f9a8ee3a890566abace568101e9b4836016.1590079968.git.christophe.leroy@csgroup.eu
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1b5c0967 |
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21-May-2020 |
Christophe Leroy <christophe.leroy@c-s.fr> |
powerpc/40x: Remove support for IBM 403GCX CONFIG_403GCX is not user selectable and is not selected by any platform. Remove it. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/635f8f5ce9d1f761b3bd8dc3e8ddad500cea26c4.1590079968.git.christophe.leroy@csgroup.eu
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7ade8495 |
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21-May-2020 |
Michal Simek <michal.simek@xilinx.com> |
powerpc: Remove Xilinx PPC405/PPC440 support The latest Xilinx design tools called ISE and EDK has been released in October 2013. New tool doesn't support any PPC405/PPC440 new designs. These platforms are no longer supported and tested. PowerPC 405/440 port is orphan from 2013 by commit cdeb89943bfc ("MAINTAINERS: Fix incorrect status tag") and commit 19624236cce1 ("MAINTAINERS: Update Grant's email address and maintainership") that's why it is time to remove the support fot these platforms. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/8c593895e2cb57d232d85ce4d8c3a1aa7f0869cc.1590079968.git.christophe.leroy@csgroup.eu
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41b8426f |
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14-Feb-2020 |
Leonardo Bras <leobras.c@gmail.com> |
powerpc/cputable: Remove unnecessary copy of cpu_spec->oprofile_type Before checking for cpu_type == NULL, this same copy happens, so doing it here will just write the same value to the t->oprofile_type again. Remove the repeated copy, as it is unnecessary. Signed-off-by: Leonardo Bras <leonardo@linux.ibm.com> Reviewed-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20200215053637.280880-1-leonardo@linux.ibm.com
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fc37a163 |
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27-Feb-2020 |
Desnes A. Nunes do Rosario <desnesn@linux.ibm.com> |
powerpc: fix hardware PMU exception bug on PowerVM compatibility mode systems PowerVM systems running compatibility mode on a few Power8 revisions are still vulnerable to the hardware defect that loses PMU exceptions arriving prior to a context switch. The software fix for this issue is enabled through the CPU_FTR_PMAO_BUG cpu_feature bit, nevertheless this bit also needs to be set for PowerVM compatibility mode systems. Fixes: 68f2f0d431d9ea4 ("powerpc: Add a cpu feature CPU_FTR_PMAO_BUG") Signed-off-by: Desnes A. Nunes do Rosario <desnesn@linux.ibm.com> Reviewed-by: Leonardo Bras <leonardo@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20200227134715.9715-1-desnesn@linux.ibm.com
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12c3f1fd |
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26-Aug-2019 |
Christophe Leroy <christophe.leroy@c-s.fr> |
powerpc/32s: get rid of CPU_FTR_601 feature Now that 601 is exclusive from other 6xx, CPU_FTR_601 and associated fixups are useless. Drop this feature and use #ifdefs instead. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/ecdb7194a17dbfa01865df6a82979533adc2c70b.1566834712.git.christophe.leroy@c-s.fr
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2874c5fd |
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27-May-2019 |
Thomas Gleixner <tglx@linutronix.de> |
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152 Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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adcf5918 |
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26-Apr-2019 |
Christophe Leroy <christophe.leroy@c-s.fr> |
powerpc: don't use direct assignation during early boot. In kernel/cputable.c, explicitly use memcpy() instead of *y = *x; This will allow GCC to replace it with __memcpy() when KASAN is selected. Acked-by: Dmitry Vyukov <dvyukov@google.com> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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0deae39c |
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10-Dec-2018 |
Christophe Leroy <christophe.leroy@c-s.fr> |
powerpc/83xx: handle machine check caused by watchdog timer When the watchdog timer is set in interrupt mode, it causes a machine check when it times out. The purpose of this mode is to ease debugging, not to crash the kernel and reboot the machine. This patch implements a special handling for that, in order to not crash the kernel if the watchdog times out while in interrupt or within the idle task. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> [scottwood: added missing #include] Signed-off-by: Scott Wood <oss@buserror.net>
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2bf1071a |
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05-Jul-2018 |
Nicholas Piggin <npiggin@gmail.com> |
powerpc/64s: Remove POWER9 DD1 support POWER9 DD1 was never a product. It is no longer supported by upstream firmware, and it is not effectively supported in Linux due to lack of testing. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Michael Ellerman <mpe@ellerman.id.au> [mpe: Remove arch_make_huge_pte() entirely] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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e11b64b1 |
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11-Jul-2018 |
Joel Stanley <joel@jms.id.au> |
powerpc: Remove Power8 DD1 from cputable This was added to support an early version of Power8 that did not have working doorbells. These machines were not publicly available, and all of the internal users have long since upgraded. Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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471d7ff8 |
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20-Feb-2018 |
Nicholas Piggin <npiggin@gmail.com> |
powerpc/64s: Remove POWER4 support POWER4 has been broken since at least the change 49d09bf2a6 ("powerpc/64s: Optimise MSR handling in exception handling"), which requires mtmsrd L=1 support. This was introduced in ISA v2.01, and POWER4 supports ISA v2.00. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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4bb3c7a0 |
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21-Mar-2018 |
Paul Mackerras <paulus@ozlabs.org> |
KVM: PPC: Book3S HV: Work around transactional memory bugs in POWER9 POWER9 has hardware bugs relating to transactional memory and thread reconfiguration (changes to hardware SMT mode). Specifically, the core does not have enough storage to store a complete checkpoint of all the architected state for all four threads. The DD2.2 version of POWER9 includes hardware modifications designed to allow hypervisor software to implement workarounds for these problems. This patch implements those workarounds in KVM code so that KVM guests see a full, working transactional memory implementation. The problems center around the use of TM suspended state, where the CPU has a checkpointed state but execution is not transactional. The workaround is to implement a "fake suspend" state, which looks to the guest like suspended state but the CPU does not store a checkpoint. In this state, any instruction that would cause a transition to transactional state (rfid, rfebb, mtmsrd, tresume) or would use the checkpointed state (treclaim) causes a "soft patch" interrupt (vector 0x1500) to the hypervisor so that it can be emulated. The trechkpt instruction also causes a soft patch interrupt. On POWER9 DD2.2, we avoid returning to the guest in any state which would require a checkpoint to be present. The trechkpt in the guest entry path which would normally create that checkpoint is replaced by either a transition to fake suspend state, if the guest is in suspend state, or a rollback to the pre-transactional state if the guest is in transactional state. Fake suspend state is indicated by a flag in the PACA plus a new bit in the PSSCR. The new PSSCR bit is write-only and reads back as 0. On exit from the guest, if the guest is in fake suspend state, we still do the treclaim instruction as we would in real suspend state, in order to get into non-transactional state, but we do not save the resulting register state since there was no checkpoint. Emulation of the instructions that cause a softpatch interrupt is handled in two paths. If the guest is in real suspend mode, we call kvmhv_p9_tm_emulation_early() to handle the cases where the guest is transitioning to transactional state. This is called before we do the treclaim in the guest exit path; because we haven't done treclaim, we can get back to the guest with the transaction still active. If the instruction is a case that kvmhv_p9_tm_emulation_early() doesn't handle, or if the guest is in fake suspend state, then we proceed to do the complete guest exit path and subsequently call kvmhv_p9_tm_emulation() in host context with the MMU on. This handles all the cases including the cases that generate program interrupts (illegal instruction or TM Bad Thing) and facility unavailable interrupts. The emulation is reasonably straightforward and is mostly concerned with checking for exception conditions and updating the state of registers such as MSR and CR0. The treclaim emulation takes care to ensure that the TEXASR register gets updated as if it were the guest treclaim instruction that had done failure recording, not the treclaim done in hypervisor state in the guest exit path. With this, the KVM_CAP_PPC_HTM capability returns true (1) even if transactional memory is not available to host userspace. Signed-off-by: Paul Mackerras <paulus@ozlabs.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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b5af4f27 |
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21-Mar-2018 |
Paul Mackerras <paulus@ozlabs.org> |
powerpc: Add CPU feature bits for TM bug workarounds on POWER9 v2.2 This adds a CPU feature bit which is set for POWER9 "Nimbus" DD2.2 processors which will be used to enable the hypervisor to assist hardware with the handling of checkpointed register values while the CPU is in suspend state, in order to work around hardware bugs. The hardware assistance for these workarounds introduced a new hardware bug relating to the XER[SO] bit. We add a separate feature bit for this bug in case future chips fix it while still requiring the hypervisor assistance with suspend state. When the dt_cpu_ftrs subsystem is in use, the software assistance can be enabled using a "tm-suspend-hypervisor-assist" node in the device tree, and a "tm-suspend-xer-so-bug" node enables the workarounds for the XER[SO] bug. In the absence of such nodes, a quirk enables both for POWER9 "Nimbus" DD2.2 processors. Signed-off-by: Paul Mackerras <paulus@ozlabs.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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d4748276 |
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23-Dec-2017 |
Nicholas Piggin <npiggin@gmail.com> |
powerpc/64s: Improve local TLB flush for boot and MCE on POWER9 There are several cases outside the normal address space management where a CPU's entire local TLB is to be flushed: 1. Booting the kernel, in case something has left stale entries in the TLB (e.g., kexec). 2. Machine check, to clean corrupted TLB entries. One other place where the TLB is flushed, is waking from deep idle states. The flush is a side-effect of calling ->cpu_restore with the intention of re-setting various SPRs. The flush itself is unnecessary because in the first case, the TLB should not acquire new corrupted TLB entries as part of sleep/wake (though they may be lost). This type of TLB flush is coded inflexibly, several times for each CPU type, and they have a number of problems with ISA v3.0B: - The current radix mode of the MMU is not taken into account, it is always done as a hash flushn For IS=2 (LPID-matching flush from host) and IS=3 with HV=0 (guest kernel flush), tlbie(l) is undefined if the R field does not match the current radix mode. - ISA v3.0B hash must flush the partition and process table caches as well. - ISA v3.0B radix must flush partition and process scoped translations, partition and process table caches, and also the page walk cache. So consolidate the flushing code and implement it in C and inline asm under the mm/ directory with the rest of the flush code. Add ISA v3.0B cases for radix and hash, and use the radix flush in radix environment. Provide a way for IS=2 (LPID flush) to specify the radix mode of the partition. Have KVM pass in the radix mode of the guest. Take out the flushes from early cputable/dt_cpu_ftrs detection hooks, and move it later in the boot process after, the MMU registers are set up and before relocation is first turned on. The TLB flush is no longer called when restoring from deep idle states. This was not be done as a separate step because booting secondaries uses the same cpu_restore as idle restore, which needs the TLB flush. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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3ffa9d9e |
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14-Nov-2017 |
Michael Ellerman <mpe@ellerman.id.au> |
powerpc/64s: Fix Power9 DD2.0 workarounds by adding DD2.1 feature Recently we added a CPU feature for Power9 DD2.0, to capture the fact that some workarounds are required only on Power9 DD1 and DD2.0 but not DD2.1 or later. Then in commit 9d2f510a66ec ("powerpc/64s/idle: avoid POWER9 DD1 and DD2.0 ERAT workaround on DD2.1") and commit e3646330cf66 "powerpc/64s/idle: avoid POWER9 DD1 and DD2.0 PMU workaround on DD2.1") we changed CPU_FTR_SECTIONs to check for DD1 or DD20, eg: BEGIN_FTR_SECTION PPC_INVALIDATE_ERAT END_FTR_SECTION_IFSET(CPU_FTR_POWER9_DD1 | CPU_FTR_POWER9_DD20) Unfortunately although this reads as "if set DD1 or DD2.0", the or is a bitwise or and actually generates a mask of both bits. The code that does the feature patching then checks that the value of the CPU features masked with that mask are equal to the mask. So the end result is we're checking for DD1 and DD20 being set, which never happens. Yes the API is terrible. Removing the ERAT workaround on DD2.0 results in random SEGVs, the system tends to boot, but things randomly die including sometimes dhclient, udev etc. To fix the problem and hopefully avoid it in future, we remove the DD2.0 CPU feature and instead add a DD2.1 (or later) feature. This allows us to easily express that the workarounds are required if DD2.1 is not set. At some point we will drop the DD1 workarounds entirely and some of this can be cleaned up. Fixes: 9d2f510a66ec ("powerpc/64s/idle: avoid POWER9 DD1 and DD2.0 ERAT workaround on DD2.1") Fixes: e3646330cf66 ("powerpc/64s/idle: avoid POWER9 DD1 and DD2.0 PMU workaround on DD2.1") Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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b6b3755e |
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02-Nov-2017 |
Nicholas Piggin <npiggin@gmail.com> |
powerpc: add POWER9_DD20 feature Cc: Michael Neuling <mikey@neuling.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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3ee87674 |
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08-Aug-2017 |
Christophe Leroy <christophe.leroy@c-s.fr> |
powerpc/8xx: Use symbolic PVR value For the 8xx, PVR values defined in arch/powerpc/include/asm/reg.h are nowhere used. Remove all defines and add PVR_8xx Use it in arch/powerpc/kernel/cputable.c Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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968159c0 |
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08-Aug-2017 |
Christophe Leroy <christophe.leroy@c-s.fr> |
powerpc/8xx: Getting rid of remaining use of CONFIG_8xx Two config options exist to define powerpc MPC8xx: * CONFIG_PPC_8xx * CONFIG_8xx arch/powerpc/platforms/Kconfig.cputype has contained the following comment about CONFIG_8xx item for some years: "# this is temp to handle compat with arch=ppc" arch/powerpc is now the only place with remaining use of CONFIG_8xx: get rid of them. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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13fef7f9 |
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08-Aug-2017 |
Michael Ellerman <mpe@ellerman.id.au> |
powerpc/47x: Guard 47x cputable entries with CONFIG_PPC_47x Currently we build the 47x cputable entries even when CONFIG_PPC_47x is disabled. That means a kernel built without CONFIG_PPC_47x will claim to support a 47x CPU and start booting, only to break somewhere later because it doesn't have 47x support compiled in. So guard the 47x cputable entries with CONFIG_PPC_47x. Note that this is inside the #ifdef CONFIG_44x section, because 47x depends on 44x. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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a4700a26 |
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19-May-2017 |
Nicholas Piggin <npiggin@gmail.com> |
powerpc: Add PPC_FEATURE userspace bits for SCV and DARN instructions Providing "scv" support to userspace requires kernel support, so it must be advertised as independently to the base ISA 3 instruction set. The darn instruction relies on firmware enablement, so it has been decided to split this out from the core ISA 3 feature as well. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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5a61ef74 |
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08-May-2017 |
Nicholas Piggin <npiggin@gmail.com> |
powerpc/64s: Support new device tree binding for discovering CPU features The ibm,powerpc-cpu-features device tree binding describes CPU features with ASCII names and extensible compatibility, privilege, and enablement metadata that allows improved flexibility and compatibility with new hardware. The interface is described in detail in ibm,powerpc-cpu-features.txt in this patch. Currently this code is not enabled by default, and there are no released firmwares that provide the binding. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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7b9f71f9 |
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27-Feb-2017 |
Nicholas Piggin <npiggin@gmail.com> |
powerpc/64s: POWER9 machine check handler Add POWER9 machine check handler. There are several new types of errors added, so logging messages for those are also added. This doesn't attempt to reuse any of the P7/8 defines or functions, because that becomes too complex. The better option in future is to use a table driven approach. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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6ae3f8ad |
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16-Feb-2017 |
Russell Currey <ruscur@russell.cc> |
powerpc: Add POWER9 architected mode to cputable PVR value of 0x0F000005 means we are arch v3.00 compliant (i.e. POWER9). Acked-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Russell Currey <ruscur@russell.cc> [mpe: Don't set num_pmcs, so we keep the PMU fields from the raw entry] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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e627f8dc |
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16-Sep-2016 |
Christophe Leroy <christophe.leroy@c-s.fr> |
powerpc/8xx: add dedicated machine check handler During a machine check, the 8xx provides indication of whether the check is due to data or instruction access, so let's display it. Lets also move 8xx specific handling into the new handler. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Scott Wood <oss@buserror.net>
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7dccfbc3 |
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24-Aug-2016 |
Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> |
powerpc/book3s: Add a cpu table entry for different POWER9 revs Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Acked-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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c12e6f24 |
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23-Jul-2016 |
Kevin Hao <haokexin@gmail.com> |
powerpc: Add option to use jump label for mmu_has_feature() As we just did for CPU features. Signed-off-by: Kevin Hao <haokexin@gmail.com> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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4db73271 |
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23-Jul-2016 |
Kevin Hao <haokexin@gmail.com> |
powerpc: Add option to use jump label for cpu_has_feature() We do binary patching of asm code using CPU features, which is a one-time operation, done during early boot. However checks of CPU features in C code are currently done at run time, even though the set of CPU features can never change after boot. We can optimise this by using jump labels to implement cpu_has_feature(), meaning checks in C code are binary patched into a single nop or branch. For a C sequence along the lines of: if (cpu_has_feature(FOO)) return 2; The generated code before is roughly: ld r9,-27640(r2) ld r9,0(r9) lwz r9,32(r9) cmpwi cr7,r9,0 bge cr7, 1f li r3,2 blr 1: ... After (true): nop li r3,2 blr After (false): b 1f li r3,2 blr 1: ... mpe: Rename MAX_CPU_FEATURES as we already have a #define with that name, and define it simply as a constant, rather than doing tricks with sizeof and NULL pointers. Rename the array to cpu_feature_keys. Use the kconfig we added to guard it. Add BUILD_BUG_ON() if the feature is not a compile time constant. Rewrite the change log. Signed-off-by: Kevin Hao <haokexin@gmail.com> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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accfad7d |
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13-Jul-2016 |
Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> |
powerpc/mm: Clear top 16 bits of va only on older cpus As per ISA, we need to do this only for architecture version 2.02 and earlier. This continued to work even for 2.07. But let's not do this for anything after 2.02. ISA 3.0 requires these top bits to be not cleared. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Acked-by: Balbir Singh <bsingharora@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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c415c9cb |
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11-Apr-2016 |
Rashmica Gupta <rashmicy@gmail.com> |
powerpc: Remove unused remnants from A2 cpu Support for the A2 cpu was removed in commit fb5a515704d7 ("powerpc: Remove platforms/wsp and associated pieces"), and the externs: __setup_cpu_a2 and __restore_cpu_a2 are still around and unused, so remove them. Signed-off-by: Rashmica Gupta <rashmicy@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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e7affb1d |
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20-Nov-2015 |
chenhui zhao <chenhui.zhao@freescale.com> |
powerpc/cache: add cache flush operation for various e500 Various e500 core have different cache architecture, so they need different cache flush operations. Therefore, add a callback function cpu_flush_caches to the struct cpu_spec. The cache flush operation for the specific kind of e500 is selected at init time. The callback function will flush all caches inside the current cpu. Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Signed-off-by: Tang Yuantian <Yuantian.Tang@feescale.com> Signed-off-by: Scott Wood <oss@buserror.net>
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c3ab300e |
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18-Feb-2016 |
Michael Neuling <mikey@neuling.org> |
powerpc: Add POWER9 cputable entry Add a cputable entry for POWER9. More code is required to actually boot and run on a POWER9 but this gets the base piece in which we can start building on. Copies over from POWER8 except for: - Adds a new CPU_FTR_ARCH_300 bit to start hanging new architecture features from (in subsequent patches). - Advertises new user features bits PPC_FEATURE2_ARCH_3_00 & HAS_IEEE128 when on POWER9. - Drops CPU_FTR_SUBCORE. - Drops PMU code and machine check. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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b4b56f9e |
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11-Jun-2015 |
Sam bobroff <sam.bobroff@au1.ibm.com> |
powerpc/tm: Abort syscalls in active transactions This patch changes the syscall handler to doom (tabort) active transactions when a syscall is made and return very early without performing the syscall and keeping side effects to a minimum (no CPU accounting or system call tracing is performed). Also included is a new HWCAP2 bit, PPC_FEATURE2_HTM_NOSC, to indicate this behaviour to userspace. Currently, the system call instruction automatically suspends an active transaction which causes side effects to persist when an active transaction fails. This does change the kernel's behaviour, but in a way that was documented as unsupported. It doesn't reduce functionality as syscalls will still be performed after tsuspend; it just requires that the transaction be explicitly suspended. It also provides a consistent interface and makes the behaviour of user code substantially the same across powerpc and platforms that do not support suspended transactions (e.g. x86 and s390). Performance measurements using http://ozlabs.org/~anton/junkcode/null_syscall.c indicate the cost of a normal (non-aborted) system call increases by about 0.25%. Signed-off-by: Sam Bobroff <sam.bobroff@au1.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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ddee09c0 |
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18-Mar-2015 |
Benjamin Herrenschmidt <benh@kernel.crashing.org> |
powerpc: Add PVR for POWER8NVL processor There's a new variant of POWER8 coming called "POWER8 with NVLink". The core is identical to POWER8 but unfortunately they strapped it with a different PVR, so we need to add an explicit entry for it. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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45706bb5 |
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18-Dec-2014 |
Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> |
powerpc/book3s: Fix flush_tlb cpu_spec hook to take a generic argument. The flush_tlb hook in cpu_spec was introduced as a generic function hook to invalidate TLBs. But the current implementation of flush_tlb hook takes IS (invalidation selector) as an argument which is architecture dependent. Hence, It is not right to have a generic routine where caller has to pass non-generic argument. This patch fixes this and makes flush_tlb hook as high level API. Reported-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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974ff4e2 |
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05-Jan-2015 |
Esben Haabendal <eha@deif.com> |
powerpc: Add machine_check cpu function for e300c3 cpus Signed-off-by: Esben Haabendal <eha@deif.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
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3477e71d |
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20-Aug-2014 |
Mihai Caraman <mihai.caraman@freescale.com> |
powerpc/booke: Restrict SPE exception handlers to e200/e500 cores SPE exception handlers are now defined for 32-bit e500mc cores even though SPE unit is not present and CONFIG_SPE is undefined. Restrict SPE exception handlers to e200/e500 cores adding CONFIG_SPE_POSSIBLE and consequently guard __stup_ivors and __setup_cpu functions. Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
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1e07a0a0 |
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09-Jul-2014 |
Michael Ellerman <mpe@ellerman.id.au> |
powerpc: Remove CLASSIC_PPC We have a strange #define in cputable.h called CLASSIC_PPC. Although it is defined for 32 & 64bit, it's only used for 32bit and it's basically a duplicate of CONFIG_PPC_BOOK3S_32, so let's use the latter. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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468a3302 |
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09-Jul-2014 |
Michael Ellerman <mpe@ellerman.id.au> |
powerpc: Drop support for pre-POWER4 cpus We inadvertently broke power3 support back in 3.4 with commit f5339277eb8d "powerpc: Remove FW_FEATURE ISERIES from arch code". No one noticed until at least 3.9. By then we'd also broken it with the optimised memcpy, copy_to/from_user and clear_user routines. We don't want to add any more complexity to those just to support ancient cpus, so it seems like it's a good time to drop support for power3 and earlier. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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bd6ba351 |
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17-Jul-2014 |
Joel Stanley <joel@jms.id.au> |
powerpc: Disable doorbells on Power8 DD1.x These processors do not currently support doorbell IPIs, so remove them from the feature list if we are at DD 1.xx for the 0x004d part. This fixes a regression caused by d4e58e5928f8 (powerpc/powernv: Enable POWER8 doorbell IPIs). With that patch the kernel would hang at boot when calling smp_call_function_many, as the doorbell would not be received by the target CPUs: .smp_call_function_many+0x2bc/0x3c0 (unreliable) .on_each_cpu_mask+0x30/0x100 .cpuidle_register_driver+0x158/0x1a0 .cpuidle_register+0x2c/0x110 .powernv_processor_idle_init+0x23c/0x2c0 .do_one_initcall+0xd4/0x260 .kernel_init_freeable+0x25c/0x33c .kernel_init+0x1c/0x120 .ret_from_kernel_thread+0x58/0x7c Fixes: d4e58e5928f8 (powerpc/powernv: Enable POWER8 doorbell IPIs) Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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fb5a5157 |
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01-Jun-2014 |
Michael Ellerman <mpe@ellerman.id.au> |
powerpc: Remove platforms/wsp and associated pieces __attribute__ ((unused)) WSP is the last user of CONFIG_PPC_A2, so we remove that as well. Although CONFIG_PPC_ICSWX still exists, it's no longer selectable for any Book3E platform, so we can remove the code in mmu-book3e.h that depended on it. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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#
dd58a092 |
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09-Jun-2014 |
Benjamin Herrenschmidt <benh@kernel.crashing.org> |
powerpc: Add AT_HWCAP2 to indicate V.CRYPTO category support The Vector Crypto category instructions are supported by current POWER8 chips, advertise them to userspace using a specific bit to properly differentiate with chips of the same architecture level that might not have them. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> CC: <stable@vger.kernel.org> [v3.10+]
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#
68f2f0d4 |
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13-Mar-2014 |
Michael Ellerman <mpe@ellerman.id.au> |
powerpc: Add a cpu feature CPU_FTR_PMAO_BUG Some power8 revisions have a hardware bug where we can lose a Performance Monitor (PMU) exception under certain circumstances. We will be adding a workaround for this case, see the next commit for details. The observed behaviour is that writing PMAO doesn't cause an exception as we would expect, hence the name of the feature. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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#
ae744f34 |
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30-Oct-2013 |
Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> |
powerpc/book3s: Flush SLB/TLBs if we get SLB/TLB machine check errors on power8. This patch handles the memory errors on power8. If we get a machine check exception due to SLB or TLB errors, then flush SLBs/TLBs and reload SLBs to recover. Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Acked-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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#
e22a2274 |
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30-Oct-2013 |
Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> |
powerpc/book3s: Flush SLB/TLBs if we get SLB/TLB machine check errors on power7. If we get a machine check exception due to SLB or TLB errors, then flush SLBs/TLBs and reload SLBs to recover. We do this in real mode before turning on MMU. Otherwise we would run into nested machine checks. If we get a machine check when we are in guest, then just flush the SLBs and continue. This patch handles errors for power7. The next patch will handle errors for power8 Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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#
04407050 |
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30-Oct-2013 |
Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> |
powerpc/book3s: Add flush_tlb operation in cpu_spec. This patch introduces flush_tlb operation in cpu_spec structure. This will help us to invoke appropriate CPU-side flush tlb routine. This patch adds the foundation to invoke CPU specific flush routine for respective architectures. Currently this patch introduce flush_tlb for p7 and p8. Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Acked-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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#
5815c434 |
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05-Jun-2013 |
Lijun Pan <LIJUN.PAN@FREESCALE.COM> |
powerpc/perf: add 2 additional performance monitor counters for e6500 core There are 6 counters in e6500 core instead of 4 in e500 core. Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
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#
33959f88 |
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17-Jul-2013 |
Michael Neuling <mikey@neuling.org> |
powerpc: Add second POWER8 PVR entry POWER8 comes with two different PVRs. This patch enables the additional PVR in the cputable. The existing entry (PVR=0x4b) is renamed to POWER8E and the new entry (PVR=0x4d) is given POWER8. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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#
6a60f9e7 |
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04-Jun-2013 |
Michael Neuling <mikey@neuling.org> |
powerpc/power8: Fix oprofile and perf In 2ac6f42 powerpc/cputable: Fix oprofile_cpu_type on power8 we broke all power8 hw events. This reverts this change and uses oprofile_type instead. Perf now works on POWER8 again and oprofile will revert to using timers on POWER8. Kudos to mpe this fix. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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#
badec11b |
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19-May-2013 |
Will Schmidt <will_schmidt@vnet.ibm.com> |
powerpc/cputable: Fix typo on P7+ cputable entry Fix a typo in setting COMMON_USER2_POWER7 bits to .cpu_user_features2 cpu specs table. Signed-off-by: Will Schmidt <will_schmidt@vnet.ibm.com> Acked-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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#
2ac6f427 |
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28-May-2013 |
Nishanth Aravamudan <nacc@linux.vnet.ibm.com> |
powerpc/cputable: Fix oprofile_cpu_type on power8 Maynard informed me that neither the oprofile kernel module nor oprofile userspace has been updated to support that "legacy" oprofile module interface for power8, which is indicated by "ppc64/power8." This results in no samples. The solution is to default to the "timer" type, instead. The raw entry also should be updated, as "ppc64/ibm-compat-v1" indicates to oprofile userspace to use "compatibility events" which are obsolete in ISA 2.07. Signed-off-by: Nishanth Aravamudan <nacc@us.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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#
748645bf |
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03-May-2013 |
Nishanth Aravamudan <nacc@linux.vnet.ibm.com> |
powerpc/cputable: Advertise support for ISEL/HTM/DSCR/TAR on POWER8 Signed-off-by: Nishanth Aravamudan <nacc@us.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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#
6c1bf482 |
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04-May-2013 |
Nishanth Aravamudan <nacc@linux.vnet.ibm.com> |
powerpc/cputable: Advertise ISEL support on appropriate embedded processors Signed-off-by: Nishanth Aravamudan <nacc@us.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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#
4a1ae4f3 |
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03-May-2013 |
Nishanth Aravamudan <nacc@linux.vnet.ibm.com> |
powerpc/cputable: Advertise DSCR support on P7/P7+ Signed-off-by: Nishanth Aravamudan <nacc@us.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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#
d63ac5f6 |
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12-Mar-2013 |
Benjamin Herrenschmidt <benh@kernel.crashing.org> |
powerpc: Fix cputable entry for 970MP rev 1.0 Commit 44ae3ab3358e962039c36ad4ae461ae9fb29596c forgot to update the entry for the 970MP rev 1.0 processor when moving some CPU features bits to the MMU feature bit mask. This breaks booting on some rare G5 models using that chip revision. Reported-by: Phileas Fogg <phileas-fogg@mail.ru> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> CC: <stable@vger.kernel.org> [v3.0+]
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#
cd66cc2e |
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07-Sep-2012 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add AltiVec support for e6500 The e6500 core adds support for AltiVec on a Book-E class processor. Connect up all the various exception handling code and build config mechanisms to allow user spaces apps to utilize AltiVec. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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#
c674e703 |
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08-Nov-2012 |
Michael Neuling <mikey@neuling.org> |
powerpc: Add POWER8 architected mode to cputable A PVR of 0x0F000004 means we are arch v2.07 complicate ie, POWER8. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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#
71e18497 |
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30-Oct-2012 |
Michael Neuling <mikey@neuling.org> |
powerpc: POWER8 cputable entry Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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#
aec937b1 |
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30-Oct-2012 |
Michael Neuling <mikey@neuling.org> |
powerpc: Add POWER8 setup code Just a copy of POWER7 for now. Will update with new code later. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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#
2c71b0cc |
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09-Jul-2012 |
Varun Sethi <Varun.Sethi@freescale.com> |
powerpc/booke: Merge the 32 bit e5500/e500mc cpu setup code. Merge the 32 bit cpu setup code for e500mc/e5500 and define the "cpu_restore" routine (for e5500/e6500) only for the 64 bit case. The cpu_restore routine is used in the 64 bit case for setting up the secondary cores. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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#
ae3a197e |
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28-Mar-2012 |
David Howells <dhowells@redhat.com> |
Disintegrate asm/system.h for PowerPC Disintegrate asm/system.h for PowerPC. Signed-off-by: David Howells <dhowells@redhat.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> cc: linuxppc-dev@lists.ozlabs.org
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#
7c801160 |
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19-Dec-2011 |
Vinh Nguyen Huu Tuong <vhtnguyen@apm.com> |
powerpc/44x: The bug fixed support for APM821xx SoC and Bluestone board This patch consists of: - Fix the pvr mask for checking pvr in cputable.c - Fix the cpu name as consistent with cpu name is describled in dts file Signed-off-by: Vinh Nguyen Huu Tuong <vhtnguyen@apm.com> Signed-off-by: Josh Boyer <jwboyer@gmail.com>
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#
10241842 |
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06-Nov-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc: Add initial e6500 cpu support Add basic support for e6500 core in its single threaded mode. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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#
df777bd3 |
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30-Nov-2011 |
Tony Breeds <tony@bakeyournoodle.com> |
powerpc/476fpe: Add 476fpe SoC code Based on original work by David 'Shaggy' Kleikamp. Signed-off-by: Tony Breeds <tony@bakeyournoodle.com> Signed-off-by: Josh Boyer <jwboyer@gmail.com>
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#
d5b9ee7b |
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28-Nov-2011 |
Tanmay Inamdar <tinamdar@apm.com> |
powerpc/40x: Add APM8018X SOC support The AppliedMicro APM8018X embedded processor targets embedded applications that require low power and a small footprint. It features a PowerPC 405 processor core built in a 65nm low-power CMOS process with a five-stage pipeline executing up to one instruction per cycle. The family has 128-kbytes of on-chip memory, a 128-bit local bus and on-chip DDR2 SDRAM controller with 16-bit interface. Signed-off-by: Tanmay Inamdar <tinamdar@apm.com> Signed-off-by: Josh Boyer <jwboyer@gmail.com>
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#
4b16f8e2 |
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22-Jul-2011 |
Paul Gortmaker <paul.gortmaker@windriver.com> |
powerpc: various straight conversions from module.h --> export.h All these files were including module.h just for the basic EXPORT_SYMBOL infrastructure. We can shift them off to the export.h header which is a way smaller footprint and thus realize some compile time gains. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
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#
26ee9767 |
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25-Jul-2011 |
Scott Wood <scottwood@freescale.com> |
powerpc: Return the_cpu_ spec from identify_cpu Commit af9eef3c7b1ed004c378c89b87642f4937337d50 caused cpu_setup to see the_cpu_spec, rather than the source struct. However, on 32-bit, the return value of identify_cpu was being used for feature fixups, and identify_cpu was returning the source struct. So if cpu_setup patches the feature bits, the update won't affect the fixups. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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#
fb9be234 |
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02-Jun-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/book3e: Fix CPU feature handling on e5500 in 32-bit mode We are missing FPU feature bit that user space may require. In the 64-bit mode this gets set since we pull it in via COMMON_USER_PPC64. We just explicitly set it so user space will be happy again. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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#
44ae3ab3 |
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06-Apr-2011 |
Matt Evans <matt@ozlabs.org> |
powerpc: Free up some CPU feature bits by moving out MMU-related features Some of the 64bit PPC CPU features are MMU-related, so this patch moves them to MMU_FTR_ bits. All cpu_has_feature()-style tests are moved to mmu_has_feature(), and seven feature bits are freed as a result. Signed-off-by: Matt Evans <matt@ozlabs.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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#
76b4eda8 |
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14-Apr-2011 |
Benjamin Herrenschmidt <benh@kernel.crashing.org> |
powerpc: Add A2 cpu support Add the cputable entry, regs and setup & restore entries for the PowerPC A2 core. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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#
24cc67de |
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20-Jan-2011 |
Benjamin Herrenschmidt <benh@kernel.crashing.org> |
powerpc: Define CPU feature for Architected 2.06 HV mode This bit indicates that we are operating in hypervisor mode on a CPU compliant to architecture 2.06 or later (currently server only). We set it on POWER7 and have a boot-time CPU setup function that clears it if MSR:HV isn't set (booting under a hypervisor). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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#
11ed0db9 |
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05-Apr-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/book3e: Fix CPU feature handling on 64-bit e5500 The CPU_FTRS_POSSIBLE and CPU_FTRS_ALWAYS defines did not encompass e5500 CPU features when built for 64-bit. This causes issues with cpu_has_feature() as it utilizes the POSSIBLE & ALWAYS defines as part of its check. Create a unique CPU_FTRS_E5500 (as its different from CPU_FTRS_E500MC), created a new group for 64-bit Book3e based CPUs and add CPU_FTRS_E5500 to that group. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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#
af9eef3c |
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20-Jan-2011 |
Benjamin Herrenschmidt <benh@kernel.crashing.org> |
powerpc: Pass the right cpu_spec to ->setup_cpu() on 64-bit When calling setup_cpu() on 64-bit, we pass a pointer to the cputable entry we have found. This used to be fine when cur_cpu_spec was a pointer to that entry, but nowadays, we copy the entry into a separate variable, and we do so before we call the setup_cpu() callback. That means that any attempt by that callback at patching the CPU table entry (to adjust CPU features for example) will patch the wrong table. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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#
c48d0dba |
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25-Jan-2011 |
Dave Kleikamp <shaggy@linux.vnet.ibm.com> |
powerpc/476: define specific cpu table entry DD2 core The DD2 core still has some unstability. Define CPU_FTR_476_DD2 to enable workarounds in later patches. This is based on an earlier, unreleased patch for DD1 by Ben Herrenschmidt. Signed-off-by: Dave Kleikamp <shaggy@linux.vnet.ibm.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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#
fbe754ca |
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11-Jan-2011 |
Anton Blanchard <anton@samba.org> |
powerpc: machine_check_generic is wrong on 64bit Decoding machine checks is CPU specific and so machine_check_generic doesn't do the right thing on 64bit chips. Luckily we never call into this code because we call ppc_md.machine_check_exception instead if available. Since we check cur_cpu_spec->machine_check before calling it, we may as well remove machine_check_generic from 64bit archs. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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#
6f08cb3b |
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17-Nov-2010 |
Michael Neuling <mikey@neuling.org> |
powerpc: Add POWER7+ cputable entry This adds the POWER7+ cputable entry for the PVR 0x004a0000. Rest is the same as vanilla POWER7. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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#
1d32bb18 |
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17-Nov-2010 |
Michael Neuling <mikey@neuling.org> |
powerpc: Remove POWER6 oprofile workarounds for POWER7 These are not needed on POWER7 so remove them. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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#
93fe56e9 |
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17-Nov-2010 |
Michael Neuling <mikey@neuling.org> |
powerpc: Remove unneeded cpu_setup/restore from POWER7 cputable entry These are not needed so just remove them Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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#
4490c06b |
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08-Oct-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/fsl-booke: Add support for FSL 64-bit e5500 core The new e5500 core is similar to the e500mc core but adds 64-bit support. We support running it in 32-bit mode as it is identical to the e500mc. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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#
6edc323d |
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13-Sep-2010 |
Tirumala Marri <tmarri@apm.com> |
powerpc/44x: Add support for the AMCC APM821xx SoC This patch adds CPU, device tree, defconfig and bluestone board support for APM821xx SoC. Signed-off-by: Tirumala R Marri <tmarri@apm.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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#
66477466 |
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18-Aug-2010 |
Dave Kleikamp <shaggy@linux.vnet.ibm.com> |
powerpc/47x: Remove redundant line from cputable.c There are two entries for .cpu_user_features in arch/powerpc/kernel/cputable.c. Remove the one that doesn't belong Signed-off-by: Dave Kleikamp <shaggy@linux.vnet.ibm.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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#
ff349103 |
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08-Jul-2010 |
Lee Nipper <lee.nipper@gmail.com> |
powerpc/40x: Distinguish AMCC PowerPC 405EX and 405EXr correctly The recent AMCC 405EX Rev D without Security uses a PVR value that matches the old 405EXr Rev A/B with Security. The 405EX Rev D without Security would be shown incorrectly as an 405EXr. The pvr_mask of 0xffff0004 is no longer sufficient to distinguish the 405EX from 405EXr. This patch replaces 2 entries in the cpu_specs table and adds 8 more, each using pvr_mask of 0xffff000f and appropriate pvr_value to distinguish the AMCC PowerPC 405EX and 405EXr instances. The cpu_name for these entries now includes the Rev, in similar fashion to the 440GX. Signed-off-by: Lee Nipper <lee.nipper@gmail.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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#
fe04b112 |
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07-Apr-2010 |
Scott Wood <scottwood@freescale.com> |
powerpc/e500mc: Implement machine check handler. Most of the MSCR bit assigments are different in e500mc versus e500, and they are now write-one-to-clear. Some e500mc machine check conditions are made recoverable (as long as they aren't stuck on), most notably L1 instruction cache parity errors. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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#
b4e8c8dd |
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05-Mar-2010 |
Torez Smith <lnxtorez@linux.vnet.ibm.com> |
powerpc/4xx: Simple platform for the ISS 4xx simulator This is a trivial 4xx plaform that uses the new simple bsp from Josh and is handy to use in simulators such as ISS or even Mambo who don't properly implement most of the actual devices in the SoC but really only the core. Signed-off-by: Torez Smith <lnxtorez@linux.vnet.ibm.com> Signed-off-by: Dave Kleikamp <shaggy@linux.vnet.ibm.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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#
fc5e7097 |
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04-Mar-2010 |
Dave Kleikamp <shaggy@linux.vnet.ibm.com> |
powerpc/476: add machine check handler for 47x core The 47x core's MCSR varies from 44x, so it needs it's own machine check handler. Signed-off-by: Dave Kleikamp <shaggy@linux.vnet.ibm.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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#
e7f75ad0 |
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05-Mar-2010 |
Dave Kleikamp <shaggy@linux.vnet.ibm.com> |
powerpc/47x: Base ppc476 support This patch adds the base support for the 476 processor. The code was primarily written by Ben Herrenschmidt and Torez Smith, but I've been maintaining it for a while. The goal is to have a single binary that will run on 44x and 47x, but we still have some details to work out. The biggest is that the L1 cache line size differs on the two platforms, but it's currently a compile-time option. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Torez Smith <lnxtorez@linux.vnet.ibm.com> Signed-off-by: Dave Kleikamp <shaggy@linux.vnet.ibm.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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#
a1110654 |
|
25-Feb-2010 |
Scott Wood <scottwood@freescale.com> |
powerpc/perf: e500 support This implements perf_event support for the Freescale embedded performance monitor, based on the existing perf_event.c that supports server/classic chips. Some limitations: - Performance monitor interrupts are regular EE interrupts, and thus you can't profile places with interrupts disabled. We may want to implement soft IRQ-disabling, with perfmon interrupts exempted and treated as NMIs. - When trying to schedule multiple event groups at once, and using restricted events, situations could arise where scheduling fails even though it would be possible. Consider three groups, each with two events. One group has restricted events, the others don't. The two non-restricted groups are scheduled, then one is removed, which happens to occupy the two counters that can't do restricted events. The remaining non-restricted group will not be moved to the non-restricted-capable counters to make room if the restricted group tries to be scheduled. Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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#
45158dc7 |
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11-Dec-2009 |
Albert Herranz <albert_herranz@yahoo.es> |
powerpc: broadway processor support This patch extends the cputable entry of the 750CL to also match the 750CL-based "Broadway" cpu found on the Nintendo Wii. As of this patch, the following "Broadway" design revision levels have been seen in the wild: - DD1.2 (87102) - DD2.0 (87200) Signed-off-by: Albert Herranz <albert_herranz@yahoo.es> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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#
04f5653477 |
|
16-Sep-2009 |
Dragos Tatulea <dtatulea@ixiacom.com> |
powerpc/oprofile: Add ppc750 CL as supported by oprofile Here's a patch that adds the ppc750 CL cpu as supported by oprofile. Signed-off-by: Dragos Tatulea <dtatulea@ixiacom.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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#
f45c4486 |
|
18-Aug-2009 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/book3e-64: Move the default cpu table entry Move the default cpu entry table for CONFIG_PPC_BOOK3E_64 to the very end since we will probably want to support both 32-bit and 64-bit kernels for some processors that are higher up in the list. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
|
#
20d70345 |
|
29-Jul-2009 |
Stefan Roese <sr@denx.de> |
powerpc: Add AMCC 460EX/460GT Rev. B support to cputable.c Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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#
2d27cfd3 |
|
23-Jul-2009 |
Benjamin Herrenschmidt <benh@kernel.crashing.org> |
powerpc: Remaining 64-bit Book3E support This contains all the bits that didn't fit in previous patches :-) This includes the actual exception handlers assembly, the changes to the kernel entry, other misc bits and wiring it all up in Kconfig. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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#
60dbf438 |
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29-Apr-2009 |
Milton Miller <miltonm@bga.com> |
powerpc: Add 2.06 tlbie mnemonics This adds the PowerPC 2.06 tlbie mnemonics and keeps backwards compatibilty for CPUs before 2.06. Only useful for bare metal systems. Signed-off-by: Milton Miller <miltonm@bga.com> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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#
b173f03d |
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14-May-2009 |
Benjamin Herrenschmidt <benh@kernel.crashing.org> |
powerpc/pseries: Really fix the oprofile CPU type on pseries My previous pach for fixing the oprofile CPU type got somewhat mismerged (by my fault) when it collided with another related patch. This should finally (fingers crossed) fix the whole thing. We make sure we keep the -old- oprofile type and CPU type whenever one of them was specified in the first pass through the function. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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0203d6ec |
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29-Apr-2009 |
Benjamin Herrenschmidt <benh@kernel.crashing.org> |
powerpc: Fix setting of oprofile cpu type commit 2657dd4e301d4841ed67a4fac7d145ad8f3e1b28 introduced a bug where we would now always override the "real" oprofile CPU type with the "compatible" one provided by a pseudo-PVR in the device-tree which is incorrect and breaks oprofile on all current configs since the "compatible" ones aren't yet recognized. This fixes it. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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79af6c49 |
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27-Apr-2009 |
Michael Wolf <mjw@linux.vnet.ibm.com> |
powerpc adjust oprofile_cpu_type version 3 Oprofile is changing the naming it is using for the compatibility modes. Instead of having compat-power<x>, oprofile will go to family naming convention and use ibm-compat-v<x>. Currently only ibm-compat-v1 will be defined. The notion of compatibility events just started with POWER6. So there is no way that any other tool could exist that is using these oprofile_cpu_type strings we want to change. Signed-off-by: Mike Wolf <mjw@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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323d23ae |
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23-Apr-2009 |
Kumar Gala <galak@kernel.crashing.org> |
Revert "powerpc: Add support for early tlbilx opcode" This reverts commit e9965577406a2148ade97b5e0ce7c448b4ba4ef6. Our HW guys were able to fix this so it never sees the light of day. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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e9965577 |
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06-Apr-2009 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc: Add support for early tlbilx opcode During the ISA 2.06 development the opcode for tlbilx changed and some early implementations used to old opcode. Add support for a MMU_FTR fixup to deal with this. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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2319f123 |
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18-Mar-2009 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/mm: e300c2/c3/c4 TLB errata workaround Complete workaround for DTLB errata in e300c2/c3/c4 processors. Due to the bug, the hardware-implemented LRU algorythm always goes to way 1 of the TLB. This fix implements the proposed software workaround in form of a LRW table for chosing the TLB-way. Based on patch from David Jander <david@protonic.nl> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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7c9583a4 |
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03-Mar-2009 |
Octavian Purdila <opurdila@ixiacom.com> |
powerpc/oprofile: Enable support for ppc750 processors This patch enables oprofile for all 3 FX variants and GX variant of the 750 processor. Signed-off-by: Octavian Purdila <opurdila@ixiacom.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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2657dd4e |
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22-Feb-2009 |
Michael Ellerman <michael@ellerman.id.au> |
powerpc: Make sure we copy all cpu_spec features except PMC related ones When identify_cpu() is called a second time with a logical PVR, it only copies a subset of the cpu_spec fields so as to avoid overwriting the performance monitor fields that were initialized based on the real PVR. However some of the other, non performance monitor related fields are also not copied: * pvr_mask * pvr_value * mmu_features * machine_check The fact that pvr_mask is not copied can result in show_cpuinfo() showing the cpu as "unknown", if we override an unknown PVR with a logical one - as reported by Shaggy. So change the logic to copy all fields, and then put back the PMC related ones in the case that we're overwriting a real PVR with a logical one. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Dave Kleikamp <shaggy@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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#
666435bb |
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22-Feb-2009 |
Michael Ellerman <michael@ellerman.id.au> |
powerpc: Deindentify identify_cpu() The for-loop body of identify_cpu() has gotten a little big, so move the loop body logic into a separate function. No other changes. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Dave Kleikamp <shaggy@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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#
c3071951 |
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10-Feb-2009 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/fsl-booke: Add support for tlbilx instructions The e500mc core supports the new tlbilx instructions that do core local invalidates and also provide us the ability to take down all TLB entries matching a given PID. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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#
6c712090 |
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05-Feb-2009 |
Madhulika Madishetty <mmadishetty@amcc.com> |
AMCC PPC 460SX redwood SoC platform initial framework This patch contains initial framework for the AMCC Redwood board. Signed-off-by: Madhulika Madishetty <mmadishetty@amcc.com> Signed-off-by: Tirumala Marri <tmarri@amcc.com> Signed-off-by: Feng Kan <fkan@amcc.com> Signed-off-by: Vidhyananth Venkatasamy <vvenkatasamy@amcc.com> Signed-off-by: Preetesh Parekh <pparekh@amcc.com> Acked-by: Loc Ho <lho@amcc.com> Acked-by: Feng Kan <fkan@amcc.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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#
105c31df |
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08-Jan-2009 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/fsl-booke: Cleanup init/exception setup to be runtime We currently have a few variants of fsl-booke processors (e500v1, e500v2, e500mc, and e200). They all have minor differences that we had previously been handling via ifdefs. To move towards having this support the following changes have been made: * PID1, PID2 only exist on e500v1 & e500v2 and should not be accessed on e500mc or e200. We use MMUCFG[NPIDS] to determine which case we are since we only touch PID1/2 in extremely early init code. * Not all IVORs exist on all the processors so introduce cpu_setup functions for each variant to setup the proper IVORs that are either unique or exist but have some variations between the processors Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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#
7c03d653 |
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18-Dec-2008 |
Benjamin Herrenschmidt <benh@kernel.crashing.org> |
powerpc/mm: Introduce MMU features We're soon running out of CPU features and I need to add some new ones for various MMU related bits, so this patch separates the MMU features from the CPU features. I moved over the 32-bit MMU related ones, added base features for MMU type families, but didn't move over any 64-bit only feature yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
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#
6d2170be |
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18-Dec-2008 |
Benjamin Herrenschmidt <benh@kernel.crashing.org> |
powerpc/4xx: Extended DCR support v2 This adds supports to the "extended" DCR addressing via the indirect mfdcrx/mtdcrx instructions supported by some 4xx cores (440H6 and later). I enabled the feature for now only on AMCC 460 chips. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
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#
640d17d6 |
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03-Dec-2008 |
Grant Likely <grant.likely@secretlab.ca> |
powerpc/virtex5: Fix Virtex5 machine check handling The 440x5 core in the Virtex5 uses the 440A type machine check (ie, they have MCSRR0/MCSRR1). They thus need to call the appropriate fixup function to hook the right variant of the exception. Without this, all machine checks become fatal due to loss of context when entering the exception handler. Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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#
df8f71fa |
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09-Oct-2008 |
Josh Boyer <jwboyer@linux.vnet.ibm.com> |
powerpc/40x: Add AMCC PowerPC 405EZ to cputable This adds the AMCC PowerPC 405EZ chip to the cputable Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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#
b950bdd0 |
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17-Aug-2008 |
Benjamin Herrenschmidt <benh@kernel.crashing.org> |
powerpc: Expose PMCs & cache topology in sysfs on 32-bit The file arch/powerpc/kernel/sysfs.c is currently only compiled for 64-bit kernels. It contain code to register CPU sysdevs in sysfs and add various properties such as cache topology and raw access by root to performance monitor counters (PMCs). A lot of that can be re-used as is on 32-bits. This makes the file be built for both, with appropriate ifdef'ing for the few bits that are really 64-bit specific, and adds some support for the raw PMCs for 75x and 74xx processors. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
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#
fc532f81 |
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25-Jul-2008 |
Nathan Lynch <ntl@pobox.com> |
powerpc: Fix boot problem due to AT_BASE_PLATFORM change Commit 9115d13453dee22473a1e8cacc90a8d64a9c4bc9 ("powerpc: Enable AT_BASE_PLATFORM aux vector") broke boot on 32-bit powerpc systems; we have to use PTRRELOC to initialize powerpc_base_platform this early in boot. Bug reported by Jon Smirl. Signed-off-by: Nathan Lynch <ntl@pobox.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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9115d134 |
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15-Jul-2008 |
Nathan Lynch <ntl@pobox.com> |
powerpc: Enable AT_BASE_PLATFORM aux vector Stash the first platform string matched by identify_cpu() in powerpc_base_platform, and supply that to the ELF loader for the value of AT_BASE_PLATFORM. Signed-off-by: Nathan Lynch <ntl@pobox.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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#
79e25bac |
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17-Jul-2008 |
Torez Smith <lnxtorez@linux.vnet.ibm.com> |
powerpc: Indicate which oprofile counters to use while in compat mode While running on a system with new hardware and a kernel where the cpu_specs[] table does not recognize the new hardware, the identify_cpu() routine will select the default case as it searches through cpu_specs[] in an attempt to match the real PVR. Once the default case is selected, non of the oprofile counters and/or fields have been set up or defined. When identify_cpu() is called once more with the logical PVR, some of the cpu specific fields are replaced with the exception of the oprofile related ones. However, in the case where we have actually taken the default case while searching for the real PVR, we need to tell oprofile that we are now running in compatibility mode so it can pick up the correct counters. We do this by setting the oprofile_cpu_type field to be that taken from the cpu_specs[] for the cpu we are now emulating. This change will detect that we are now altering the real PVR and determine if we also need to update the oprofile_cpu_type field. Signed-off-by: Torez Smith <lnxtorez@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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#
0f473314 |
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09-Jul-2008 |
Nathan Lynch <ntl@pobox.com> |
powerpc: Add PPC_FEATURE_PSERIES_PERFMON_COMPAT Background from Maynard Johnson: As of POWER6, a set of 32 common events is defined that must be supported on all future POWER processors. The main impetus for this compat set is the need to support partition migration, especially from processor P(n) to processor P(n+1), where performance software that's running in the new partition may not be knowledgeable about processor P(n+1). If a performance tool determines it does not support the physical processor, but is told (via the PPC_FEATURE_PSERIES_PERFMON_COMPAT bit) that the processor supports the notion of the PMU compat set, then the performance tool can surface just those events to the user of the tool. PPC_FEATURE_PSERIES_PERFMON_COMPAT indicates that the PMU supports at least this basic subset of events which is compatible across POWER processor lines. Signed-off-by: Nathan Lynch <ntl@pobox.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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23e7237e |
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01-Jul-2008 |
John Linn <john.linn@xilinx.com> |
powerpc/virtex: add Xilinx 440 cpu to the cputable Updates the cputable to include the 440 processor found in the Xilinx Virtex5 FXT FPGA. Signed-off-by: John Linn <john.linn@xilinx.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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51c52e86 |
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23-Jun-2008 |
Michael Ellerman <michael@ellerman.id.au> |
powerpc: Split out do_feature_fixups() from cputable.c The logic to patch CPU feature sections lives in cputable.c, but these days it's used for CPU features as well as firmware features. Move it into it's own file for neatness and as preparation for some additions. While we're moving the code, we pull the loop body logic into a separate routine, and remove a comment which doesn't apply anymore. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
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b7bcda63 |
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23-Jun-2008 |
Michael Ellerman <michael@ellerman.id.au> |
powerpc: Add PPC_NOP_INSTR, a hash define for the preferred nop instruction A bunch of code has hard-coded the value for a "nop" instruction, it would be nice to have a #define for it. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
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#
635f5a63 |
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18-Jun-2008 |
Joel Schopp <jschopp@austin.ibm.com> |
powerpc: Add cputable entry for Power7 architected mode Add an entry for Power7 architected mode and add "(raw)" to Power7 raw mode to distinguish it more clearly. Signed-off-by: Joel Schopp <jschopp@austin.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
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#
e952e6c4 |
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17-Jun-2008 |
Michael Neuling <mikey@neuling.org> |
powerpc: Add cputable entry for POWER7 Add a cputable entry for the POWER7 processor. Also tell firmware that we know about POWER7. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Joel Schopp <jschopp@austin.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
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#
fc4033b2 |
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18-Jun-2008 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: add DOZE/NAP support for e500 core The e500 core enter DOZE/NAP power-saving modes when the core go to cpu_idle routine. The power management default running mode is DOZE, If the user echo 1 > /proc/sys/kernel/powersave-nap the system will change to NAP running mode. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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#
3dfa8773 |
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16-Jun-2008 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/booke: Add support for new e500mc core The new e500mc core from Freescale is based on the e500v2 but with the following changes: * Supports only the Enhanced Debug Architecture (DSRR0/1, etc) * Floating Point * No SPE * Supports lwsync * Doorbell Exceptions * Hypervisor * Cache line size is now 64-bytes (e500v1/v2 have a 32-byte cache line) Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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939e622c |
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11-Jun-2008 |
Josh Boyer <jwboyer@linux.vnet.ibm.com> |
Revert "[POWERPC] 4xx: Fix 460GT support to not enable FPU" This reverts commit acb0142bf01c0ebe18f09e37814451ee6a873e27. AMCC has indicated that the PPC 460GT does have FPU support. This revert enables the FPU for those chips again. Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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#
516c8be3 |
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11-May-2008 |
Paul Mackerras <paulus@samba.org> |
[POWERPC] Fix default cputable entries for e200 and e500 families Commit 76bc080ef5a34aedb63e1691f28c6b42f3468e4e ("POWERPC] Make default cputable entries reflect selected CPU family") added default entries for the e200 and e500 families, but missed a closing brace on those entries, as pointed out by David Gibson. This adds the closing braces. Signed-off-by: Paul Mackerras <paulus@samba.org>
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76bc080e |
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04-May-2008 |
Benjamin Herrenschmidt <benh@kernel.crashing.org> |
[POWERPC] Make default cputable entries reflect selected CPU family Changes the cputable so that various CPU families that have an exclusive CONFIG_ option have a more sensible default entry to use if the specific processor hasn't been identified. This makes the kernel more generally useful when booted on an unknown PVR for things like new 4xx variants. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
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acb0142b |
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19-Apr-2008 |
Stefan Roese <sr@denx.de> |
[POWERPC] 4xx: Fix 460GT support to not enable FPU The AMCC 460GT doesn't have an FPU so let's not enable support for it. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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464076a4 |
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23-Feb-2008 |
Stefan Roese <sr@denx.de> |
[POWERPC] 4xx: Add AMCC 460EX/460GT support to cputable.c & cpu_setup_44x.S This patch adds basic support for the AMCC 460EX/460GT PPC's to arch/powerpc. Currently those PPC's are still based on a 440 core and *not* a 460 core. Here some basic features of those SoC's: 460EX: - Up to 1.2GHz, 32kB L1 I-cache and D-cache, 256kB L2-cache, FPU - 1 * PCI (max 66MHz), 2 * PCIe (one 4-lane, one 1-lane) - 2 * GBit Ethernet with TCP/IP acceleration - USB 2.0 Host/Device OTG and Host interface - SATA controller - Optional security feature 460GT (only changes to 460EX): - 4 * GBit Ethernet with TCP/IP acceleration - RapidIO - No SATA - No USB Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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1347a2c1 |
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04-Feb-2008 |
Andy Fleming <afleming@freescale.com> |
[POWERPC} Add oprofile support for e300 The e300 c3 and c4 variants support hardware performance monitor counters which are identical to those found in the e500. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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39aef685 |
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04-Feb-2008 |
Andy Fleming <afleming@freescale.com> |
[POWERPC] Made FSL Book-E PMC support more generic Some of the more recent e300 cores have the same performance monitor implementation as the e500. e300 isn't book-e, so the name isn't really appropriate. In preparation for e300 support, rename a bunch of fsl_booke things to say fsl_emb (Freescale Embedded Performance Monitors). Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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#
3f8fc3e0 |
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09-Jan-2008 |
Sean MacLennan <smaclennan@pikatech.com> |
[POWERPC] 4xx: Add PowerPC 440EP Rev C This adds the 440EP revision C PVR to the CPU table. The chip has an FPU on it, so we also match the logical PVR Signed-off-by: Sean MacLennan <smaclennan@pikatech.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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#
b676d84e |
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15-Jan-2008 |
Stefan Roese <sr@denx.de> |
[POWERPC] 4xx: Add 405EXr to cputable This patch adds the 405EXr to the powerpc cuptable. Basically the 405EXr is a 405EX with only one EMAC and only one PCIe interface. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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#
e3e414bc |
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24-Dec-2007 |
Josh Boyer <jwboyer@linux.vnet.ibm.com> |
[POWERPC] Conditionally compile e200 and e500 platforms in cputable The e200 and e500 platforms are separated in various parts of the kernel with ifdefs, most notably reg_booke.h and traps.c. The new machine_check rework requires them to be similarly separated in cputable.c to avoid compile errors. Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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#
b2be3b15 |
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21-Dec-2007 |
Valentine Barshak <vbarshak@ru.mvista.com> |
[POWERPC] 4xx: Correct 440GRx machine_check callback Correct the PowerPC 440GRx machine check callback. Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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#
47c0bd1a |
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20-Dec-2007 |
Benjamin Herrenschmidt <benh@kernel.crashing.org> |
[POWERPC] Reworking machine check handling and Fix 440/440A This adds a cputable function pointer for the CPU-side machine check handling. The semantic is still the same as the old one, the one in ppc_md. overrides the one in cputable, though ultimately we'll want to change that so the CPU gets first. This removes CONFIG_440A which was a problem for multiplatform kernels and instead fixes up the IVOR at runtime from a setup_cpu function. The "A" version of the machine check also tweaks the regs->trap value to differenciate the 2 versions at the C level. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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#
a58d5244 |
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19-Oct-2007 |
Li Yang <leoyang.li@nxp.com> |
[POWERPC] add e300c4 entry to cputable Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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#
d1dfc35d |
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25-Oct-2007 |
Valentine Barshak <vbarshak@ru.mvista.com> |
[POWERPC] 4xx: Workaround for the 440EP(x)/GR(x) processors identical PVR issue. PowerPC 440EP(x) 440GR(x) processors have the same PVR values, since they have identical cores. However, FPU is not supported on GR(x) and enabling APU instruction broadcast in the CCR0 register (to enable FPU) may cause unpredictable results. There's no safe way to detect FPU support at runtime. This patch provides a workarund for the issue. We use a POWER6 "logical PVR approach". First, we identify all EP(x) and GR(x) processors as GR(x) ones (which is safe). Then we check the device tree cpu path. If we have a EP(x) processor entry, we call identify_cpu again with PVR | 0x8. This bit is always 0 in the real PVR. This way we enable FPU only for 440EP(x). Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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#
5d8476c8 |
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11-Oct-2007 |
Stefan Roese <sr@denx.de> |
[POWERPC] 4xx: Add AMCC 405EX support to cputable.c Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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#
87a72f9e |
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03-Oct-2007 |
Paul Mackerras <paulus@samba.org> |
[POWERPC] Fix performance monitor on machines with logical PVR Some IBM machines supply a "logical" PVR (processor version register) value in the device tree in the cpu nodes rather than the real PVR. This is used for instance to indicate that the processors in a POWER6 partition have been configured by the hypervisor to run in POWER5+ mode rather than POWER6 mode. To cope with this, we call identify_cpu a second time with the logical PVR value (the first call is with the real PVR value in the very early setup code). However, POWER5+ machines can also supply a logical PVR value, and use the same value (the value that indicates a v2.04 architecture compliant processor). This causes problems for code that uses the performance monitor (such as oprofile), because the PMU registers are different in POWER6 (even in POWER5+ mode) from the real POWER5+. This change works around this problem by taking out the PMU information from the cputable entries for the logical PVR values, and changing identify_cpu so that the second call to it won't overwrite the PMU information that was established by the first call (the one with the real PVR), but does update the other fields. Specifically, if the cputable entry for the logical PVR value has num_pmcs == 0, none of the PMU-related fields get used. So that we can create a mixed cputable entry, we now make cur_cpu_spec point to a single static struct cpu_spec, and copy stuff from cpu_specs[i] into it. This has the side-effect that we can now make cpu_specs[] be initdata. Ultimately it would be good to move the PMU-related fields out to a separate structure, pointed to by the cputable entries, and change identify_cpu so that it saves the PMU info pointer, copies the whole structure, and restores the PMU info pointer, rather than identify_cpu having to list all the fields that are *not* PMU-related. Signed-off-by: Paul Mackerras <paulus@samba.org> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
|
#
340ffd26 |
|
21-Sep-2007 |
Valentine Barshak <vbarshak@ru.mvista.com> |
[POWERPC] 4xx: 440EPx/GRx incorrect write to DDR SDRAM errata workaround Add a workaround for PowerPC 440EPx/GRx incorrect write to DDR SDRAM errata. Data can be written to wrong address in SDRAM when write pipelining enabled on plb0. We disable it in the cpu_setup for these processors at early init. Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
|
#
8112753b |
|
21-Sep-2007 |
Valentine Barshak <vbarshak@ru.mvista.com> |
[POWERPC] 4xx: Move 440EP(x) FPU setup from head_44x to cpu_setup_4xx The PowerPC 440EP(x) FPU init is currently done in head_44x under ifdefs. Since we should support more then one board in the same kernel, we move FPU initialization code from head_44x to cpu_setup_44x and add cpu_setup callbacks for 440EP(x). Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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#
84e3ad5b |
|
21-Sep-2007 |
Valentine Barshak <vbarshak@ru.mvista.com> |
[POWERPC] 4xx: Introduce cpu_setup functionality to 44x platform This adds cpu_setup functionality for ppc44x platform. Low level cpu-spefic initialization routines should be placed in cpu_setup_44x.S and a callback should be added to cputable. The cpu_setup is invoked by identify_cpu() function at early init. Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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#
5e14d21e |
|
13-Sep-2007 |
Kumar Gala <galak@kernel.crashing.org> |
[POWERPC] Add cpu feature for SPE handling Make it so that SPE support can be determined at runtime. This is similiar to how we handle AltiVec. This allows us to have SPE support built in and work on processors with and without SPE. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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#
15fc993e |
|
29-Aug-2007 |
Valentine Barshak <vbarshak@ru.mvista.com> |
[POWERPC] PowerPC 440EPx: Sequoia board support AMCC PPC440EPx Sequoia board support. Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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#
31a12cec |
|
10-Jul-2007 |
Mike Wolf <mjw@linux.vnet.ibm.com> |
[POWERPC] Oprofile support for Power 5++ This adds a new oprofile cpu type for Power 5 revision 3 chips. The new name is ppc64/power5++ and is used so that the performance counters can be set up correctly. Signed-off-by: Mike Wolf <mjw@us.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
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#
333e6154 |
|
15-Jun-2007 |
Roland Dreier <rdreier@cisco.com> |
[POWERPC] Add cputable entry for PowerPC 440SPe Rev. B When adding the cputable entry for 440SPe Rev. B, we also need to adjust the existing entries for 440SP Rev. A and 440SPe Rev. B so that they look more bits of the PVR. The 440SPe Rev. B has PVR 53421891, which would match the current 440SP Rev. A pattern of 53xxx891. To distinguish between 440SP and 440SPe, we need to use the first three digits of the PVR, which are respectively 532 and 534. Signed-off-by: Roland Dreier <rolandd@cisco.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
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#
2fae4985 |
|
18-May-2007 |
Anton Blanchard <anton@samba.org> |
[POWERPC] Add missing pmc_type fields in cpu_table A number of cpu_table entries were missing the pmc_type field, which means that the sysfs entries for the performance monitor counters don't get created. This adds them. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
|
#
3d372548 |
|
02-May-2007 |
James.Yang <James.Yang@freescale.com> |
[POWERPC] Remove CPU_FTR_NEED_COHERENT for 7448. Remove CPU_FTR_NEED_COHERENT for MPC7448 (and single-core MPC86xx). This prevents needlessly setting M=1 when not SMP. Signed-off-by: James.Yang <James.Yang@freescale.com> Acked-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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#
25fc530e |
|
18-Apr-2007 |
Olof Johansson <olof@lixom.net> |
[POWERPC] pasemi: PA6T oprofile support Oprofile support for PA6T, kernel side. Also rename the PA6T_SPRN.* defines to SPRN_PA6T.*. Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Paul Mackerras <paulus@samba.org>
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#
a14c4508 |
|
12-Apr-2007 |
Josh Boyer <jwboyer@linux.vnet.ibm.com> |
[POWERPC] Fix PowerPC 750CL and 750GX CPU features PowerPC 750CL has high BATs. The patch below adds a CPU_FTRS_750CL that includes that. Without it, the original firmware mappings in the high BATs aren't cleared which continue to override the linux translations. It also adds CPU_FTR_COMMON to CPU_FTRS_750GX for completeness. Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
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#
cfbff8a3 |
|
03-Oct-2006 |
Jake Moilanen <moilanen@austin.ibm.com> |
[POWERPC] 750CL cputable entry 750CL cputable entry from Steve Winiecki. Signed-off-by: Jake Moilanen <moilanen@austin.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
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#
3546e811 |
|
25-Feb-2007 |
Olof Johansson <olof@lixom.net> |
[POWERPC] No DEEPNAP on 970MP 1.0 970MP rev 1.0 is reported to have nonworking DEEPNAP support, we've had bug reports of lockups on those machines. Appearantly Apple used them on some dual-core dual-cpu systems. Rev 1.1 is OK, and that's the one that all 4-way systems seem to use. Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Paul Mackerras <paulus@samba.org>
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#
40d244d6 |
|
12-Feb-2007 |
Stephen Rothwell <sfr@canb.auug.org.au> |
[POWERPC] correct a prototype This rids us of a warning. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
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#
1199919b |
|
04-Feb-2007 |
Olof Johansson <olof@lixom.net> |
[POWERPC] pasemi: Idle loops Powersave support on PA6T. Right now it only uses 'doze' mode, and will default to no savings (spin). Signed-off-by: Olof Johansson <olof@lixom.net> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Paul Mackerras <paulus@samba.org>
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#
1bd2e5ae |
|
28-Jan-2007 |
Olof Johansson <olof@lixom.net> |
[POWERPC] Add PMC type to cputable Add cputable entries for which type of PMC implementation the processor has. I've only filled in the current 64-bit processors, the unfilled default value will have same behaviour as before so it can be done over time as needed. Also tidy up the dummy_perf implementation a bit, aggregating it into one function with ifdefs instead of several. Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Paul Mackerras <paulus@samba.org>
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#
a147c585 |
|
08-Dec-2006 |
Kumar Gala <galak@kernel.crashing.org> |
[POWERPC] Fix 440SPe CPU table entry The 440SPe CPU table entry was missing the CPU_FTR_NODSISRALIGN and really should have been CPU_FTRS_44X. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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#
aa42c69c |
|
08-Dec-2006 |
Kim Phillips <kim.phillips@freescale.com> |
[POWERPC] Add support for FP emulation for the e300c2 core The e300c2 has no FPU. Its MSR[FP] is grounded to zero. If an attempt is made to execute a floating point instruction (including floating-point load, store, or move instructions), the e300c2 takes a floating-point unavailable interrupt. This patch adds support for FP emulation on the e300c2 by declaring a new CPU_FTR_FP_TAKES_FPUNAVAIL, where FP unavail interrupts are intercepted and redirected to the ProgramCheck exception path for correct emulation handling. (If we run out of CPU_FTR bits we could look to reclaim this bit by adding support to test the cpu_user_features for PPC_FEATURE_HAS_FPU instead) It adds a nop to the exception path for 32-bit processors with a FPU. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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#
57933f8f |
|
30-Nov-2006 |
Scott Wood <scottwood@freescale.com> |
[POWERPC] Add the e300c3 core to the CPU table. This core is used in Freescale's 831x chips. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
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#
fecb352f |
|
21-Nov-2006 |
Mike Wolf <mjw@us.ibm.com> |
[POWERPC] powerpc: Make 970MP detectable by oprofile Change the oprofile_cpu_type in cputables.c to be ppc64/970MP. Oprofile needs to distinquish the MP from other 970 processors so it can add some new counters specific to the 970MP. Signed-off-by: Mike Wolf <mjw@us.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
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#
974a76f5 |
|
10-Nov-2006 |
Paul Mackerras <paulus@samba.org> |
[POWERPC] Distinguish POWER6 partition modes and tell userspace This adds code to look at the properties firmware puts in the device tree to determine what compatibility mode the partition is in on POWER6 machines, and set the ELF aux vector AT_HWCAP and AT_PLATFORM entries appropriately. Specifically, we look at the cpu-version property in the cpu node(s). If that contains a "logical" PVR value (of the form 0x0f00000x), we call identify_cpu again with this PVR value. A value of 0x0f000001 indicates the partition is in POWER5+ compatibility mode, and a value of 0x0f000002 indicates "POWER6 architected" mode, with various extensions disabled. We also look for various other properties: ibm,dfp, ibm,purr and ibm,spurr. Signed-off-by: Paul Mackerras <paulus@samba.org>
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#
18f2190d |
|
20-Nov-2006 |
Maynard Johnson <maynardj@us.ibm.com> |
[POWERPC] cell: Add oprofile support Add PPU event-based and cycle-based profiling support to Oprofile for Cell. Oprofile is expected to collect data on all CPUs simultaneously. However, there is one set of performance counters per node. There are two hardware threads or virtual CPUs on each node. Hence, OProfile must multiplex in time the performance counter collection on the two virtual CPUs. The multiplexing of the performance counters is done by a virtual counter routine. Initially, the counters are configured to collect data on the even CPUs in the system, one CPU per node. In order to capture the PC for the virtual CPU when the performance counter interrupt occurs (the specified number of events between samples has occurred), the even processors are configured to handle the performance counter interrupts for their node. The virtual counter routine is called via a kernel timer after the virtual sample time. The routine stops the counters, saves the current counts, loads the last counts for the other virtual CPU on the node, sets interrupts to be handled by the other virtual CPU and restarts the counters, the virtual timer routine is scheduled to run again. The virtual sample time is kept relatively small to make sure sampling occurs on both CPUs on the node with a relatively small granularity. Whenever the counters overflow, the performance counter interrupt is called to collect the PC for the CPU where data is being collected. The oprofile driver relies on a firmware RTAS call to setup the debug bus to route the desired signals to the performance counter hardware to be counted. The RTAS call must set the routing registers appropriately in each of the islands to pass the signals down the debug bus as well as routing the signals from a particular island onto the bus. There is a second firmware RTAS call to reset the debug bus to the non pass thru state when the counters are not in use. Signed-off-by: Carl Love <carll@us.ibm.com> Signed-off-by: Maynard Johnson <mpjohn@us.ibm.com> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
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#
0909c8c2 |
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19-Oct-2006 |
Benjamin Herrenschmidt <benh@kernel.crashing.org> |
[POWERPC] Support feature fixups in vdso's This patch reworks the feature fixup mecanism so vdso's can be fixed up. The main issue was that the construct: .long label (or .llong on 64 bits) will not work in the case of a shared library like the vdso. It will generate an empty placeholder in the fixup table along with a reloc, which is not something we can deal with in the vdso. The idea here (thanks Alan Modra !) is to instead use something like: 1: .long label - 1b That is, the feature fixup tables no longer contain addresses of bits of code to patch, but offsets of such code from the fixup table entry itself. That is properly resolved by ld when building the .so's. I've modified the fixup mecanism generically to use that method for the rest of the kernel as well. Another trick is that the 32 bits vDSO included in the 64 bits kernel need to have a table in the 64 bits format. However, gas does not support 32 bits code with a statement of the form: .llong label - 1b (Or even just .llong label) That is, it cannot emit the right fixup/relocation for the linker to use to assign a 32 bits address to an .llong field. Thus, in the specific case of the 32 bits vdso built as part of the 64 bits kernel, we are using a modified macro that generates: .long 0xffffffff .llong label - 1b Note that is assumes that the value is negative which is enforced by the .lds (those offsets are always negative as the .text is always before the fixup table and gas doesn't support emiting the reloc the other way around). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
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#
42c4aaad |
|
24-Oct-2006 |
Benjamin Herrenschmidt <benh@kernel.crashing.org> |
[POWERPC] Consolidate feature fixup code There are currently two versions of the functions for applying the feature fixups, one for CPU features and one for firmware features. In addition, they are both in assembly and with separate implementations for 32 and 64 bits. identify_cpu() is also implemented in assembly and separately for 32 and 64 bits. This patch replaces them with a pair of C functions. The call sites are slightly moved on ppc64 as well to be called from C instead of from assembly, though it's a very small change, and thus shouldn't cause any problem. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Paul Mackerras <paulus@samba.org>
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#
362ff7b2 |
|
18-Oct-2006 |
Jake Moilanen <moilanen@austin.ibm.com> |
[POWERPC] Add 970GX cputable entry 970GX cputable entry from Steve Winiecki. Signed-off-by: Jake Moilanen <moilanen@austin.ibm.com> arch/powerpc/kernel/cputable.c | 15 +++++++++++++++ arch/powerpc/oprofile/op_model_power4.c | 2 +- include/asm-powerpc/reg.h | 1 + 3 files changed, 17 insertions(+), 1 deletion(-) Signed-off-by: Paul Mackerras <paulus@samba.org>
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#
5b43d20a |
|
04-Oct-2006 |
Olof Johansson <olof@lixom.net> |
[POWERPC] powerpc: Enable DEEPNAP power savings mode on 970MP Without this patch, on an idle system I get: cpu-power-0:21.638 cpu-power-1:27.102 cpu-power-2:29.343 cpu-power-3:25.784 Total: 103.8W With this patch: cpu-power-0:11.730 cpu-power-1:17.185 cpu-power-2:18.547 cpu-power-3:17.528 Total: 65.0W If I lower HZ to 100, I can get it as low as: cpu-power-0:10.938 cpu-power-1:16.021 cpu-power-2:17.245 cpu-power-3:16.145 Total: 60.2W Another (older) Quad G5 went from 54W to 39W at HZ=250. Coming back out of Deep Nap takes 40-70 cycles longer than coming back from just Nap (which already takes quite a while). I don't think it'll be a performance issue (interrupt latency on an idle system), but in case someone does measurements feel free to report them. Signed-off-by: Olof Johansson <olof@lixom.net> Acked-by: Michael Buesch <mb@bu3sch.de> Signed-off-by: Paul Mackerras <paulus@samba.org>
|
#
99f48610 |
|
12-Oct-2006 |
Anton Blanchard <anton@samba.org> |
[POWERPC] POWER6 has 6 PMCs Change ->num_pmcs to match the number of PMCs in POWER6. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
|
#
6c4a2501 |
|
02-Oct-2006 |
Kim Phillips <kim.phillips@freescale.com> |
[POWERPC] Add initial support for the e300c2 core Add support for the Freescale e300c2 core found in the MPC832x processor line. As far as initial kernel support is concerned, the e300c2 core is identical to the e300c1 found in the mpc834x, except that it's had its floating point unit chopped off. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
|
#
838fdb4d |
|
14-Sep-2006 |
Peter Bergner <bergner@vnet.ibm.com> |
[POWERPC] Add AT_PLATFORM value for Xilinx Virtex-4 FX Jakub noticed the cputable.c entry for Xilinx Virtex-4 FX was missing a .platform value, so the AT_PLATFORM value wouldn't be set correctly. This adds it. Signed-off-by: Peter Bergner <bergner@vnet.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
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#
b3ebd1d8 |
|
06-Sep-2006 |
Olof Johansson <olof@lixom.net> |
[POWERPC] powerpc: PA6T cputable entry, PVR value Introduce PWRficient PA6T cputable entries and feature bits. Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Paul Mackerras <paulus@samba.org>
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#
f39b7a55 |
|
10-Aug-2006 |
Olof Johansson <olof@lixom.net> |
[POWERPC] Cleanup CPU inits Cleanup CPU inits a bit more, Geoff Levand already did some earlier. * Move CPU state save to cpu_setup, since cpu_setup is only ever done on cpu 0 on 64-bit and save is never done more than once. * Rename __restore_cpu_setup to __restore_cpu_ppc970 and add function pointers to the cputable to use instead. Powermac always has 970 so no need to check there. * Rename __970_cpu_preinit to __cpu_preinit_ppc970 and check PVR before calling it instead of in it, it's too early to use cputable. * Rename pSeries_secondary_smp_init to generic_secondary_smp_init since everyone but powermac and iSeries use it. Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Paul Mackerras <paulus@samba.org>
|
#
6ab3d562 |
|
30-Jun-2006 |
Jörn Engel <joern@wohnheim.fh-wedel.de> |
Remove obsolete #include <linux/config.h> Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de> Signed-off-by: Adrian Bunk <bunk@stusta.de>
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#
9ad494f6 |
|
27-Jun-2006 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc: minor cleanups for mpc86xx * Remove duplicated cputable entry for 8641 (matches w/7448) * Removed __init from function prototypes in mpc86xx.h * Moved pci fixups into board specific code * Moved mpc86xx_exclude_device to generic mpc86xx pci code * Fixed sparse warnings in mpc86xx_smp.c * Removed board specific header include from asm-powerpc/mpc86xx.h Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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#
9674ed38 |
|
17-Jun-2006 |
Jon Loeliger <jdl@jdl.com> |
[POWERPC] Add 8641 CPU table entry. Signed-off-by: Wei Zhang <Wei.Zhang@freescale.com> Signed-off-by: Xianghua Xiao <x.xiao@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
|
#
227318bb |
|
10-Jun-2006 |
Anton Blanchard <anton@samba.org> |
[POWERPC] Remove stale 64bit on 32bit kernel code Remove some stale POWER3/POWER4/970 on 32bit kernel support. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
|
#
fab5db97 |
|
07-Jun-2006 |
Paul Mackerras <paulus@samba.org> |
[PATCH] powerpc: Implement support for setting little-endian mode via prctl This adds the PowerPC part of the code to allow processes to change their endian mode via prctl. This also extends the alignment exception handler to be able to fix up alignment exceptions that occur in little-endian mode, both for "PowerPC" little-endian and true little-endian. We always enter signal handlers in big-endian mode -- the support for little-endian mode does not amount to the creation of a little-endian user/kernel ABI. If the signal handler returns, the endian mode is restored to what it was when the signal was delivered. We have two new kernel CPU feature bits, one for PPC little-endian and one for true little-endian. Most of the classic 32-bit processors support PPC little-endian, and this is reflected in the CPU feature table. There are two corresponding feature bits reported to userland in the AT_HWCAP aux vector entry. This is based on an earlier patch by Anton Blanchard. Signed-off-by: Paul Mackerras <paulus@samba.org>
|
#
e78dbc80 |
|
07-Jun-2006 |
Michael Neuling <mikey@neuling.org> |
[PATCH] powerpc: oprofile support for POWER6 POWER6 moves some of the MMCRA bits and also requires some bits to be cleared each PMU interrupt. Signed-off-by: Michael Neuling <mikey@neuling.org> Acked-by: Anton Blanchard <anton@samba.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
|
#
87af41be |
|
04-May-2006 |
Anton Blanchard <anton@samba.org> |
[PATCH] powerpc: add num_pmcs to 970MP cputable entry The 970MP cputable entry needs a num_pmcs entry for oprofile to work. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
|
#
b26f100d |
|
18-May-2006 |
Geoff Levand <geoffrey.levand@am.sony.com> |
[PATCH] powerpc: remove do-nothing cpu setup routines Removed the do-nothing routines __setup_cpu_power3 and __setup_cpu_power4 and replaced them with a null pointer check in the caller. Also removed the Cell processor specific routine __setup_cpu_be which improperly accessed the hypervisor page size configuration at SPR HID6. Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
|
#
03054d51 |
|
28-Apr-2006 |
Anton Blanchard <anton@samba.org> |
[PATCH] powerpc: Add cputable entry for POWER6 Add a cputable entry for the POWER6 processor. The SIHV and SIPR bits in the mmcra have moved in POWER6, so disable support for that until oprofile is fixed. Also tell firmware that we know about POWER6. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
|
#
aa5cb021 |
|
28-Feb-2006 |
Benjamin Herrenschmidt <benh@kernel.crashing.org> |
[PATCH] powerpc: Expose SMT and L1 icache snoop userland features This patch makes userland aware of the icache snoop capability of the POWER5 (and possibly others in the future) and of SMT capabilities. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
|
#
72646c7f |
|
19-Jan-2006 |
Grant C. Likely <grant.likely@secretlab.ca> |
[PATCH] powerpc: Add Virtex-4 FX to cpu table Signed-off-by: Grant C. Likely <grant.likely@secretlab.ca> Signed-off-by: Paul Mackerras <paulus@samba.org>
|
#
7a45fb19 |
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12-Jan-2006 |
Andy Whitcroft <apw@shadowen.org> |
[PATCH] powerpc: oprofile cpu type names clash with other code In 2.6.15-git6 a change was commited in the oprofile support in the powerpc architecture. It introduced the powerpc_oprofile_type which contains the define G4. This causes a name clash with the existing wacom usb tablet driver. CC [M] drivers/usb/input/wacom.o drivers/usb/input/wacom.c:98: error: conflicting types for `G4' include/asm/cputable.h:37: error: previous declaration of `G4' CC [M] drivers/usb/mon/mon_text.o make[3]: *** [drivers/usb/input/wacom.o] Error 1 make[2]: *** [drivers/usb/input] Error 2 The elements of an enum declared in global scope are effectivly global identifiers themselves. As such we need to ensure the names are unique. This patch updates the later oprofile support to use unique names. Signed-off-by: Andy Whitcroft <apw@shadowen.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
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80f15dc7 |
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13-Jan-2006 |
Paul Mackerras <paulus@samba.org> |
powerpc: Provide a suitable AT_PLATFORM value The glibc folks want to use AT_PLATFORM to select between possible alternative versions of shared libraries. This commit makes the kernel supply an AT_PLATFORM string that indicates what class of processor we are running on. Processors with the same set of user-level instructions and roughly the same instruction scheduling characteristics are given the same AT_PLATFORM value; for example, 821, 823 and 860 are all reported as "ppc823", and 7447, 7447A, 7448, 7450, 7451, 7455 are all called "ppc7450". The intention is that the AT_PLATFORM values match the values that gcc accepts for the -mcpu= option. For values which are numeric (e.g. -mcpu=750), "ppc" has been prepended. This also adds a PPC_FEATURE_BOOKE bit to the AT_HWCAP value and sets it for the 440 family and the Freescale 85xx family. Signed-off-by: Paul Mackerras <paulus@samba.org>
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834608f7 |
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08-Jan-2006 |
Anton Blanchard <anton@samba.org> |
[PATCH] ppc64: POWER5+ oprofile support POWER5+ adds new PMU groups and as such needs to be treated differently by oprofile userspace. Change it to report itself as power5+. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
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32a33994 |
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08-Jan-2006 |
Anton Blanchard <anton@samba.org> |
[PATCH] ppc64: Fix oprofile when compiled as a module My recent changes to oprofile broke it when built as a module. Fix it by using an enum instead of a function pointer. This way we still retain the oprofile configuration in the cputable. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
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c902be71 |
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04-Jan-2006 |
Arnd Bergmann <arnd@arndb.de> |
[PATCH] cell: enable pause(0) in cpu_idle This patch enables support for pause(0) power management state for the Cell Broadband Processor, which is import for power efficient operation. The pervasive infrastructure will in the future enable us to introduce more functionality specific to the Cell's pervasive unit. From: Maximino Aguilar <maguilar@us.ibm.com> Signed-off-by: Arnd Bergmann <arndb@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
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555d97ac |
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15-Dec-2005 |
Andy Fleming <afleming@freescale.com> |
[PATCH] powerpc: G4+ oprofile support This patch adds oprofile support for the 7450 and all its multitudinous derivatives. * Added 7450 (and derivatives) support for oprofile * Changed e500 cputable to have oprofile model and cpu_type fields * Added support for classic 32-bit performance monitor interrupt * Cleaned up common powerpc oprofile code to be as common as possible * Cleaned up oprofile_impl.h to reflect 32 bit classic code * Added 32-bit MMCRx bitfield definitions and SPR numbers Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
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a7ddc5e8 |
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09-Nov-2005 |
Paul Mackerras <paulus@samba.org> |
powerpc: Add user CPU features for POWER4, POWER5, POWER5+ and Cell. This is at the request of the glibc folks, who want to use these bits to select libraries optimized for the microarchitecture and new instructions in these processors. Signed-off-by: Paul Mackerras <paulus@samba.org>
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b0f7b8bc |
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07-Nov-2005 |
Roland Dreier <rolandd@cisco.com> |
[PATCH] ppc32: Add 440SPe support Add support for the AMCC PowerPC 440SPe SoC, including PCI Express in root port mode. Signed-off-by: Roland Dreier <rolandd@cisco.com> Cc: Matt Porter <mporter@kernel.crashing.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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3c726f8d |
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06-Nov-2005 |
Benjamin Herrenschmidt <benh@kernel.crashing.org> |
[PATCH] ppc64: support 64k pages Adds a new CONFIG_PPC_64K_PAGES which, when enabled, changes the kernel base page size to 64K. The resulting kernel still boots on any hardware. On current machines with 4K pages support only, the kernel will maintain 16 "subpages" for each 64K page transparently. Note that while real 64K capable HW has been tested, the current patch will not enable it yet as such hardware is not released yet, and I'm still verifying with the firmware architects the proper to get the information from the newer hypervisors. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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c1c3a554 |
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29-Oct-2005 |
Paul Mackerras <paulus@samba.org> |
powerpc: 32-bit needs cur_cpu_spec exported too Somehow we ended up with an #ifdef CONFIG_PPC64 around the export of cur_cpu_spec, but raid6 as a module needs it on ppc32 as well as ppc64. Signed-off-by: Paul Mackerras <paulus@samba.org>
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4920960f |
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11-Oct-2005 |
Stephen Rothwell <sfr@canb.auug.org.au> |
powerpc: consolidate cputable.c Also simplify arch/ppc64/kernel/Makefile Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
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