#
2874c5fd |
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27-May-2019 |
Thomas Gleixner <tglx@linutronix.de> |
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152 Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
57c8a661 |
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30-Oct-2018 |
Mike Rapoport <rppt@linux.vnet.ibm.com> |
mm: remove include/linux/bootmem.h Move remaining definitions and declarations from include/linux/bootmem.h into include/linux/memblock.h and remove the redundant header. The includes were replaced with the semantic patch below and then semi-automated removal of duplicated '#include <linux/memblock.h> @@ @@ - #include <linux/bootmem.h> + #include <linux/memblock.h> [sfr@canb.auug.org.au: dma-direct: fix up for the removal of linux/bootmem.h] Link: http://lkml.kernel.org/r/20181002185342.133d1680@canb.auug.org.au [sfr@canb.auug.org.au: powerpc: fix up for removal of linux/bootmem.h] Link: http://lkml.kernel.org/r/20181005161406.73ef8727@canb.auug.org.au [sfr@canb.auug.org.au: x86/kaslr, ACPI/NUMA: fix for linux/bootmem.h removal] Link: http://lkml.kernel.org/r/20181008190341.5e396491@canb.auug.org.au Link: http://lkml.kernel.org/r/1536927045-23536-30-git-send-email-rppt@linux.vnet.ibm.com Signed-off-by: Mike Rapoport <rppt@linux.vnet.ibm.com> Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Acked-by: Michal Hocko <mhocko@suse.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Chris Zankel <chris@zankel.net> Cc: "David S. Miller" <davem@davemloft.net> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Greentime Hu <green.hu@gmail.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Guan Xuetao <gxt@pku.edu.cn> Cc: Ingo Molnar <mingo@redhat.com> Cc: "James E.J. Bottomley" <jejb@parisc-linux.org> Cc: Jonas Bonn <jonas@southpole.se> Cc: Jonathan Corbet <corbet@lwn.net> Cc: Ley Foon Tan <lftan@altera.com> Cc: Mark Salter <msalter@redhat.com> Cc: Martin Schwidefsky <schwidefsky@de.ibm.com> Cc: Matt Turner <mattst88@gmail.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Michal Simek <monstr@monstr.eu> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Paul Burton <paul.burton@mips.com> Cc: Richard Kuo <rkuo@codeaurora.org> Cc: Richard Weinberger <richard@nod.at> Cc: Rich Felker <dalias@libc.org> Cc: Russell King <linux@armlinux.org.uk> Cc: Serge Semin <fancer.lancer@gmail.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Tony Luck <tony.luck@intel.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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#
38c0a74f |
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12-Jul-2018 |
Paul Burton <paulburton@kernel.org> |
MIPS: Fix off-by-one in pci_resource_to_user() The MIPS implementation of pci_resource_to_user() introduced in v3.12 by commit 4c2924b725fb ("MIPS: PCI: Use pci_resource_to_user to map pci memory space properly") incorrectly sets *end to the address of the byte after the resource, rather than the last byte of the resource. This results in userland seeing resources as a byte larger than they actually are, for example a 32 byte BAR will be reported by a tool such as lspci as being 33 bytes in size: Region 2: I/O ports at 1000 [disabled] [size=33] Correct this by subtracting one from the calculated end address, reporting the correct address to userland. Signed-off-by: Paul Burton <paul.burton@mips.com> Reported-by: Rui Wang <rui.wang@windriver.com> Fixes: 4c2924b725fb ("MIPS: PCI: Use pci_resource_to_user to map pci memory space properly") Cc: James Hogan <jhogan@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Wolfgang Grandegger <wg@grandegger.com> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org # v3.12+ Patchwork: https://patchwork.linux-mips.org/patch/19829/
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#
73530266 |
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26-Jul-2017 |
Matt Redfearn <matt.redfearn@mips.com> |
MIPS: PCI: Fix smp_processor_id() in preemptible Commit 1c3c5eab1715 ("sched/core: Enable might_sleep() and smp_processor_id() checks early") enables checks for might_sleep() and smp_processor_id() being used in preemptible code earlier in the boot than before. This results in a new BUG from pcibios_set_cache_line_size(). BUG: using smp_processor_id() in preemptible [00000000] code: swapper/0/1 caller is pcibios_set_cache_line_size+0x10/0x70 CPU: 1 PID: 1 Comm: swapper/0 Not tainted 4.13.0-rc1-00007-g3ce3e4ba4275 #615 Stack: 0000000000000000 ffffffff81189694 0000000000000000 ffffffff81822318 000000000000004e 0000000000000001 800000000e20bd08 20c49ba5e3540000 0000000000000000 0000000000000000 ffffffff818d0000 0000000000000000 0000000000000000 ffffffff81189328 ffffffff818ce692 0000000000000000 0000000000000000 ffffffff81189bc8 ffffffff818d0000 0000000000000000 ffffffff81828907 ffffffff81769970 800000020ec78d80 ffffffff818c7b48 0000000000000001 0000000000000001 ffffffff818652b0 ffffffff81896268 ffffffff818c0000 800000020ec7fb40 800000020ec7fc58 ffffffff81684cac 0000000000000000 ffffffff8118ab50 0000000000000030 ffffffff81769970 0000000000000001 ffffffff81122a58 0000000000000000 0000000000000000 ... Call Trace: [<ffffffff81122a58>] show_stack+0x90/0xb0 [<ffffffff81684cac>] dump_stack+0xac/0xf0 [<ffffffff813f7050>] check_preemption_disabled+0x120/0x128 [<ffffffff818855e8>] pcibios_set_cache_line_size+0x10/0x70 [<ffffffff81100578>] do_one_initcall+0x48/0x140 [<ffffffff81865dc4>] kernel_init_freeable+0x194/0x24c [<ffffffff8169c534>] kernel_init+0x14/0x118 [<ffffffff8111ca84>] ret_from_kernel_thread+0x14/0x1c Fix this by using the cpu_*cache_line_size() macros instead. These macros are the "proper" way to determine the CPU cache sizes. This makes use of the newly added cpu_tcache_line_size. Fixes: 1c3c5eab1715 ("sched/core: Enable might_sleep() and smp_processor_id() checks early") Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Suggested-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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#
35368f80 |
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12-Apr-2017 |
David Woodhouse <dwmw@amazon.co.uk> |
MIPS: PCI: Use generic pci_mmap_resource_range() Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
f66e2258 |
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12-Apr-2017 |
David Woodhouse <dwmw@amazon.co.uk> |
PCI: Add BAR index argument to pci_mmap_page_range() In all cases we know which BAR it is. Passing it in means that arch code (or generic code; watch this space) won't have to go looking for it again. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
f8091a88 |
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05-Oct-2016 |
Paul Burton <paulburton@kernel.org> |
MIPS: PCI: Split pci.c into pci.c & pci-legacy.c Split out the parts of pci.c that are used by existing systems with MIPS-style PCI drivers but that will not be used by systems with more generic PCI drivers such as pcie-xilinx. This is done in preparation for allowing configurations where the code moved to pci-legacy.c is not built. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Paul Burton <paul.burton@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/14344/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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#
ab96b031 |
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05-Oct-2016 |
Paul Burton <paulburton@kernel.org> |
MIPS: PCI: Inline pcibios_assign_all_busses The MIPS implementation of pcibios_assign_all_busses trivially returns 1. Implement it as a static function in asm/pci.h such that the compiler can inline it & optimise out never-taken paths. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14343/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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#
f474ba9d |
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05-Oct-2016 |
Paul Burton <paulburton@kernel.org> |
MIPS: PCI: Make pcibios_set_cache_line_size an initcall In preparation for allowing configurations in which pcibios_init is not included, make pcibios_set_cache_line_size an initcall. arch_initcall is used such that it runs before the pcibios_init subsys_initcall for platforms that continue to use it. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14342/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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#
88555b48 |
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05-Oct-2016 |
Paul Burton <paulburton@kernel.org> |
MIPS: PCI: Support for CONFIG_PCI_DOMAINS_GENERIC Introduce support for CONFIG_PCI_DOMAINS_GENERIC, allowing for platforms to make use of generic PCI domains instead of the MIPS-specific implementation. The set_pci_need_domain_info function is introduced to abstract away the removed need_domain_info field in struct pci_controller, and pcibios_scanbus is adjusted to use the pci_domain_nr accessor instead of directly accessing the index field. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14341/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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#
23dac14d |
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05-Oct-2016 |
Paul Burton <paulburton@kernel.org> |
MIPS: PCI: Use struct list_head lists Rather than open-coding a linked list implementation, make use of the one in linux/list.h. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14340/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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#
04613617 |
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23-Jun-2016 |
Bjorn Helgaas <bhelgaas@google.com> |
MIPS/PCI: Claim bus resources on PCI_PROBE_ONLY set-ups We claim PCI BAR and bridge window resources in pci_bus_assign_resources(), but when PCI_PROBE_ONLY is set, we treat those resources as immutable and don't call pci_bus_assign_resources(), so the resources aren't put in the resource tree. When the resources aren't in the tree, they don't show up in /proc/iomem, we can't detect conflicts, and we need special cases elsewhere for PCI_PROBE_ONLY or resources without a parent pointer. Claim all PCI BAR and window resources in the PCI_PROBE_ONLY case. If a PCI_PROBE_ONLY platform assigns conflicting resources, Linux can't fix the conflicts. Previously we didn't notice the conflicts, but now we will, which may expose new failures. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
8221a013 |
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17-Jun-2016 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Unify pci_resource_to_user() declarations Replace the pci_resource_to_user() declarations in each arch that defines HAVE_ARCH_PCI_RESOURCE_TO_USER with a single one in linux/pci.h. Change the MIPS static inline implementation to a non-inline version so the static inline doesn't conflict with the new non-static linux/pci.h declaration. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
e8b5325c |
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29-Aug-2014 |
Sergey Ryazanov <ryazanov.s.a@gmail.com> |
MIPS: make PCI_DMA_BUS_IS_PHYS=1 constant No one of supported MIPS machines has an IOMMU unit, so we can safely define PCI_DMA_BUS_IS_PHYS = 1. Also remove iommu flag from the pci controller structure, since it is useless. Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com> Cc: Linux MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/7604/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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#
237865f1 |
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15-Sep-2015 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Revert "PCI: Call pci_read_bridge_bases() from core instead of arch code" Revert dff22d2054b5 ("PCI: Call pci_read_bridge_bases() from core instead of arch code"). Reading PCI bridge windows is not arch-specific in itself, but there is PCI core code that doesn't work correctly if we read them too early. For example, Hannes found this case on an ARM Freescale i.mx6 board: pci_bus 0000:00: root bus resource [mem 0x01000000-0x01efffff] pci 0000:00:00.0: PCI bridge to [bus 01-ff] pci 0000:00:00.0: BAR 8: no space for [mem size 0x01000000] (mem window) pci 0000:01:00.0: BAR 2: failed to assign [mem size 0x00200000] pci 0000:01:00.0: BAR 1: failed to assign [mem size 0x00004000] pci 0000:01:00.0: BAR 0: failed to assign [mem size 0x00000100] The 00:00.0 mem window needs to be at least 3MB: the 01:00.0 device needs 0x204100 of space, and mem windows are megabyte-aligned. Bus sizing can increase a bridge window size, but never *decrease* it (see d65245c3297a ("PCI: don't shrink bridge resources")). Prior to dff22d2054b5, ARM didn't read bridge windows at all, so the "original size" was zero, and we assigned a 3MB window. After dff22d2054b5, we read the bridge windows before sizing the bus. The firmware programmed a 16MB window (size 0x01000000) in 00:00.0, and since we never decrease the size, we kept 16MB even though we only needed 3MB. But 16MB doesn't fit in the host bridge aperture, so we failed to assign space for the window and the downstream devices. I think this is a defect in the PCI core: we shouldn't rely on the firmware to assign sensible windows. Ray reported a similar problem, also on ARM, with Broadcom iProc. Issues like this are too hard to fix right now, so revert dff22d2054b5. Reported-by: Hannes <oe5hpm@gmail.com> Reported-by: Ray Jui <rjui@broadcom.com> Link: http://lkml.kernel.org/r/CAAa04yFQEUJm7Jj1qMT57-LG7ZGtnhNDBe=PpSRa70Mj+XhW-A@mail.gmail.com Link: http://lkml.kernel.org/r/55F75BB8.4070405@broadcom.com Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Yinghai Lu <yinghai@kernel.org> Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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#
dff22d20 |
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09-Jul-2015 |
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> |
PCI: Call pci_read_bridge_bases() from core instead of arch code When we scan a PCI bus, we read PCI-PCI bridge window registers with pci_read_bridge_bases() so we can validate the resource hierarchy. Most architectures call pci_read_bridge_bases() from pcibios_fixup_bus(), but PCI-PCI bridges are not arch-specific, so this doesn't need to be in arch-specific code. Call pci_read_bridge_bases() directly from the PCI core instead of from arch code. For alpha and mips, we now call pci_read_bridge_bases() always; previously we only called it if PCI_PROBE_ONLY was set. [bhelgaas: changelog] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Ralf Baechle <ralf@linux-mips.org> CC: James E.J. Bottomley <jejb@parisc-linux.org> CC: Michael Ellerman <mpe@ellerman.id.au> CC: Bjorn Helgaas <bhelgaas@google.com> CC: Richard Henderson <rth@twiddle.net> CC: Benjamin Herrenschmidt <benh@kernel.crashing.org> CC: David Howells <dhowells@redhat.com> CC: Russell King <linux@arm.linux.org.uk> CC: Tony Luck <tony.luck@intel.com> CC: David S. Miller <davem@davemloft.net> CC: Ingo Molnar <mingo@redhat.com> CC: Guenter Roeck <linux@roeck-us.net> CC: Michal Simek <monstr@monstr.eu> CC: Chris Zankel <chris@zankel.net>
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#
a2e50f53 |
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19-Jan-2015 |
Joshua Kinard <kumba@gentoo.org> |
MIPS: PCI: Add a hook for IORESOURCE_BUS in pci_controller/bridge_controller On SGI Origin 2k/Onyx2 and SGI Octane systems, there can exist multiple PCI buses attached to the Xtalk bus. The current code will stop counting PCI buses after it finds the first one. If one installs the optional PCI cardcage ("shoebox") into these systems, because of the order of the Xtalk widgets, the current PCI code will find the cardcage first, and fail to detect the BaseIO PCI devices, which are on a higher Xtalk widget ID. This patch adds the hooks needed for resolving this issue in the IP27 PCI code (in a later patch). Verified on both an SGI Onyx2 and an SGI Octane. Signed-off-by: Joshua Kinard <kumba@gentoo.org> Cc: Linux MIPS List <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/9074/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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#
9e808eb6 |
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12-Mar-2015 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Cleanup control flow Return errors immediately so the straightline path is the normal, no-error path. No functional change. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
b97ea289 |
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15-Mar-2015 |
Yijing Wang <wangyijing@huawei.com> |
PCI: Assign resources before drivers claim devices (pci_scan_root_bus()) Previously, pci_scan_root_bus() created a root PCI bus, enumerated the devices on it, and called pci_bus_add_devices(), which made the devices available for drivers to claim them. Most callers assigned resources to devices after pci_scan_root_bus() returns, which may be after drivers have claimed the devices. This is incorrect; the PCI core should not change device resources while a driver is managing the device. Remove pci_bus_add_devices() from pci_scan_root_bus() and do it after any resource assignment in the callers. Note that ARM's pci_common_init_dev() already called pci_bus_add_devices() after pci_scan_root_bus(), so we only need to remove the first call: pci_common_init_dev pcibios_init_hw pci_scan_root_bus pci_bus_add_devices # first call pci_bus_assign_resources pci_bus_add_devices # second call [bhelgaas: changelog, drop "root_bus" var in alpha common_init_pci(), return failure earlier in mn10300, add "return" in x86 pcibios_scan_root(), return early if xtensa platform_pcibios_fixup() fails] Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Richard Henderson <rth@twiddle.net> CC: Ivan Kokshaysky <ink@jurassic.park.msu.ru> CC: Matt Turner <mattst88@gmail.com> CC: David Howells <dhowells@redhat.com> CC: Tony Luck <tony.luck@intel.com> CC: Michal Simek <monstr@monstr.eu> CC: Ralf Baechle <ralf@linux-mips.org> CC: Koichi Yasutake <yasutake.koichi@jp.panasonic.com> CC: Sebastian Ott <sebott@linux.vnet.ibm.com> CC: "David S. Miller" <davem@davemloft.net> CC: Chris Metcalf <cmetcalf@ezchip.com> CC: Chris Zankel <chris@zankel.net> CC: Max Filippov <jcmvbkbc@gmail.com> CC: Thomas Gleixner <tglx@linutronix.de>
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#
cffe00c0 |
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25-Jul-2013 |
Andrew Murray <amurray@thegoodpenguin.co.uk> |
MIPS: of/pci: Use of_pci_range_parser This patch converts the pci_load_of_ranges function to use the new common of_pci_range_parser. Signed-off-by: Andrew Murray <amurray@embedded-bits.co.uk> Signed-off-by: Andrew Murray <Andrew.Murray@arm.com> Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Reviewed-by: Rob Herring <rob.herring@calxeda.com> Reviewed-by: Grant Likely <grant.likely@secretlab.ca> Tested-by: Linus Walleij <linus.walleij@linaro.org> Cc: linux-mips@linux-mips.org Cc: jason@lakedaemon.net Patchwork: https://patchwork.linux-mips.org/patch/5625/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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#
928bea96 |
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22-Jul-2013 |
Yinghai Lu <yinghai@kernel.org> |
PCI: Delay enabling bridges until they're needed We currently enable PCI bridges after scanning a bus and assigning resources. This is often done in arch code. This patch changes this so we don't enable a bridge until necessary, i.e., until we enable a PCI device behind the bridge. We do this in the generic pci_enable_device() path, so this also removes the arch-specific code to enable bridges. [bhelgaas: changelog] Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
9a97cd43 |
|
04-Apr-2013 |
Gabor Juhos <juhosg@openwrt.org> |
MIPS/PCI: Implement pcibios_get_phb_of_node The of_node field of the device assigned to a PCI bus is used during scanning of the PCI bus. However on MIPS, the of_node field is assigned only after the bus has been scanned. Implement the architecture specific version of 'pcibios_get_phb_of_node'. Which ensures that the PCI driver core will initialize the of_node field before starting the scan. Also remove the local assignment of bus->dev.of_node, it is not needed after the patch. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
22283178 |
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02-Feb-2013 |
Gabor Juhos <juhosg@openwrt.org> |
MIPS: avoid possible resource conflict in register_pci_controller The IO and memory resources of a PCI controller might already have a parent resource set when they are passed to 'register_pci_controller'. If the parent resource is set, the request_resource call will fail due to resource conflict and the current code will not be able to register the PCI controller. Use the parent resource if it is available in the request_resource call to avoid the isssue. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4910/ Signed-off-by: John Crispin <blogic@openwrt.org>
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#
70342287 |
|
21-Jan-2013 |
Ralf Baechle <ralf@linux-mips.org> |
MIPS: Whitespace cleanup. Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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#
28eb0e46 |
|
21-Dec-2012 |
Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
MIPS: drivers: remove __dev* attributes. CONFIG_HOTPLUG is going away as an option. As a result, the __dev* markings need to be removed. This change removes the use of __devinit, __devexit_p, __devinitdata, and __devexit from these drivers. Based on patches originally written by Bill Pemberton, but redone by me in order to handle some of the coding style issues better, by hand. Cc: Bill Pemberton <wfp5p@virginia.edu> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
0a6f19db |
|
21-Nov-2012 |
Bill Pemberton <wfp5p@virginia.edu> |
mips/PCI: Remove CONFIG_HOTPLUG ifdefs Remove conditional code based on CONFIG_HOTPLUG being false. It's always on now in preparation of it going away as an option. Signed-off-by: Bill Pemberton <wfp5p@virginia.edu> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Grant Likely <grant.likely@secretlab.ca> Cc: Rob Herring <rob.herring@calxeda.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
8885b7b6 |
|
17-Sep-2012 |
Thierry Reding <thierry.reding@avionic-design.de> |
PCI: Provide a default pcibios_update_irq() Most architectures implement this in exactly the same way. Instead of having each architecture duplicate this function, provide a single implementation in the core and make it a weak symbol so that it can be overridden on architectures where it is required. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
3ddbebf8 |
|
17-Sep-2012 |
Thierry Reding <thierry.reding@avionic-design.de> |
PCI: Discard __init annotations for pci_fixup_irqs() and related functions Remove the __init annotations in order to keep pci_fixup_irqs() around after init (e.g. for hotplug). This requires the same change for the implementation of pcibios_update_irq() on all architectures. While at it, all __devinit annotations are removed as well, since they will be useless now that HOTPLUG is always on. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
938ca516 |
|
25-Jun-2012 |
Myron Stowe <myron.stowe@redhat.com> |
MIPS/PCI: adjust section annotations for pcibios_setup() Make pcibios_setup() consistently use the "__init" section annotation. Signed-off-by: Myron Stowe <myron.stowe@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
b918c62e |
|
17-May-2012 |
Yinghai Lu <yinghai@kernel.org> |
PCI: replace struct pci_bus secondary/subordinate with busn_res Replace the struct pci_bus secondary/subordinate members with the struct resource busn_res. Later we'll build a resource tree of these bus numbers. [bhelgaas: changelog] Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
a48cf37a |
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04-May-2012 |
John Crispin <blogic@openwrt.org> |
MIPS: pci: parse memory ranges from devicetree Implement pci_load_of_ranges on MIPS. Due to lack of test hardware only 32bit bus width is supported. This function is based on pci_process_bridge_OF_ranges from powerpc. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3729/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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#
96a6b9ad |
|
23-Feb-2012 |
Bjorn Helgaas <bhelgaas@google.com> |
mips/PCI: get rid of device resource fixups Tell the PCI core about host bridge address translation so it can take care of bus-to-resource conversion for us. Here's the wrinkle on Cobalt: we can't generate normal I/O port addresses on PCI because the GT-64111 doesn't do any address translation, so we have this: CPU I/O port addresses [io 0x0000-0xffffff] PCI bus I/O port addresses [io 0x10000000-0x10ffffff] Legacy-mode IDE controllers start out with the legacy bus addresses, e.g., 0x1f0, assigned by pci_setup_device(). These are outside the range of addresses GT-64111 can generate on PCI, but pcibios_fixup_device_resources() converted them to CPU addresses anyway by adding io_offset. Therefore, we had to pre-adjust them in cobalt_legacy_ide_fixup(). With io_offset = 0xf0000000, we had this: res->start = 0x1f0 initialized in pci_setup_device() res->start = 0x100001f0 -= io_offset in cobalt_legacy_ide_fixup() res->start = 0x1f0 += io_offset in pcibios_fixup_device_resources() The difference after this patch is that the generic pci_bus_to_resource() only adds the offset if the bus address is inside a host bridge window. Since 0x1f0 is not a valid bus address and is not inside any windows, it is unaffected, so we now have this: region->start = 0x1f0 initialized in pci_setup_device() res->start = 0x1f0 no offset by pci_bus_to_resource() That means we can remove both pcibios_fixup_device_resources() and cobalt_legacy_ide_fixup(). I would *rather* set the host bridge offset to zero (which corresponds to what the GT-64111 actually does), and have both CPU and PCI addresses of [io 0x10000000-0x10ffffff]. However, that would require changes to generic code that assumes legacy I/O addresses, such as pic1_io_resource ([io 0x0020-0x00021]), and we'd have to keep a Cobalt IDE fixup. Of course, none of this changes the fact that references to I/O port 0x1f0 actually go to port 0x100001f0, not 0x1f0, on the Cobalt PCI bus. Fortunately the VT82C586 IDE controller only decodes the low 24 address bits, so it does work. CC: Ralf Baechle <ralf@linux-mips.org> CC: Yoichi Yuasa <yuasa@linux-mips.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
14be538c |
|
23-Feb-2012 |
Bjorn Helgaas <bhelgaas@google.com> |
mips/PCI: removed unused pci_probe configurability We never assign anything other than PCI_ASSIGN_ALL_BUSSES to pci_probe, so just remove the indirection. If configurability is required in the future, please use the pci_flags/PCI_REASSIGN_ALL_BUS functionality as is done for powerpc. CC: Ralf Baechle <ralf@linux-mips.org> CC: linux-mips@linux-mips.org Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
29090606 |
|
23-Feb-2012 |
Bjorn Helgaas <bhelgaas@google.com> |
mips/PCI: replace pci_probe_only with pci_flags Some architectures (alpha, mips, powerpc) have an arch-specific "pci_probe_only" flag. Others use PCI_PROBE_ONLY in pci_flags for the same purpose. This moves mips to the pci_flags approach so generic code can use the same test across all architectures. CC: Ralf Baechle <ralf@linux-mips.org> CC: linux-mips@linux-mips.org Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
f79eaeb1 |
|
16-Dec-2011 |
Bjorn Helgaas <bhelgaas@google.com> |
MIPS: PCI: use list_for_each_entry() for bus->devices traversal Replace open-coded list traversal with list_for_each_entry(). Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: linux-pci@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3200/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
#
c539ef7d |
|
11-Jan-2012 |
Ralf Baechle <ralf@linux-mips.org> |
MIPS: Set default pci cache line size. On MIPS the generic PCI code has always defaulted to L1_CACHE_BYTES because the architecutre PCI code did not provide a better default. In particular on systems with S-caches or T-caches this was suboptimal. Provide a better default by setting pci_dfl_cache_line_size based on the size of the line size of the lowest level of the cache hierarchy. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/2982/
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#
7c090e5b |
|
28-Oct-2011 |
Bjorn Helgaas <bhelgaas@google.com> |
mips/PCI: convert to pci_scan_root_bus() for correct root bus resources Convert from pci_scan_bus() to pci_scan_root_bus() and remove root bus resource fixups. This fixes the problem of "early" and "header" quirks seeing incorrect root bus resources. Based on original patch by Deng-Cheng Zhu. Reference: https://lkml.org/lkml/2011/8/26/89 CC: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Deng-Cheng Zhu <dczhu@mips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
96633fa2 |
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28-Oct-2011 |
Myron Stowe <mstowe@redhat.com> |
PCI: MIPS: use generic pcibios_set_master() This patch removes MIPS' architecture-specific 'pcibios_set_master()' routine and lets the default PCI core based implementation handle PCI device 'latency timer' setup. No functional change. Acked-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Myron Stowe <myron.stowe@redhat.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
96c55900 |
|
28-Oct-2011 |
Myron Stowe <mstowe@redhat.com> |
PCI: Pull PCI 'latency timer' setup up into the core The 'latency timer' of PCI devices, both Type 0 and Type 1, is setup in architecture-specific code [see: 'pcibios_set_master()']. There are two approaches being taken by all the architectures - check if the 'latency timer' is currently set between 16 and 255 and if not bring it within bounds, or, do nothing (and then there is the gratuitously different PA-RISC implementation). There is nothing architecture-specific about PCI's 'latency timer' so this patch pulls its setup functionality up into the PCI core by creating a generic 'pcibios_set_master()' function using the '__weak' attribute which can be used by all architectures as a default which, if necessary, can then be over-ridden by architecture-specific code. No functional change. Signed-off-by: Myron Stowe <myron.stowe@redhat.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
cae39d13 |
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28-Jul-2011 |
Paul Gortmaker <paul.gortmaker@windriver.com> |
mips: add export.h to files using EXPORT_SYMBOL/THIS_MODULE Or else we get lots of variations on this: arch/mips/pci/pci.c:330: warning: type defaults to 'int' in declaration of 'EXPORT_SYMBOL' scattered throughout the build. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
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#
25985edc |
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30-Mar-2011 |
Lucas De Marchi <lucas.demarchi@profusion.mobi> |
Fix common misspellings Fixes generated by 'codespell' and manually reviewed. Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
|
#
81904710 |
|
24-Feb-2010 |
Bjorn Helgaas <bjorn.helgaas@hp.com> |
MIPS: Cobalt: convert legacy port addresses to GT-64111 bus addresses The GT-64111 PCI host bridge has no address translation mechanism, so it can't generate legacy port accesses. This quirk fixes legacy device port resources to contain the bus addresses actually generated by the GT-64111. I think this is the approach Ben Herrenschmidt suggested long ago: http://marc.info/?l=linux-kernel&m=119733290624544&w=2 This allows us to remove the IORESOURCE_PCI_FIXED hack from pcibios_fixup_device_resources(), which converts bus addresses to CPU addresses. IORESOURCE_PCI_FIXED denotes resources that can't be moved; it has nothing to do with converting bus to CPU addresses. Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Cc: Yoichi Yuasa <yuasa@linux-mips.org> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: linux-mips@linux-mips.org Tested-by: Yoichi Yuasa <yuasa@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/998/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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#
3b7a17fc |
|
01-Jan-2010 |
Dominik Brodowski <linux@dominikbrodowski.net> |
resource/PCI: mark struct resource as const Now that we return the new resource start position, there is no need to update "struct resource" inside the align function. Therefore, mark the struct resource as const. Cc: Bjorn Helgaas <bjorn.helgaas@hp.com> Cc: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Dominik Brodowski <linux@dominikbrodowski.net> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
b26b2d49 |
|
01-Jan-2010 |
Dominik Brodowski <linux@dominikbrodowski.net> |
resource/PCI: align functions now return start of resource As suggested by Linus, align functions should return the start of a resource, not void. An update of "res->start" is no longer necessary. Cc: Bjorn Helgaas <bjorn.helgaas@hp.com> Cc: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Dominik Brodowski <linux@dominikbrodowski.net> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
982f6ffe |
|
16-Sep-2009 |
Ralf Baechle <ralf@linux-mips.org> |
MIPS: Remove useless zero initializations. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
#
67eed580 |
|
16-Dec-2008 |
Bjorn Helgaas <bjorn.helgaas@hp.com> |
PCI: mips: use generic INTx swizzle from PCI core Use the generic pci_common_swizzle() instead of arch-specific code. Note that pci_common_swizzle() loops based on dev->bus->self, not dev->bus->parent as the mips common_swizzle() did. I think they are equivalent for this purpose. Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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#
30d546da |
|
09-Dec-2008 |
Bjorn Helgaas <bjorn.helgaas@hp.com> |
PCI: mips: use generic pci_swizzle_interrupt_pin() Use the generic pci_swizzle_interrupt_pin() instead of arch-specific code. Acked-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
|
#
98873f53 |
|
09-Dec-2008 |
Ralf Baechle <ralf@linux-mips.org> |
MIPS: Better than nothing implementation of PCI mmap to fix X. Certain X11 servers such as the SIS server will only work if PCI mmap is implemented. This patch implements PCI mmap but to be on the same side so close to a release it only supports uncached mappings so performance will not be optimal for some uses such as framebuffers. Thanks to Zhang Le <r0bertz@gentoo.org> for the original report and testing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
#
540799e3 |
|
14-Oct-2008 |
Aurelien Jarno <aurelien@aurel32.net> |
MIPS: PCI: Scan busses when they are registered The patch below changes register_pci_controller() such that controllers being added after pcibios_init() has run are be scanned immediately. This is needed for example by the BCM47xx PCI controller, which is located on the SSB bus, which is now initialized after the PCI subsystem. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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#
47a5c976 |
|
23-Jul-2008 |
Atsushi Nemoto <anemo@mba.ocn.ne.jp> |
[MIPS] Introduce pcibios_plat_setup Introduce pcibios_plat_setup for platform-specific pcibios_setup. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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#
3450004a |
|
15-Jul-2008 |
Dmitri Vorobiev <dmitri.vorobiev@movial.fi> |
[MIPS] PCI: Make the pcibios_max_latency variable static The pcibios_max_latency variable is needlessly defined global, and this patch makes it static. Build-tested using malta_defconfig. Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@movial.fi> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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#
d58eaab5 |
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18-Jun-2008 |
Dmitri Vorobiev <dmitri.vorobiev@movial.fi> |
[MIPS] Namespace clean-up in arch/mips/pci/pci.c The following symbols hose_head hose_tail are needlessly defined global in arch/mips/pci/pci.c, and this patch makes them static. The variable pci_isa_hose is not used, and is removed by this patch. Spotted by namespacecheck. Tested by booting a Malta 4Kc board up to the shell prompt. Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@movial.fi> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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#
234fcd14 |
|
08-Mar-2008 |
Ralf Baechle <ralf@linux-mips.org> |
[MIPS] Fix loads of section missmatches Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
#
40d7c1aa |
|
19-Feb-2008 |
Ralf Baechle <ralf@linux-mips.org> |
[MIPS] PCI: Coding style fixes for pcibios_enable_resources. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
#
986c9485 |
|
19-Feb-2008 |
Ralf Baechle <ralf@linux-mips.org> |
[MIPS] PCI: Port i386 PCI fixes. The MIPS version of pcibios_enalbe_resources did not have the fixes from ed6d14f9760857c745206c978b80352fc09cfd19 yet which under circumstances similar to x86 might result in failures. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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#
d20e47e1 |
|
11-Dec-2007 |
Ralf Baechle <ralf@linux-mips.org> |
[MIPS] PCI: Make pcibios_fixup_device_resources ignore legacy resources. There might be other reasons why a resource might be marked as fixed such as a PCI UART holding the system console but until we use IORESOURCE_PCI_FIXED that way also this will work. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
#
41f9c78c |
|
29-Aug-2007 |
Ralf Baechle <ralf@linux-mips.org> |
[MIPS] PCI: Set need_domain_info if controller domain index is non-zero. This fixes this little funny: bigsur:/proc/bus/pci# ls -l total 0 dr-xr-xr-x 2 root root 0 Aug 28 19:31 00 dr-xr-xr-x 2 root root 0 Aug 28 19:31 00 dr-xr-xr-x 2 root root 0 Aug 28 19:31 01 dr-xr-xr-x 2 root root 0 Aug 28 19:31 03 -r--r--r-- 1 root root 0 Aug 28 19:31 devices Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
#
d4ef9dd3 |
|
29-Aug-2007 |
Ralf Baechle <ralf@linux-mips.org> |
[MIPS] PCI: Set need_domain_info if controller domain index is non-zero. This fixes this little funny: bigsur:/proc/bus/pci# ls -l total 0 dr-xr-xr-x 2 root root 0 Aug 28 19:31 00 dr-xr-xr-x 2 root root 0 Aug 28 19:31 00 dr-xr-xr-x 2 root root 0 Aug 28 19:31 01 dr-xr-xr-x 2 root root 0 Aug 28 19:31 03 -r--r--r-- 1 root root 0 Aug 28 19:31 devices Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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#
606bf782 |
|
23-Aug-2007 |
Ralf Baechle <ralf@linux-mips.org> |
[MIPS] HOTPLUG: Make register_pci_controller __devinit. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
#
c4aa2563 |
|
23-Aug-2007 |
Ralf Baechle <ralf@linux-mips.org> |
[MIPS] PCI: Remove __devinit attribute from pcibios_fixup_bus. Since 96bde06a2df1b363206d3cdef53134b84ff37813 several callers of pcibios_resource_to_bus are no longer marked __devinit resulting in a pile of modpost warnings if PCI && !HOTPLUG: MODPOST vmlinux.o WARNING: vmlinux.o(.text+0x15dde8): Section mismatch: reference to .init.text:pcibios_resource_to_bus (between 'pci_map_rom' and 'pci_map_rom_copy') WARNING: vmlinux.o(.text+0x15e140): Section mismatch: reference to .init.text:pcibios_resource_to_bus (between 'pci_update_resource' and 'pci_claim_resource') WARNING: vmlinux.o(.text+0x15f0cc): Section mismatch: reference to .init.text:pcibios_resource_to_bus (between 'pci_setup_cardbus' and 'pci_bus_assign_resources') WARNING: vmlinux.o(.text+0x15f0f0): Section mismatch: reference to .init.text:pcibios_resource_to_bus (between 'pci_setup_cardbus' and 'pci_bus_assign_resources') WARNING: vmlinux.o(.text+0x15f114): Section mismatch: reference to .init.text:pcibios_resource_to_bus (between 'pci_setup_cardbus' and 'pci_bus_assign_resources') WARNING: vmlinux.o(.text+0x15f138): Section mismatch: reference to .init.text:pcibios_resource_to_bus (between 'pci_setup_cardbus' and 'pci_bus_assign_resources') WARNING: vmlinux.o(.text+0x15f438): Section mismatch: reference to .init.text:pcibios_resource_to_bus (between 'pci_bus_assign_resources' and 'pbus_size_mem') WARNING: vmlinux.o(.text+0x15f4f4): Section mismatch: reference to .init.text:pcibios_resource_to_bus (between 'pci_bus_assign_resources' and 'pbus_size_mem') Removing __devinit from pcibios_resource_to_bus make the same necessary for pcibios_fixup_device_resources as well. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
#
4547d224 |
|
23-Aug-2007 |
Ralf Baechle <ralf@linux-mips.org> |
[MIPS] PCI: Remove __devinit attribute from pcibios_fixup_bus. Since 96bde06a2df1b363206d3cdef53134b84ff37813 pcibios_fixup_bus's caller pci_scan_child_bus is no longer marked __devinit resulting in this modpost warning if PCI && !HOTPLUG: MODPOST vmlinux.o WARNING: vmlinux.o(.text+0x158b9c): Section mismatch: reference to .init.text:pcibios_fixup_bus (between 'pci_scan_child_bus' and 'pci_scan_bus_parented') Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
#
8ed07a1c |
|
12-Jul-2007 |
Atsushi Nemoto <anemo@mba.ocn.ne.jp> |
[MIPS] Fix a sparse warning in arch/mips/pci/pci.c Fixes this warning: arch/mips/pci/pci.c:284:18: warning: symbol 'dev' shadows an earlier one arch/mips/pci/pci.c:272:17: originally declared here Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
#
639702bd |
|
08-Apr-2007 |
Thomas Bogendoerfer <tsbogend@alpha.franken.de> |
[MIPS] Register PCI host bridge resource earlier PCI based SNI RM machines have their EISA bus behind an Intel PCI/EISA bridge. So the PCI IO range must start at 0x0000. Changing that will break the PCI bus, because i8259.c already has registered it's IO addresses before the PCI bus gets initialized. Below is a patch, which will register the PCI host bridge resources inside register_pci_controller(). It also changes i8259.c to use insert_region(), because request_resource() will fail, if the IO space of the PIT hanging of the PCI host bridge (maybe passing the resource parent to init_i8259_irqs() is a cleaner fix for that). Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
#
44197088 |
|
22-Feb-2007 |
Atsushi Nemoto <anemo@mba.ocn.ne.jp> |
[MIPS] Mark pcibios_fixup_device_resources() as __devinit pcibios_fixup_device_resources() is called by pcibios_fixup_bus() which is marked as __devinit. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
#
140c1729 |
|
07-Dec-2006 |
Ralf Baechle <ralf@linux-mips.org> |
[MIPS] Iomap implementation. This implementation has support for the concept of one separate ioport address space by PCI domain. A pointer to the virtual address where the port space of a domain has been mapped has been added to struct pci_controller and systems should be fixed to fill in this value. For single domain systems this will be the same value as passed to set_io_port_base(). Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
#
6ab3d562 |
|
30-Jun-2006 |
Jörn Engel <joern@wohnheim.fh-wedel.de> |
Remove obsolete #include <linux/config.h> Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de> Signed-off-by: Adrian Bunk <bunk@stusta.de>
|
#
e31dd6e4 |
|
12-Jun-2006 |
Greg Kroah-Hartman <gregkh@suse.de> |
[PATCH] 64bit resource: change pci core and arch code to use resource_size_t Based on a patch series originally from Vivek Goyal <vgoyal@in.ibm.com> Cc: Vivek Goyal <vgoyal@in.ibm.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
|
#
610019ba |
|
17-Jun-2006 |
Ralf Baechle <ralf@linux-mips.org> |
[MIPS] Remove unused function alloc_pci_controller. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
#
8a1417de |
|
20-Oct-2005 |
Andrew Isaacson <adi@broadcom.com> |
BCM1480 HT support PCI support code for PLX 7250 PCI-X tunnel on BCM91480B BigSur board. Signed-Off-By: Andy Isaacson <adi@broadcom.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
#
e5de3b46 |
|
12-Jul-2005 |
Ralf Baechle <ralf@linux-mips.org> |
In pcibios_enable_resources go back to handling all PCI_NUM_RESOURCES resources. We tried previous but ran into problems ... Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
#
e63ea56f |
|
03-Sep-2005 |
Yoichi Yuasa <yuasa@hh.iij4u.or.jp> |
[PATCH] mips: add pcibios_bus_to_resource This patch has added pcibios_bus_to_resource to MIPS. Signed-off-by: Yoichi Yuasa <yuasa@hh.iij4u.or.jp> Cc: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
|
#
42a3b4f2 |
|
03-Sep-2005 |
Ralf Baechle <ralf@linux-mips.org> |
[PATCH] mips: nuke trailing whitespace Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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1da177e4 |
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16-Apr-2005 |
Linus Torvalds <torvalds@ppc970.osdl.org> |
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
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