#
26bff9eb |
|
06-May-2020 |
Thomas Bogendoerfer <tsbogend@alpha.franken.de> |
MIPS: Only include the platform file needed Instead of including all Platform files, we simply include the needed one and avoid clashes with makefile variables. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
|
#
b2afb64c |
|
03-Nov-2019 |
Huacai Chen <chenhuacai@kernel.org> |
MIPS: Loongson: Rename LOONGSON1 to LOONGSON32 Now old Loongson-2E/2F use LOONGSON2EF and will be removed in future, newer Loongson-2/3 use LOONGSON64. So rename LOONGSON1 to LOONGSON32 will make the naming style more unified. Signed-off-by: Huacai Chen <chenhc@lemote.com> [paulburton@kernel.org: Fix checkpatch whitespace warning in irqflags.h] Signed-off-by: Paul Burton <paulburton@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@linux-mips.org Cc: linux-mips@vger.kernel.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: Huacai Chen <chenhuacai@gmail.com>
|
#
7e280f6b |
|
22-Jan-2019 |
Jiaxun Yang <jiaxun.yang@flygoat.com> |
MIPS: Loongson32: Revert ISA level to MIPS32R2 GS232 core have implemented all necessary mips32r2 instructions. Serval missing FP instructions can be emulated by kernel. The issue of di instruction have been solved. Thus we revert the ISA level back to MIPS32R2. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org Cc: keguang.zhang@gmail.com
|
#
d1b83f0f |
|
22-Jan-2019 |
Jiaxun Yang <jiaxun.yang@flygoat.com> |
MIPS: Loongson32: Set load address to 0x80200000 PMON bootloader on Loongson-1C will use memory between 0x80100000 and 0x80200000 as stack. Use 0x80100000 as load address may hang the bootloader during loading. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org Cc: keguang.zhang@gmail.com
|
#
60bc84e2 |
|
04-Jan-2017 |
谢致邦 (XIE Zhibang) <Yeking@Red54.com> |
MIPS: Loongson: Merge load addresses Systems based upon the Loongson 1B & 1C CPUs share the same load address, as do those based upon Loongson 1A. Unify the definition of this load address to reduce duplication & avoid the need for an extra Loongson 1A case in future. [paul.burton@mips.com: Rewrite commit message.] Signed-off-by: 谢致邦 (XIE Zhibang) <Yeking@Red54.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/14927/ Cc: linux-mips@linux-mips.org
|
#
968dc5a0 |
|
01-Jun-2017 |
谢致邦 (XIE Zhibang) <Yeking@Red54.com> |
MIPS: Loongson: Set Loongson32 to MIPS32R1 LS232 (Loonson 2-issue 32-bit, also called GS232 (Godson 2-issue 32-bit)) is the CPU core (microarchitecture) of Loongson 1A/1B/1C. According to "LS232 用户手册 (LS232 User Manual)", LS232 implements the MIPS32 Release 1 instruction set, and part of the MIPS32 Release 2 instruction set. In the manual, LS232 implements all of the MIPS32R2 instruction set except the FPU instructions, and LS232 also implements 5 FPU instructions of the MIPS32R2 instruction set: CEIL.L.fmt, CVT.L.fmt, FLOOR.L.fmt, TRUNC.L.fmt, and ROUND.L.fmt. But a bug of the DI instruction has been found during tests, the DI instruction can not disable interrupts in arch_local_irq_disable() with CONFIG_PREEMPT_NONE=y and CFLAGS='-mno-branch-likely' in some cases. [paul.burton@mips.com: - Remove the _MIPS_ISA redefinition to match the change made for the generic MIPSr1 CPUs by commit 344ebf09949c ("MIPS: Always use -march=<arch>, not -<arch> shortcuts").] Signed-off-by: 谢致邦 (XIE Zhibang) <Yeking@Red54.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/16155/ Cc: linux-mips@linux-mips.org Cc: ralf@linux-mips.org
|
#
12e3280b |
|
18-May-2016 |
Yang Ling <gnaygnil@gmail.com> |
MIPS: Loongson1C: Add board support Adds basic platform devices for Loongson1C, including serial port and ethernet. Signed-off-by: Yang Ling <gnaygnil@gmail.com> Cc: keguang.zhang@gmail.com Cc: chenhc@lemote.com Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13304/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
#
30ad29bb |
|
20-Apr-2015 |
Huacai Chen <chenhuacai@kernel.org> |
MIPS: Loongson: Naming style cleanup and rework Currently, code of Loongson-2/3 is under loongson directory and code of Loongson-1 is under loongson1 directory. Besides, there are Kconfig options such as MACH_LOONGSON and MACH_LOONGSON1. This naming style is very ugly and confusing. Since Loongson-2/3 are both 64-bit general- purpose CPU while Loongson-1 is 32-bit SoC, we rename both file names and Kconfig symbols from loongson/loongson1 to loongson64/loongson32. [ralf@linux-mips.org: Resolve a number of simple conflicts.] Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: Kelvin Cheung <keguang.zhang@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/9790/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|