History log of /linux-master/arch/microblaze/include/asm/cache.h
Revision Date Author Comments
# 4ea57ce4 13-Jun-2023 Catalin Marinas <catalin.marinas@arm.com>

microblaze: move the ARCH_{DMA,SLAB}_MINALIGN definitions to asm/cache.h

The microblaze architecture defines ARCH_DMA_MINALIGN in asm/page.h. Move
it to asm/cache.h to allow a generic ARCH_DMA_MINALIGN definition in
linux/cache.h without redefine errors/warnings.

While at it, also move ARCH_SLAB_MINALIGN to asm/cache.h for
consistency.

Link: https://lkml.kernel.org/r/20230613155245.1228274-3-catalin.marinas@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Christophe Leroy <christophe.leroy@csgroup.eu>
Cc: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>
Cc: kernel test robot <lkp@intel.com>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Nicholas Piggin <npiggin@gmail.com>
Cc: Rich Felker <dalias@libc.org>
Cc: Vlastimil Babka <vbabka@suse.cz>
Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>


# 4726dd60 03-Feb-2020 Michal Simek <michal.simek@xilinx.com>

microblaze: Convert headers to SPDX license

Covert all headers to SPDX.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Stefan Asserhall <stefan.asserhall@xilinx.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>


# 598acab4 26-Apr-2010 Michal Simek <monstr@monstr.eu>

microblaze: Define correct L1_CACHE_SHIFT value

Microblaze cacheline length is configurable and current cpu
uses two cacheline length 4 and 8.

We are taking conservative maximum value to be sure that cacheline
alignment is satisfied for all cases.

Here is the calculation for cacheline lenght 8 32bit=4Byte values
which is corresponding with SHIFT 5.

Signed-off-by: Michal Simek <monstr@monstr.eu>


# a1f55113 15-Oct-2009 Michal Simek <monstr@monstr.eu>

microblaze: Move cache macro from cache.h to cacheflush.h

Signed-off-by: Michal Simek <monstr@monstr.eu>


# ceb8944b 16-Apr-2009 Michal Simek <monstr@monstr.eu>

microblaze: Remove uncache shadow condition

Uncached shadow feature is not supported in current
kernel code that's why I removed it.

Signed-off-by: Michal Simek <monstr@monstr.eu>


# 8beb8503 27-Mar-2009 Michal Simek <monstr@monstr.eu>

microblaze_v8: cache support

Reviewed-by: Ingo Molnar <mingo@elte.hu>
Acked-by: Stephen Neuendorffer <stephen.neuendorffer@xilinx.com>
Acked-by: John Linn <john.linn@xilinx.com>
Acked-by: John Williams <john.williams@petalogix.com>
Signed-off-by: Michal Simek <monstr@monstr.eu>