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186f69b6 |
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06-Apr-2022 |
Guo Ren <guoren@kernel.org> |
csky: atomic: Optimize cmpxchg with acquire & release Optimize cmpxchg with ASM acquire/release fence ASM instructions instead of previous generic based. Prevent a fence when cmxchg's first load != old. Comments by Rutland: 8e86f0b409a4 ("arm64: atomics: fix use of acquire + release for full barrier semantics") Comments by Boqun: FWIW, you probably need to make sure that a barrier instruction inside an lr/sc loop is a good thing. IIUC, the execution time of a barrier instruction is determined by the status of store buffers and invalidate queues (and probably other stuffs), so it may increase the execution time of the lr/sc loop, and make it unlikely to succeed. But this really depends on how the arch executes these instructions. Link: https://lore.kernel.org/linux-riscv/CAJF2gTSAxpAi=LbAdu7jntZRUa=-dJwL0VfmDfBV5MHB=rcZ-w@mail.gmail.com/T/#m27a0f1342995deae49ce1d0e1f2683f8a181d6c3 Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Signed-off-by: Guo Ren <guoren@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com>
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0b1f557a |
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05-Mar-2021 |
Junlin Yang <yangjunlin@yulong.com> |
csky: Fixup typos fixes three typos found by codespell. Signed-off-by: Junlin Yang <yangjunlin@yulong.com> Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
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6607aa6f |
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27-Feb-2021 |
Guo Ren <guoren@linux.alibaba.com> |
csky: Fixup compile error : error: C++ style comments are not allowed in ISO C90 // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. ^ error: (this will be reported only once per input file) Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
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8d11f21a |
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19-Dec-2020 |
Guo Ren <guoren@linux.alibaba.com> |
csky: Fixup barrier design Remove shareable bit for ordering barrier, just keep ordering in current hart is enough for SMP. Using three continuous sync.is as PTW barrier to prevent speculative PTW in 860 microarchitecture. Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
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81b23ba6 |
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30-Jul-2019 |
Guo Ren <ren_guo@c-sky.com> |
csky: Fixup mb() synchronization problem The mb() is the superset of dma and smp. Using bar.xxx to implement mb() will cause problem when sync data with dma device, becasue bar.xxx couldn't guarantee bus transactions finished at outside bus level. We must use sync.s instead of bar.xxx for dma data synchronization and it will guarantee retirement after getting the bus bresponse. Changes for V2: - Use sync.s for all mb, rmb, wmb, dma_wmb, dma_rmb. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Cc: Arnd Bergmann <arnd@arndb.de>
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00a9730e |
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05-Sep-2018 |
Guo Ren <ren_guo@c-sky.com> |
csky: Cache and TLB routines This patch adds cache and tlb sync codes for abiv1 & abiv2. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
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