arm64: zynqmp: Align usb clock nodes with binding

dwc3-xilinx.yaml defines 2 clocks which are not defined that's why define
them (bus_early clock is moved to bus_clk in glue logic).
With also describing kv260 assigned clock rates with assigned clocks.
Also add missing status property to standard dwc3 core.

Link: https://lore.kernel.org/r/aa4c65a8997c7a65f23da3a3088bb5eb64281307.1704728353.git.michal.simek@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>

arm64: zynqmp: Describe assigned-clocks for uarts

Describe assigned-clocks for both uarts. SOM is using this functionality.

Link: https://lore.kernel.org/r/21579f273554a19bc95a40f49956793b5261627f.1704728353.git.michal.simek@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>

arm64: zynqmp: Assign TSU clock frequency for GEMs

Allow changing TSU clock for all GEMs. Kria SOM is using this
functionality that's why set TSU clock frequency as 250MHz (minimum when
running at 1G) to allow PTP functionality.

Signed-off-by: Harini Katakam <harini.katakam@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/3b9285b50a2a4abb136ecb0873343a4e84626581.1686228675.git.michal.simek@amd.com

arm64: zynqmp: Switch to amd.com emails

Update my and DPs email address to match current setup.

Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/108cbbbab29e13d386d38a779fd582f10844a030.1685443337.git.michal.simek@amd.com

arm64: zynqmp: Add phase tags marking

bootph-all as phase tag was added to dt-schema
(dtschema/schemas/bootph.yaml) to cover U-Boot challenges with DT.
That's why add it also to Linux to be aligned with bootloader requirement.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/48b554aef75d11e6ad2ef7d21f22accb35432112.1683034376.git.michal.simek@amd.com

arm64: zynqmp: Setup clock for DP and DPDMA

Clocks are coming from shared HW design where these frequencies should be
aligned with PLL setup.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/807e22371394222f728ff7d6b190a96a12145439.1683034376.git.michal.simek@amd.com

arm64: zynqmp: Use assigned-clock-rates for setting up SD clock in SOM

With limited low level configuration done via psu-init only IPs connected
on SOM are initialized and configured. All IPs connected to carrier card
are not initialized. There is a need to do proper reset, pin configuration
and also clock setting.
The patch targets the last part which is setting up proper clock for EMMC
on production SOMs and SD on kv260-revB.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/cf5a4e412e1674500a71a0b1eed7fa8393f37ae9.1683034376.git.michal.simek@amd.com

arm64: zynqmp: Add mali-400 gpu node for zynqmp

Add mali-400 gpu node for zynqmp.
Enabled gpu node for xilinx boards.

Signed-off-by: Parth Gajjar <parth.gajjar@amd.com>
Signed-off-by: Vishal Sagar <vishal.sagar@amd.com>
Link: https://lore.kernel.org/r/20230321070619.29440-3-parth.gajjar@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>

arm64: dts: zynqmp: Remove clock-names from GEM in zynqmp-clk-ccf.dtsi

Remove clock-names from GEM nodes from clk-ccf because they should be only
present in zynqmp.dtsi. And as is visible both clock-names defined didn't
really match.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/24ce27f91a55ed04ca7ee2ff7db0c674702ef722.1670594284.git.michal.simek@amd.com

arm64: dts: zynqmp: add AMS driver to device tree

Add an entry to the ZynqMP device tree to support the AMS device which
now has a driver in mainline.

Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Reviewed-by: Michael Tretter <m.tretter@pengutronix.de>
Link: https://lore.kernel.org/r/20220120010246.3794962-2-robert.hancock@calian.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

arm64: dts: zynqmp: Move USB clocks to dwc3 node

These clocks are not used by the dwc3-xilinx driver except to
enable/disable them. Move them to the dwc3 node so its driver can use
them to configure the reference clock period.

Tested-by: Robert Hancock <robert.hancock@calian.com>
Reviewed-by: Robert Hancock <robert.hancock@calian.com>
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Link: https://lore.kernel.org/r/20220127200636.1456175-7-sean.anderson@seco.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

arm64: zynqmp: Move clock node to zynqmp-clk-ccf.dtsi

Using clock firmware driver is not the only one option how to configure
clock. In past fixed clocks were also used and that configuration is still
valid that's why move clock firmware node to the same file where zynqmp_clk
references are used.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/48bfd8cf0de4d10b9c4d745218595f28954f70d5.1623684253.git.michal.simek@xilinx.com

arm64: dts: zynqmp: Add DisplayPort subsystem

Add a DT node for the DisplayPort subsystem, a hard IP present in the
Zynq Ultrascale+ MPSoC.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/4d978aef852cacdfb35aa8e50d648a787e73b90c.1611232558.git.michal.simek@xilinx.com

arm64: dts: zynqmp: Add DPDMA node

Add a DT node for the DisplayPort DMA engine (DPDMA).

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/3d11015512a085592f2aca76eeddc04178d38bbe.1611232558.git.michal.simek@xilinx.com

arm64: dts: zynqmp: Add missing lpd watchdog node

Xilinx ZynqMP SoC has FPD (Full Power Domain) and LPD (Low Power Domain)
watchdogs. There are cases where also LPD WDT should be used by Arm cores
that's why list it with disabled status.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/0489a1d5528614f1d570ea153d38b813f0c1eb9f.1611224800.git.michal.simek@xilinx.com

arm64: dts: zynqmp: Wire zynqmp qspi controller

Add missing ZynqMP qspi IP. It works in single mode only.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/5cebbc59a452f282c4ce0f0e1dffecadac8f126a.1611224800.git.michal.simek@xilinx.com

arm64: dts: zynqmp: Wire arasan nand controller

Add missing arasan controller with clocks. Disable it by default. Every
board can enable it with specifying others properties.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/05cc1ce7973ac5200aeca428c137b422c827c5e8.1611224800.git.michal.simek@xilinx.com

arm64: dts: zynqmp: Remove undocumented u-boot properties

u-boot, DT properties are not documented anywhere in Linux DT binding
that's why remove them.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/8ba339425b9c9f319bdedce7741367055a30713c.1598257720.git.michal.simek@xilinx.com
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>

arm64: dts: xilinx: Add the clock nodes for zynqmp

Add clock nodes for zynqmp based on CCF.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>