#
1a5010ea |
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15-Feb-2024 |
Devarsh Thakkar <devarsht@ti.com> |
arm64: dts: ti: Add common1 register space for AM65x SoC This adds common1 register space for AM65x SoC which is using TI's Keystone display hardware and supporting it as described in Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml Fixes: fc539b90eda2 ("arm64: dts: ti: am654: Add DSS node") Signed-off-by: Devarsh Thakkar <devarsht@ti.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Reviewed-by: Aradhya Bhatia <a-bhatia1@ti.com> Link: https://lore.kernel.org/r/20240216062426.4170528-3-devarsht@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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#
2822c791 |
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22-Jan-2024 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-am65: Add MIT license along with GPL-2.0 Modify license to include dual licensing as GPL-2.0-only OR MIT license for SoC and TI evm device tree files. This allows for Linux kernel device tree to be used in other Operating System ecosystems such as Zephyr or FreeBSD. While at this, update the GPL-2.0 to be GPL-2.0-only to be in sync with latest SPDX conventions (GPL-2.0 is deprecated). While at this, update the TI copyright year to sync with current year to indicate license change (and add it at least for one file which was missing TI copyright). Cc: "Alexander A. Klimov" <grandmaster@al2klimov.de> Cc: Jan Kiszka <jan.kiszka@siemens.com> Cc: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Cc: Matthias Schiffer <matthias.schiffer@ew.tq-group.com> Cc: Pierre Gondois <pierre.gondois@arm.com> Cc: Rob Herring <robh@kernel.org> Cc: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Cc: Tony Lindgren <tony@atomide.com> Acked-by: Jan Kiszka <jan.kiszka@siemens.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com> Acked-by: Pierre Gondois <pierre.gondois@arm.com> Acked-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20240122145539.194512-7-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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#
e074d9d9 |
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23-Jan-2024 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am65: Remove PCIe endpoint nodes These nodes are example nodes for the PCIe controller in "endpoint" mode. By default the controller is in "root complex" mode and there is already a DT node for the same. Examples should go in the bindings or other documentation. Remove this node. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20240124183659.149119-3-afd@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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#
21cfb2ba |
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09-Jan-2024 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am654-main: Add device tree entry for SGX GPU Add SGX GPU device entry to base AM654 dtsi file. Signed-off-by: Andrew Davis <afd@ti.com> Reviewed-by: Javier Martinez Canillas <javierm@redhat.com> Message-ID: <20240109171950.31010-10-afd@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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#
0fa8d3a5 |
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13-Dec-2023 |
Manorit Chawdhry <m-chawdhry@ti.com> |
arm64: dts: ti: k3-am65: Add additional regs for DMA components Add additional reg properties for UDMA and RingAcc nodes which are mostly used by bootloader components before Device Manager firmware services are available, in order to setup DMA transfers. Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jai Luthra <j-luthra@ti.com> Link: https://lore.kernel.org/r/20231213135138.929517-2-vigneshr@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
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#
006d9351 |
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17-Nov-2023 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am65: Enable SDHCI nodes at the board level SDHCI nodes defined in the top-level AM65 SoC dtsi files are incomplete and will not be functional unless they are extended. As the attached SD/eMMC is only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the SDHCI nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20231117163339.89952-1-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
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#
1a4402e1 |
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17-Nov-2023 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am65: Add full compatible to dss-oldi-io-ctrl node This matches the binding for this register region which fixes a couple DTS check warnings. While here trim the leading 0s from the "reg" definition. Signed-off-by: Andrew Davis <afd@ti.com> Reviewed-by: Aradhya Bhatia <a-bhatia1@ti.com> Link: https://lore.kernel.org/r/20231117141433.9461-1-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
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#
b5716085 |
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06-Nov-2023 |
Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> |
arm64: dts: ti: k3-am65-main: Fix DSS irq trigger type DSS irq trigger type is set to IRQ_TYPE_EDGE_RISING in the DT file, but the TRM says it is level triggered. For some reason triggering on rising edge results in double the amount of expected interrupts, e.g. for normal page flipping test the number of interrupts per second is 2 * fps. It is as if the IRQ triggers on both edges. There are no other side effects to this issue than slightly increased CPU & power consumption due to the extra interrupt. Switching to IRQ_TYPE_LEVEL_HIGH is correct and fixes the issue, so let's do that. Fixes: fc539b90eda2 ("arm64: dts: ti: am654: Add DSS node") Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Reviewed-by: Aradhya Bhatia <a-bhatia1@ti.com> Link: https://lore.kernel.org/r/20231106-am65-dss-clk-edge-v1-1-4a959fec0e1e@ideasonboard.com Signed-off-by: Nishanth Menon <nm@ti.com>
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#
209f4e89 |
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19-Oct-2023 |
MD Danish Anwar <danishanwar@ti.com> |
arm64: dts: ti: k3-am65-main: Add ICSSG IEP nodes The ICSSG IP on AM65x SoCs have two Industrial Ethernet Peripherals (IEPs) to manage/generate Industrial Ethernet functions such as time stamping. Each IEP sub-module is sourced from an internal clock mux that can be sourced from either of the IP instance's ICSSG_IEP_GCLK or ICSSG_ICLK. Add the IEP nodes for all the ICSSG instances. Signed-off-by: MD Danish Anwar <danishanwar@ti.com> Link: https://lore.kernel.org/r/20231020051937.3709871-2-danishanwar@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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#
6507bfa7 |
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05-Oct-2023 |
Vignesh Raghavendra <vigneshr@ti.com> |
arm64: dts: ti: k3-*: Convert NAVSS to simple-bus "simple-mfd" as standalone compatible is frowned upon, so model main and MCU NAVSS (Navigator SubSystem) nodes as simple-bus as there is really no need for these nodes to be MFD. Link: https://lore.kernel.org/r/20231005151302.1290363-3-vigneshr@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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#
702110c2 |
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09-Aug-2023 |
Vignesh Raghavendra <vigneshr@ti.com> |
arm64: dts: ti: k3: Add cfg reg region to ringacc node Add register range of ringacc cfg node to all k3 SoC dtsi files. This is normally under Device Management firmware control but some entities like bootloader have to access directly and thus required to be present in DT. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230809175932.2553156-3-vigneshr@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
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#
f6a5b651 |
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01-Aug-2023 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3: Fix epwm_tbclk node name to generic name The name "clock" is not allowed for nodes, use "clock-controller" to remove the DTS check warning. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20230802174521.236255-3-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
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#
2a7cc7be |
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13-Jul-2023 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: Fix compatible of ti,*-ehrpwm-tbclk TI EHRPWM compatible is just ti,*-ehrpwm-tbclk without needing a syscon compatibility. Fixes the following dtbs_check warnings: compatible: [''ti,am654-ehrpwm-tbclk, 'syscon'] is too long compatible: ['ti,am64-epwm-tbclk', 'syscon'] is too long compatible: ['ti,am62-epwm-tbclk', 'syscon'] is too long Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230713184759.3336536-1-nm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
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#
414772b8 |
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02-Jul-2023 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
arm64: dts: ti: minor whitespace cleanup around '=' The DTS code coding style expects exactly one space before and after '=' sign. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230702185221.44319-1-krzysztof.kozlowski@linaro.org Signed-off-by: Nishanth Menon <nm@ti.com>
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2b9bb988 |
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07-Jun-2023 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-am65-main: Drop deprecated ti,otap-del-sel property ti,otap-del-sel has been deprecated in favor of ti,otap-del-sel-legacy. Drop the duplicate and misleading ti,otap-del-sel property. Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230607132043.3932726-3-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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13fdc081 |
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24-Apr-2023 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-am65-main: Remove "syscon" nodes added for pcieX_ctrl Remove "syscon" nodes added for pcieX_ctrl and have the PCIe node point to the parent with an offset argument. This change is as discussed in [1]. [1] http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230424144949.244135-2-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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#
cfc75a93 |
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07-Nov-2022 |
Jayesh Choudhary <j-choudhary@ti.com> |
arm64: dts: ti: k3-am65-main: Drop RNG clock The x1-clk used by trng submodule comes directly from the system clock after a fixed divider. It is always running and has a fixed frequency that cannot be changed, making it uncontrollable. Hence this property should be dropped from the rng node. Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20221107110607.59216-2-j-choudhary@ti.com
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#
b86833ab |
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31-Oct-2022 |
Jayesh Choudhary <j-choudhary@ti.com> |
arm64: dts: ti: k3-am65-main: Drop dma-coherent in crypto node crypto driver itself is not dma-coherent. So drop it. Fixes: b366b2409c97 ("arm64: dts: ti: k3-am6: Add crypto accelarator node") Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com> Link: https://lore.kernel.org/r/20221031152520.355653-2-j-choudhary@ti.com
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#
cdbaf880 |
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15-Nov-2022 |
Tony Lindgren <tony@atomide.com> |
arm64: dts: ti: k3-am65: Add general purpose timers for am65 There are 12 general purpose timers on am65 that can be used for things like PWM using pwm-omap-dmtimer driver. There are also additional four timers in the MCU domain that do not have interrupts routable for Linux. We configure the timers with the 25 MHz input clock by default as the 32.768 kHz clock may not be wired on the device. We leave the MCU domain timers clock mux unconfigured, and mark the MCU domain timers reserved. The MCU domain timers are likely reserved by the software for the ESM module. Compared to am64, the timer clocks are different on am65. And the MCU timers are at a different IO address. Then j72 adds more timers compared to am65 with a total of 30 timers. And the j72 clocks are different. To avoid duplication for dtsi files, eventually we may want to consider adding timer specific shared dtsi files with the timer clocks mapped using SoC specific files in include/dt-bindings/clock. But let's get am65 timers usable first. Cc: Keerthy <j-keerthy@ti.com> Cc: Nishanth Menon <nm@ti.com> Cc: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20221115154842.7755-3-tony@atomide.com
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#
7928c712 |
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15-Nov-2022 |
Tony Lindgren <tony@atomide.com> |
arm64: dts: ti: k3-am65: Configure pinctrl for timer IO pads Compared to the earlier TI SoCs, am65 has an additional level of dedicated multiplexing registers for the timer IO pads. There are timer IO pads in the MCU domain, and in the MAIN domain. These pads can be muxed for the related timers. There are timer IO control registers for input and output. The registers for CTRLMMR_TIMER*_CTRL and CTRLMMR_MCU_TIMER*_CTRL are used to control the input. The registers for CTCTRLMMR_TIMERIO*_CTRL and CTRLMMR_MCU_TIMERIO*_CTRL the output. The multiplexing is documented in TRM "5.1.2.3.1.4 Timer IO Muxing Control Registers" and "5.1.3.3.1.5 Timer IO Muxing Control Registers", and the CASCADE_EN bit is documented in TRM "12.8.3.1 Timers Overview". For chaining timers, the timer IO control registers also have a CASCADE_EN input bit in the CTRLMMR_TIMER*_CTRL in the registers. The CASCADE_EN bit muxes the previous timer output, or possibly and external TIMER_IO pad source, to the input clock of the selected timer instance for odd numered timers. For the even numbered timers, the CASCADE_EN bit does not do anything. The timer cascade input routing options are shown in TRM "Figure 12-3632. Timers Overview". For handling beyond multiplexing, the driver support for timer cascading should be likely be handled via the clock framework. Cc: Keerthy <j-keerthy@ti.com> Cc: Nishanth Menon <nm@ti.com> Cc: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20221115154842.7755-2-tony@atomide.com
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81685b3d |
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15-Nov-2022 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
arm64: dts: ti: Trim addresses to 8 digits Hex numbers in addresses and sizes should be rather eight digits, not nine. Drop leading zeros. No functional change (same DTB). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20221115105044.95225-1-krzysztof.kozlowski@linaro.org
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#
fdb02688 |
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28-Oct-2022 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am65: Enable McASP nodes at the board level McASP nodes defined in the top-level AM65x SoC dtsi files are incomplete and will not be functional unless they are extended with pinmux information. As the pinmux is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the McASP nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20221028142417.10642-12-afd@ti.com
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3f9089ea |
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28-Oct-2022 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am65: Enable Mailbox nodes at the board level Mailbox nodes defined in the top-level AM65x SoC dtsi files are incomplete and may not be functional unless they are extended with a chosen interrupt and connection to a remote processor. As the remote processors depend on memory nodes which are only known at the board integration level, these nodes should only be enabled when provided with the above information. Disable the Mailbox nodes in the dtsi files and only enable the ones that are actually used on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20221028142417.10642-11-afd@ti.com
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7ff8432c |
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28-Oct-2022 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am65: Enable PCIe nodes at the board level PCIe nodes defined in the top-level AM65x SoC dtsi files are incomplete and will not be functional unless they are extended with a SerDes PHY. And usually only one of the two modes can be used at a time as they share a SerDes link. As the PHY and mode is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the PCIe nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20221028142417.10642-10-afd@ti.com
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c75c5c0b |
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28-Oct-2022 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am65: Enable MDIO nodes at the board level MDIO nodes defined in the top-level AM65x SoC dtsi files are incomplete and will not be functional unless they are extended with a pinmux. As the attached PHY is only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the MDIO nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20221028142417.10642-8-afd@ti.com
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c1d1189e |
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28-Oct-2022 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am65: Enable ECAP nodes at the board level ECAP nodes defined in the top-level AM65x SoC dtsi files are incomplete and will not be functional unless they are extended with pinmux information. (These and the EPWM nodes could be used to trigger internal actions but they are not used like that currently) As the pinmux is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the ECAP nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20221028142417.10642-6-afd@ti.com
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5780cf09 |
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28-Oct-2022 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am65: Enable EPWM nodes at the board level EPWM nodes defined in the top-level AM65x SoC dtsi files are incomplete and will not be functional unless they are extended with pinmux information. As the pinmux is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the EPWM nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20221028142417.10642-5-afd@ti.com
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1c49cbb1 |
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28-Oct-2022 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am65: Enable SPI nodes at the board level SPI nodes defined in the top-level AM65x SoC dtsi files are incomplete and will not be functional unless they are extended with pinmux information. As the pinmux is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the SPI nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20221028142417.10642-4-afd@ti.com
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c0a5ba87 |
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28-Oct-2022 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am65: Enable I2C nodes at the board level I2C nodes defined in the top-level AM65x SoC dtsi files are incomplete and will not be functional unless they are extended with pinmux information. As the pinmux is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the I2C nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20221028142417.10642-3-afd@ti.com
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#
65e8781a |
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28-Oct-2022 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am65: Enable UART nodes at the board level UART nodes defined in the top-level AM65x SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux information. As the pinmux is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the UART nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20221028142417.10642-2-afd@ti.com
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49611f43 |
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22-Aug-2022 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am65-main: Do not exclusively claim SA2UL The SA2UL hardware is also used by SYSFW and OP-TEE. It should be requested using the shared TI-SCI flags instead of the exclusive flags or the request will fail. Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jayesh Choudhary <j-choudhary@ti.com> Link: https://lore.kernel.org/r/20220823001136.10944-3-afd@ti.com
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#
530eaa57 |
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22-Aug-2022 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am65-main: Move SA2UL to unused PSI-L thread ID The first TX and first two RX PSI-L threads for SA2UL are used by SYSFW on High Security(HS) devices. Use the next available threads to prevent resource allocation conflicts. Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jayesh Choudhary <j-choudhary@ti.com> Link: https://lore.kernel.org/r/20220823001136.10944-2-afd@ti.com
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1ad4669b |
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22-Aug-2022 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am65-main: Disable RNG node The hardware random number generator is used by OP-TEE and is access is denied to other users with SoC level bus firewalls. Any access to this device from Linux will result in firewall errors. We could remove this node, but it is still valid device description, and it is possible it could be re-enabled in the bootloader if OP-TEE is not used. So only disable this node for now. Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jayesh Choudhary <j-choudhary@ti.com> Link: https://lore.kernel.org/r/20220823001136.10944-1-afd@ti.com
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5888f1ed |
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26-May-2022 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
arm64: dts: ti: Adjust whitespace around '=' Fix whitespace coding style: use single space instead of tabs or multiple spaces around '=' sign in property assignment. No functional changes (same DTB). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20220526204139.831895-1-krzysztof.kozlowski@linaro.org
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8cae268b |
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15-Feb-2022 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-am65: Fix gic-v3 compatible regs Though GIC ARE option is disabled for no GIC-v2 compatibility, Cortex-A53 is free to implement the CPU interface as long as it communicates with the GIC using the stream protocol. This requires that the SoC integration mark out the PERIPHBASE[1] as reserved area within the SoC. See longer discussion in [2] for further information. Update the GIC register map to indicate offsets from PERIPHBASE based on [3]. Without doing this, systems like kvm will not function with gic-v2 emulation. [1] https://developer.arm.com/documentation/ddi0500/e/system-control/aarch64-register-descriptions/configuration-base-address-register--el1 [2] https://lore.kernel.org/all/87k0e0tirw.wl-maz@kernel.org/ [3] https://developer.arm.com/documentation/ddi0500/e/generic-interrupt-controller-cpu-interface/gic-programmers-model/memory-map Cc: stable@vger.kernel.org # 5.10+ Fixes: ea47eed33a3f ("arm64: dts: ti: Add Support for AM654 SoC") Reported-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220215201008.15235-2-nm@ti.com
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1c953935 |
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14-Sep-2021 |
Kishon Vijay Abraham I <kishon@ti.com> |
arm64: dts: ti: k3-am65-main: Cleanup "ranges" property in "pcie" DT node *dtbs_check* on "Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml" YAML file resulted in the following errors. pcie@5500000: ranges: 'oneOf' conditional failed, one must be fixed: pcie@5600000: ranges: 'oneOf' conditional failed, one must be fixed Cleanup "ranges" property in "pcie" DT node to fix the above errors. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20210915055358.19997-7-kishon@ti.com
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d65f069e |
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07-Jun-2021 |
Vignesh Raghavendra <vigneshr@ti.com> |
arm64: dts: ti: Drop reg-io-width/reg-shift from UART nodes 8250_omap compatible UART IPs on all SoCs have registers aligned at 4 byte address boundary and constant byte addressability. Thus there is no need for reg-io-width or reg-shift DT properties. These properties are not used by 8250_omap driver nor documented as part of binding document. Therefore drop them. This is in preparation to move omap-serial.txt to YAML format. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20210607134558.23704-1-vigneshr@ti.com
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d49a769d |
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01-Jun-2021 |
Roger Quadros <rogerq@ti.com> |
arm64: dts: ti: k3-am65-main: Add ICSSG MDIO nodes The ICSSGs on K3 AM65x SoCs contain an MDIO controller that can be used to control external PHYs associated with the Industrial Ethernet peripherals within each ICSSG instance. The MDIO module used within the ICSSG is similar to the MDIO Controller used in TI Davinci SoCs. A bus frequency of 1 MHz is chosen for the MDIO operations. The nodes are added and enabled in the common k3-am65-main.dtsi file by default, and disabled in the existing AM65 board dts files. These nodes need pinctrl lines, and so should be enabled only on boards where they are actually wired and pinned out for ICSSG Ethernet. Any new board dts file should disable these if they are not sure. Signed-off-by: Roger Quadros <rogerq@ti.com> [s-anna@ti.com: move the disabled status to board dts files] Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20210601150032.11432-2-s-anna@ti.com
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79b08ae7 |
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28-May-2021 |
Aswath Govindraju <a-govindraju@ti.com> |
arm64: dts: ti: k3-am65: Add support for UHS-I modes in MMCSD1 subsystem UHS-I speed modes are supported in AM65 S.R. 2.0 SoC[1]. Add support by removing the no-1-8-v tag and including the voltage regulator device tree nodes for power cycling. However, the 4 bit interface of AM65 SR 1.0 cannot be supported at 3.3 V or 1.8 V because of erratas i2025 and i2026 [2]. As the SD card is the primary boot mode for development usecases, continue to enable SD card and disable UHS-I modes in it to minimize any ageing issues happening because of erratas. k3-am6528-iot2050-basic and k3-am6548-iot2050-advanced boards use S.R. 1.0 version of AM65 SoC. Therefore, add no-1-8-v in sdhci1 device tree node of the common iot2050 device tree file. [1] - https://www.ti.com/lit/ug/spruid7e/spruid7e.pdf, section 12.3.6.1.1 [2] - https://www.ti.com/lit/er/sprz452e/sprz452e.pdf Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Acked-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20210529033749.6250-1-a-govindraju@ti.com
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#
cab12bad |
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11-May-2021 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3*: Introduce reg definition for interrupt routers Interrupt routers are memory mapped peripherals, that are organized in our dts bus hierarchy to closely represents the actual hardware behavior. However, without explicitly calling out the reg property, using 2021.03+ dt-schema package, this exposes the following problem with dtbs_check: /arch/arm64/boot/dts/ti/k3-am654-base-board.dt.yaml: bus@100000: interrupt-controller0: {'type': 'object'} is not allowed for {'compatible': ['ti,sci-intr'], ..... Even though we don't use interrupt router directly via memory mapped registers and have to use it via the system controller, the hardware block is memory mapped, so describe the base address in device tree. This is a valid, comprehensive description of hardware and permitted by the existing ti,sci-intr schema. Reviewed-by: Tero Kristo <kristo@kernel.org> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20210511194821.13919-1-nm@ti.com
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#
9ecdb6d6 |
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10-May-2021 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-am65|j721e|am64: Map the dma / navigator subsystem via explicit ranges Instead of using empty ranges property, lets map explicitly the address range that is mapped onto the dma / navigator subsystems (navss/dmss). This is also exposed via the dtbs_check with dt-schema newer than 2021.03 version by throwing out following: arch/arm64/boot/dts/ti/k3-am654-base-board.dt.yaml: bus@100000: main-navss: {'type': 'object'} is not allowed for {'compatible': ['simple-mfd'], '#address-cells': [[2]], ..... This has already been correctly done for J7200, however was missed for other k3 SoCs. Fix that oversight. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tero Kristo <kristo@kernel.org> Acked-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20210510145429.8752-1-nm@ti.com
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#
9818d1a0 |
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04-Mar-2021 |
Suman Anna <s-anna@ti.com> |
arm64: dts: ti: k3-am65-main: Add ICSSG nodes Add the DT nodes for the ICSSG0, ICSSG1 and ICSSG2 processor subsystems that are present on the K3 AM65x SoCs. The three ICSSGs are identical to each other for the most part, with the ICSSG2 supporting slightly enhanced features for supporting SGMII PRU Ethernet. Each ICSSG instance is represented by a PRUSS subsystem node. These nodes are enabled by default. The ICSSGs on K3 AM65x SoCs are super-sets of the PRUSS on the AM57xx/ 6AK2G SoCs except for larger Shared Data RAM and the lack of a PRU-ICSS crossbar. They include two auxiliary PRU cores called RTUs and few other additional sub-modules. The interrupt integration is also different on the K3 AM65x SoCs and are propagated through various SoC-level Interrupt Router and Interrupt Aggregator blocks. The AM65x SR2.0 SoCs have a revised ICSSG IP that is based off the subsequent IP used on J721E SoCs, and has two new auxiliary PRU cores called Tx_PRUs. The Tx_PRUs have 6 KB of IRAMs and leverage the same host interrupts as the regular PRU cores. The Broadside (BS) RAM within each core is also sized differently w.r.t SR1.0. The ICSSG subsystem node contains the entire address space. The various sub-modules of the ICSSG are represented as individual child nodes (so platform devices themselves) of the PRUSS subsystem node. These include the various PRU cores and the interrupt controller. All the Data RAMs are represented within a child node of its own named 'memories' without any compatible. The Real Time Media Independent Interface controllers (MII_RT and MII_G_RT), and the CFG sub-module are represented as syscon nodes. The ICSSG CFG module has clock muxes for IEP clock and CORE clock, these clk nodes are added under the CFG child node 'clocks'. The default parents for these mux clocks are also assigned. The DT nodes use all standard properties. The regs property in the PRU/RTU/Tx_PRU nodes define the addresses for the Instruction RAM, the Debug and Control sub-modules for that PRU core. The firmware for each PRU/RTU/Tx_PRU core is defined through a 'firmware-name' property. The default names for the firmware images for each PRU, RTU and Tx_PRU cores are defined as follows (these can be adjusted either in derivative board dts files or through sysfs at runtime if required): ICSSG0 PRU0 Core : am65x-pru0_0-fw ; PRU1 Core : am65x-pru0_1-fw ICSSG0 RTU0 Core : am65x-rtu0_0-fw ; RTU1 Core : am65x-rtu0_1-fw ICSSG0 Tx_PRU0 Core : am65x-txpru0_0-fw ; Tx_PRU1 Core : am65x-txpru0_1-fw ICSSG1 PRU0 Core : am65x-pru1_0-fw ; PRU1 Core : am65x-pru1_1-fw ICSSG1 RTU0 Core : am65x-rtu1_0-fw ; RTU1 Core : am65x-rtu1_1-fw ICSSG1 Tx_PRU0 Core : am65x-txpru1_0-fw ; Tx_PRU1 Core : am65x-txpru1_1-fw ICSSG2 PRU0 Core : am65x-pru2_0-fw ; PRU1 Core : am65x-pru2_1-fw ICSSG2 RTU0 Core : am65x-rtu2_0-fw ; RTU1 Core : am65x-rtu2_1-fw ICSSG2 Tx_PRU0 Core : am65x-txpru2_0-fw ; Tx_PRU1 Core : am65x-txpru2_1-fw Note: 1. The ICSSG nodes are all added as per the SR2.0 device. Any sub-module IP differences need to be handled within the driver using SoC device match logic or separate dts/overlay files (if needs to be supported) with the Tx_PRU nodes expected to be disabled at the minimum. 2. The ICSSG INTC on AM65x SoCs share 5, 6, 7 host interrupts with other processors, so use the 'ti,irqs-reserved' property in derivative board dts files _if_ any of them should not be handled by the host OS. 3. There are few more sub-modules like the Industrial Ethernet Peripherals (IEPs), MDIO, PWM, UART that do not have bindings and so will be added in the future. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20210304160712.8452-2-s-anna@ti.com
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#
b605d4f6 |
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11-Feb-2021 |
Jan Kiszka <jan.kiszka@siemens.com> |
arm64: dts: ti: k3-am65-main: Add device_type to pcie*_rc nodes This is demanded by the parent binding of ti,am654-pcie-rc, see Documentation/devicetree/bindings/pci/designware-pcie.txt. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/881dfd6c75423efce1d10261909939cd5ef19937.1613071976.git.jan.kiszka@siemens.com
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#
0cf73209 |
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15-Jan-2021 |
Grygorii Strashko <grygorii.strashko@ti.com> |
arm64: dts: ti: k3: mmc: fix dtbs_check warnings Now the dtbs_check produces below warnings sdhci@4f80000: clock-names:0: 'clk_ahb' was expected sdhci@4f80000: clock-names:1: 'clk_xin' was expected $nodename:0: 'sdhci@4f80000' does not match '^mmc(@.*)?$' Fix above warnings by updating mmc DT definitions to follow sdhci-am654.yaml bindings: - rename sdhci dt nodes to 'mmc@' - swap clk_xin/clk_ahb clocks, the clk_ahb clock expected to be defined first Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Suman Anna <s-anna@ti.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20210115193016.5581-1-grygorii.strashko@ti.com
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15ffd94a |
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27-Nov-2020 |
Sekhar Nori <nsekhar@ti.com> |
arm64: dts: ti: k3: squelch warning about lack of #interrupt-cells There are couple of places where INTA interrupt controller lacks #interrupt-cells property. This leads to warnings of the type: arch/arm64/boot/dts/ti/k3-j721e-main.dtsi:147.51-156.5: Warning (interrupt_provider): /bus@100000/main-navss/interrupt-controller@33d00000: Missing #interrupt-cells in interrupt provider when building TI device-tree files with W=2 warning level. Fix these. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Link: https://lore.kernel.org/r/20201127210128.9151-1-nsekhar@ti.com
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#
bfbf9be7 |
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13-Nov-2020 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: am65/j721e: Fix up un-necessary status set to "okay" for crypto The default state of a device tree node is "okay". There is no specific use of explicitly adding status = "okay" in the SoC dtsi. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Keerthy <j-keerthy@ti.com> Acked-by: Tero Kristo <t-kristo@ti.com> Cc: Keerthy <j-keerthy@ti.com> Link: https://lore.kernel.org/r/20201113211826.13087-4-nm@ti.com
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af03de2b |
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13-Nov-2020 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-am65*: Cleanup disabled nodes at SoC dtsi level The device tree standard states that when the status property is not present under a node, the okay value is assumed. There are many reasons for doing the same, the number of strings in the device tree, default power management functionality, etc. are a few of the reasons. In general, after a few rounds of discussions [1] there are few options one could take when dealing with SoC dtsi and board dts a. SoC dtsi provide nodes as a super-set default (aka enabled) state and to prevent messy board files, when more boards are added per SoC, we optimize and disable commonly un-used nodes in board-common.dtsi b. SoC dtsi disables all hardware dependent nodes by default and board dts files enable nodes based on a need basis. c. Subjectively pick and choose which nodes we will disable by default in SoC dtsi and over the years we can optimize things and change default state depending on the need. While there are pros and cons on each of these approaches, the right thing to do will be to stick with device tree default standards and work within those established rules. So, we choose to go with option (a). Lets cleanup defaults of am654 SoC dtsi before this gets more harder to cleanup later on and new SoCs are added. The dtb generated is identical with the patch and it is just cleanup to ensure we have a clean usage model NOTE: There is a known risk of omission that new board dts developers might miss reviewing both the board schematics in addition to all the DT nodes of the SoC when setting appropriate nodes status to disable or reserved in the board dts. This can expose issues in drivers that may not anticipate an incomplete node (example: missing appropriate board properties) being in an "okay" state. These cases are considered bugs and need to be fixed in the drivers as and when identified. [1] https://lore.kernel.org/linux-arm-kernel/20201027130701.GE5639@atomide.com/ Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Reviewed-by: Tony Lindgren <tony@atomide.com> Cc: Jyri Sarha <jsarha@ti.com> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: Peter Ujfalusi <peter.ujfalusi@ti.com> Cc: Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/r/20201113211826.13087-2-nm@ti.com
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cfbf17e6 |
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04-Nov-2020 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-am65*/j721e*: Fix unit address format error for dss node Fix the node address to follow the device tree convention. This fixes the dtc warning: <stdout>: Warning (simple_bus_reg): /bus@100000/dss@04a00000: simple-bus unit address format error, expected "4a00000" Fixes: 76921f15acc0 ("arm64: dts: ti: k3-j721e-main: Add DSS node") Fixes: fc539b90eda2 ("arm64: dts: ti: am654: Add DSS node") Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Jyri Sarha <jsarha@ti.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: Jyri Sarha <jsarha@ti.com> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> Link: https://lore.kernel.org/r/20201104222519.12308-1-nm@ti.com
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50301e88 |
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02-Nov-2020 |
Tomi Valkeinen <tomi.valkeinen@ti.com> |
arm64: dts: ti: k3-am65: mark dss as dma-coherent DSS is IO coherent on AM65, so we should mark it as such with 'dma-coherent' property in the DT file. Fixes: fc539b90eda2 ("arm64: dts: ti: am654: Add DSS node") Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Nikhil Devshatwar <nikhil.nd@ti.com> Cc: stable@vger.kernel.org # v5.8+ Link: https://lore.kernel.org/r/20201102134650.55321-1-tomi.valkeinen@ti.com
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9dcd17be |
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29-Aug-2020 |
Grygorii Strashko <grygorii.strashko@ti.com> |
arm64: dts: ti: k3-am65: ringacc: drop ti, dma-ring-reset-quirk Remove obsolete "ti,dma-ring-reset-quirk" Ringacc DT property. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20200829184139.15547-4-grygorii.strashko@ti.com
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e5c956c4 |
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03-Sep-2020 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-*: Fix up node_name_chars_strict warnings Building with W=2 throws up a bunch of easy to fixup warnings.. node_name_chars_strict is one of them.. Knock those out. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Suman Anna <s-anna@ti.com> Link: https://lore.kernel.org/r/20200903130015.21361-9-nm@ti.com
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dcccf770 |
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03-Sep-2020 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-*: Use generic pinctrl for node names Use pinctrl@ naming for nodes following standard conventions of device tree (section 2.2.2 Generic Names recommendation in [1]). [1] https://github.com/devicetree-org/devicetree-specification/tree/v0.3 Suggested-by: Suman Anna <s-anna@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Suman Anna <s-anna@ti.com> Link: https://lore.kernel.org/r/20200903130015.21361-6-nm@ti.com
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86e67b59 |
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03-Sep-2020 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-am65*: Use generic clock for syscon clock names serdes and ehrpwm_tbclk nodes should be using clock@ naming for nodes following standard conventions of device tree (section 2.2.2 Generic Names recommendation in [1]). [1] https://github.com/devicetree-org/devicetree-specification/tree/v0.3 Suggested-by: Suman Anna <s-anna@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Suman Anna <s-anna@ti.com> Acked-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20200903130015.21361-5-nm@ti.com
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91e5f404 |
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03-Sep-2020 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-am65*: Use generic gpio for node names Use gpio@ naming for nodes following standard conventions of device tree (section 2.2.2 Generic Names recommendation in [1]). [1] https://github.com/devicetree-org/devicetree-specification/tree/v0.3 Suggested-by: Suman Anna <s-anna@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Suman Anna <s-anna@ti.com> Link: https://lore.kernel.org/r/20200903130015.21361-4-nm@ti.com
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05e393c5 |
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03-Sep-2020 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-am65-main: Use lower case hexadecimal Device tree convention uses lower case a-f for hexadecimals. Fix the same. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Suman Anna <s-anna@ti.com> Link: https://lore.kernel.org/r/20200903130015.21361-3-nm@ti.com
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269a5641 |
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02-Aug-2020 |
Sekhar Nori <nsekhar@ti.com> |
arm64: dts: ti: k3-am65: restrict PCIe to Gen2 speed Per errata i2104 documented in AM65x device errata document (TI document number SPRZ452E, revised June 2019), Gen3 operation is not supported for both PCIe Root Complex and Endpoint modes of operation. See: https://www.ti.com/lit/er/sprz452e/sprz452e.pdf Restrict speed to Gen2 to address the errata. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20200802165356.10285-1-nsekhar@ti.com
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b366b240 |
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26-Aug-2020 |
Keerthy <j-keerthy@ti.com> |
arm64: dts: ti: k3-am6: Add crypto accelarator node Add crypto accelarator node for supporting hardware crypto algorithms, including SHA1, SHA256, SHA512, AES, 3DES, and AEAD suites. [t-kristo@ti.com: Modifications based on introduction of yaml binding] Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20200826082921.19143-2-t-kristo@ti.com
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6da45875 |
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06-Aug-2020 |
Lokesh Vutla <lokeshvutla@ti.com> |
arm64: dts: k3-am65: Update the RM resource types Update the ringacc and udma dt nodes to use the latest RM resource types similar to the ones used in k3-j721e dt nodes. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Acked-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20200806074826.24607-14-lokeshvutla@ti.com
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#
fef84512 |
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06-Aug-2020 |
Lokesh Vutla <lokeshvutla@ti.com> |
arm64: dts: k3-am65: ti-sci-inta/intr: Update to latest bindings Update the INTA and INTR dt nodes to the latest DT bindings. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Acked-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20200806074826.24607-13-lokeshvutla@ti.com
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#
6e6972f9 |
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26-Jun-2020 |
Grygorii Strashko <grygorii.strashko@ti.com> |
arm64: dts: ti: k3-am65/j721e-main: rename gic-its node to msi-controller The preferable name for gic-its is msi-controller, so rename it to fix dtbs_check warning: k3-j721e-common-proc-board.dt.yaml: interrupt-controller@1800000: gic-its@1820000: False schema does not allow {'compatible': ['arm,gic-v3-its'], 'reg': [[0, 25296896, 0, 65536]], 'socionext,synquacer-pre-its': [[16777216, 4194304]], 'msi-controller': True, '#msi-cells': [[1]]} Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
303d6f62 |
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12-Jul-2020 |
Alexander A. Klimov <grandmaster@al2klimov.de> |
arm64: dts: ti: k3-*: Replace HTTP links with HTTPS ones Rationale: Reduces attack surface on kernel devs opening the links for MITM as HTTPS traffic is much harder to manipulate. Deterministic algorithm: For each file: If not .svg: For each line: If doesn't contain `\bxmlns\b`: For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`: If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`: If both the HTTP and HTTPS versions return 200 OK and serve the same content: Replace HTTP with HTTPS. Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
d7600d07 |
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10-Jul-2020 |
Faiz Abbas <faiz_abbas@ti.com> |
arm64: dts: ti: k3-am65-main: Add support for sdhci1 Add support for the 2nd SDHCI controller on TI's AM654x SoCs. Although it supports upto SDR104 (100 MBps @ 200 MHz) speed mode, only enable support upto High Speed (25 MBps @ 50 MHz) for now. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
eac99d38 |
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19-May-2020 |
Faiz Abbas <faiz_abbas@ti.com> |
arm64: dts: ti: k3-am654-main: Update otap-del-sel values According to the latest AM65x Data Manual[1], a different output tap delay value is optimum for a given speed mode. Update these values. [1] http://www.ti.com/lit/gpn/am6526 Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
b3f7e95f |
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01-May-2020 |
Grygorii Strashko <grygorii.strashko@ti.com> |
arm64: dts: ti: k3-am65-main: add main navss cpts node Add DT node for Main NAVSS CPTS module. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
57dfcb5d |
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22-Mar-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
arm64: dts: ti: k3-am65-main: Add ehrpwm nodes Add DT nodes for all ehrpwm instances present on AM654 EVM. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
fc539b90 |
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21-Apr-2020 |
Jyri Sarha <jsarha@ti.com> |
arm64: dts: ti: am654: Add DSS node Add DSS node to k3-am65-main.dtsi with labels for board specific support and syscon node for oldi-io-ctrl. Signed-off-by: Jyri Sarha <jsarha@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
7ec378ed |
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12-Mar-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
arm64: dts: ti: k3-am65-main: Add DMA entries for main_spi0 Add DMA entry for main_spi0, that has SPI flash connected, for better throughput and reduced CPU load. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
a81e5442 |
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11-Mar-2020 |
Dave Gerlach <d-gerlach@ti.com> |
arm64: dts: ti: k3-am65: Add clocks to dwc3 nodes The TI sci-clk driver can scan the DT for all clocks provided by system firmware and does this by checking the clocks property of all nodes, so we must add this to the dwc3 nodes so USB clocks are available. Without this USB does not work with latest system firmware i.e. [ 1.714662] clk: couldn't get parent clock 0 for /interconnect@100000/dwc3@4020000 Fixes: cc54a99464ccd ("arm64: dts: ti: k3-am6: add USB suppor") Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Cc: stable@kernel.org Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
e98a0424 |
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11-Dec-2019 |
Benoit Parrot <bparrot@ti.com> |
arm64: dts: ti: k3-am65-main Add CAL node Add CAL dtsi node for AM654 device. Including proper power-domains and clock properties. Signed-off-by: Benoit Parrot <bparrot@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
9bcb631e |
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23-Jan-2020 |
Peter Ujfalusi <peter.ujfalusi@ti.com> |
arm64: dts: ti: k3-am654-main: Add McASP nodes Add the nodes for McASP 0-2 and keep them disabled because several required properties are not present as they are board specific. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
3d623054 |
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23-Jan-2020 |
Peter Ujfalusi <peter.ujfalusi@ti.com> |
arm64: dts: ti: k3-am65: DMA support Add the ringacc and udmap nodes for main and mcu NAVSS. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
12f20700 |
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23-Jan-2020 |
Peter Ujfalusi <peter.ujfalusi@ti.com> |
arm64: dts: ti: k3-am65-main: Move secure proxy under cbass_main_navss Secure proxy (NAVSS0_SEC_PROXY0) is part of the Navigator Subsystem. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
2daaa180 |
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23-Jan-2020 |
Peter Ujfalusi <peter.ujfalusi@ti.com> |
arm64: dts: ti: k3-am65-main: Correct main NAVSS representation NAVSS is a subsystem containing different IPs, it is not really a bus. Change the compatible from "simple-bus" to "simple-mfd" to reflect that. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
500f1ff9 |
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24-Jul-2019 |
Suman Anna <s-anna@ti.com> |
arm64: dts: ti: k3-am65-main: Add mailbox cluster nodes The AM65x Main NavSS block contains a Mailbox IP instance with multiple clusters. Each cluster is equivalent to an Mailbox IP instance on OMAP platforms. Add all the Mailbox clusters as their own nodes under the MAIN NavSS cbass_main_navss interconnect node instead of creating an almost empty parent node for the new K3 mailbox IP and the clusters as its child nodes. All these nodes are enabled by default in the base dtsi file, but any cluster that does not define any child sub-mailbox nodes should be disabled in the corresponding board dts files. NOTE: The NavSS only has a limited number of interrupts, so none of the interrupts generated by a Mailbox IP are added by default. Only the needed interrupts that are targeted towards the A53 GIC will have to be added later on in the board dts files alongside the corresponding sub-mailbox child nodes. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
389ce1a7 |
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08-Aug-2019 |
Suman Anna <s-anna@ti.com> |
arm64: dts: ti: k3-am65-main: Fix gic-its node unit-address The gic-its node unit-address has an additional zero compared to the actual reg value. Fix it. Fixes: ea47eed33a3f ("arm64: dts: ti: Add Support for AM654 SoC") Reported-by: Robert Tivy <rtivy@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
75f535d0 |
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22-Jul-2019 |
Suman Anna <s-anna@ti.com> |
arm64: dts: ti: k3-am65-main: Add hwspinlock node The Main NavSS block on AM65x SoCs contains a HwSpinlock IP instance that is similar to the IP on some OMAP SoCs. Add the DT node for this on AM65x SoCs. The node is present within the NavSS block, and is added as a child node under the cbass_main_navss interconnect node. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
c68272cb |
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29-Jul-2019 |
Lokesh Vutla <lokeshvutla@ti.com> |
arm64: dts: ti: k3-am654: Update the power domain cells Update the power-domain cells to 2 and mark all devices as exclusive. Main uart 0 is the debug console for based boards and it is used by different software entities like u-boot, atf, linux. So just mark main_uart0 as shared device for base board. Reviewed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
30eb8ea4 |
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29-May-2019 |
Kishon Vijay Abraham I <kishon@ti.com> |
arm64: dts: k3-am6: Add PCIe Endpoint DT node Add PCIe Endpoint DT node. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
cfa6437a |
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29-May-2019 |
Kishon Vijay Abraham I <kishon@ti.com> |
arm64: dts: k3-am6: Add PCIe Root Complex DT node Add PCIe Root Complex DT node. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
cedc255c |
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29-May-2019 |
Kishon Vijay Abraham I <kishon@ti.com> |
arm64: dts: k3-am6: Add SERDES DT node Add DT node for SERDES0 and SERDES1. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
1cbe04b0 |
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29-May-2019 |
Kishon Vijay Abraham I <kishon@ti.com> |
arm64: dts: k3-am6: Add mux-controller DT node required for muxing SERDES Add mux-controller DT node as a child node of scm_conf. This is required for muxing SERDES between USB, PCIe and ICSS2 SGMII. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
4b4ffc6e |
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29-May-2019 |
Kishon Vijay Abraham I <kishon@ti.com> |
arm64: dts: k3-am6: Add "socionext,synquacer-pre-its" property to gic_its GIC_ITS used in AM654 platform has the same configuration as that of GIC_ITS used in Socionext SoCs. Add "socionext,synquacer-pre-its" property to get PCI MSI working. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
980cc427 |
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06-Jun-2019 |
Keerthy <j-keerthy@ti.com> |
arm64: dts: ti: am6-main: Add gpio nodes Add gpio0/1 nodes under main domain. They have 96 and 90 gpios respectively and all are capable of generating banked interrupts. Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
cba9943c |
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02-May-2019 |
Lokesh Vutla <lokeshvutla@ti.com> |
arm64: dts: ti: k3-am654: Add interrupt controllers in main domain Main domain in AM654 has the following interrupt controller instances: - Main Domain GPIO Interrupt router connected to gpio in main domain. - Under the Main Domain Navigator Subsystem(NAVSS) - Main Navss Interrupt Router connected to main navss inta and mailboxes. - Main Navss Interrupt Aggregator connected to main domain UDMASS Add DT nodes for the above three interrupt controllers available in main domain. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
cc54a994 |
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05-Feb-2019 |
Roger Quadros <rogerq@ti.com> |
arm64: dts: ti: k3-am6: add USB support Adds support for USB0 and USB1 instances on the AM6 SoC. USB0 is limited to high-speed for now. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
7147f341 |
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05-Feb-2019 |
Jyri Sarha <jsarha@ti.com> |
arm64: dts: ti: am654: Add Main System Control Module node Main System control module support is added to the device tree to allow driver to access to their control module registers. Signed-off-by: Jyri Sarha <jsarha@ti.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
42d712a7 |
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11-Jan-2019 |
Roger Quadros <rogerq@ti.com> |
arm64: dts: ti: k3-am65: Add MSMC RAM node The AM65 SoC has 2MB MSMC RAM. Add this as a mmio-sram node so drivers can use it via genpool API. Following areas are marked reserved: - Lower 128KB for ATF - 64KB@0xf0000 for SYSFW - Upper 1MB for cache The reserved locations are subject to change at runtime by the bootloader. Cc: Nishanth Menon <nm@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Cc: Andrew F. Davis <afd@ti.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
5e00e9a2 |
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17-Jan-2019 |
Faiz Abbas <faiz_abbas@ti.com> |
arm64: dts: ti: k3-am654: Add Support for eMMC host controller Add support for the Secure Digital Host Controller Interface (SDHCI) present on TI's AM654 SOCs. It is compatible with eMMC5.1 Host Specifications. Enable only upto HS200 speed mode. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Acked-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
2cd7d393 |
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09-Dec-2018 |
Vignesh R <vigneshr@ti.com> |
arm64: dts: ti: k3-am654: Add McSPI DT nodes There are 3 instances of McSPI in MCU domain and 4 instances in Main domain. Add DT nodes for all McSPI instances present on AM654 SoC. Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
c484fc95 |
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11-Dec-2018 |
Vignesh R <vigneshr@ti.com> |
arm64: dts: ti: k3-am654: Populate power-domain property for UART nodes Populate power-domain property for UART nodes, this is required for Linux to enable UART clocks via PM calls. Without this UART instances not initialized by bootloader (like main_uart1) fails to work in Linux. Also, drop current-speed property from main_uart1 and main_uart2 nodes as these UARTs are not initialized before Linux boots up and current speed is unknown. Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
07c663b0 |
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07-Dec-2018 |
Vignesh R <vigneshr@ti.com> |
arm64: dts: ti: k3-am65-main: Add ECAP PWM node Add DT entry for ECAP0 PWM node present in main domain Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
19a1768f |
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12-Nov-2018 |
Vignesh R <vigneshr@ti.com> |
arm64: dts: ti: k3-am654-base-board: Add I2C nodes Add DT entries for I2C instances present in AM654 SoC. Signed-off-by: Vignesh R <vigneshr@ti.com> Acked-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
1d79b437 |
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12-Nov-2018 |
Tero Kristo <t-kristo@ti.com> |
arm64: dts: ti: k3-am65: Add pinctrl regions Add pinctrl regions for the main and wkup mmr. The range for main pinctrl region contains a gap at offset 0x2e4, and because of this, the pinctrl range is split into two sections. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Acked-by: Nishanth Menon <nm@ti.com>
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#
77ccbae4 |
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05-Sep-2018 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: am654: Add secure proxy instance for main domain Add secure proxy instance for Main domain Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
4201af25 |
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05-Sep-2018 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: am654: Add uart nodes Add uart nodes for AM654 device tree components. Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
3bc15720 |
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05-Sep-2018 |
Kishon Vijay Abraham I <kishon@ti.com> |
arm64: dts: ti: k3-am65: Change #address-cells and #size-cells of interconnect to 2 AM65 has two PCIe controllers and each PCIe controller has '2' address spaces one within the 4GB address space of the SoC and the other above the 4GB address space of the SoC (cbass_main) in addition to the register space. The size of the address space above the 4GB SoC address space is 4GB. These address ranges will be used by CPU/DMA to access the PCIe address space. In order to represent the address space above the 4GB SoC address space and to represent the size of this address space as 4GB, change address-cells and size-cells of interconnect to 2. Since OSPI has similar need in MCU Domain Memory Map, change address-cells and size-cells of cbass_mcu interconnect also to 2. Fixes: ea47eed33a3fe3d919 ("arm64: dts: ti: Add Support for AM654 SoC") Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Vignesh R <vigneshr@ti.com> Acked-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
ea47eed3 |
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26-Jun-2018 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: Add Support for AM654 SoC The AM654 SoC is a lead device of the K3 Multicore SoC architecture platform, targeted for broad market and industrial control with aim to meet the complex processing needs of modern embedded products. Some highlights of this SoC are: * Quad ARMv8 A53 cores split over two clusters * GICv3 compliant GIC500 * Configurable L3 Cache and IO-coherent architecture * Dual lock-step capable R5F uC for safety-critical applications * High data throughput capable distributed DMA architecture under NAVSS * Three Gigabit Industrial Communication Subsystems (ICSSG), each with dual PRUs and dual RTUs * Hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL * Centralized System Controller for Security, Power, and Resource management. * Dual ADCSS, eQEP/eCAP, eHRPWM, dual CAN-FD * Flash subsystem with OSPI and Hyperbus interfaces * Multimedia capability with CAL, DSS7-UL, SGX544, McASP * Peripheral connectivity including USB3, PCIE, MMC/SD, GPMC, I2C, SPI, GPIO See AM65x Technical Reference Manual (SPRUID7, April 2018) for further details: http://www.ti.com/lit/pdf/spruid7 NOTE: 1. AM654 is the first of the device variants, hence we introduce a generic am65.dtsi. 2. We indicate the proper bus topology, the ranges are elaborated in each bus segment instead of using the top level ranges to make sure that peripherals in each segment use the address space accurately. 3. Peripherals in each bus segment is maintained in a separate dtsi allowing for reuse in different bus segment representation from a different core such as R5. This is also the reason for maintaining a 1-1 address map in the ranges. 4. Cache descriptions follow the ARM64 standard description. Further tweaks may be necessary as we introduce more complex devices, but can be introduced in context of the device introduction. Reviewed-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Benjamin Fair <b-fair@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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