#
f051b6ac |
|
31-Jan-2024 |
Johan Jonker <jbx6244@gmail.com> |
arm64: dts: rockchip: fix rk3399 hdmi ports node Fix rk3399 hdmi ports node so that it matches the rockchip,dw-hdmi.yaml binding. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/a6ab6f75-3b80-40b1-bd30-3113e14becdd@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
f118d99e |
|
09-Jan-2024 |
Quentin Schulz <quentin.schulz@theobroma-systems.com> |
arm64: dts: rockchip: add spi controller aliases on rk3399 There are 6 SPI controllers on RK3399 and they are all numbered in the TRM, so let's add the appropriate aliases to the main DTSI so that any RK3399-based board doesn't need to define the aliases themselves to benefit from stable SPI indices in userspace. Cc: Quentin Schulz <foss+kernel@0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Link: https://lore.kernel.org/r/20240109-rk3399-spi-aliases-v1-1-2009e44e734a@theobroma-systems.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
b72633ba |
|
14-Dec-2023 |
Dragan Simic <dsimic@manjaro.org> |
arm64: dts: rockchip: Add cache information to the SoC dtsi for RK3399 Add missing cache information to the Rockchip RK3399 SoC dtsi. The specified values were derived by hand from the cache size specifications available from the RK3399 datasheet; for future reference, here's a brief summary: - Each Cortex-A72 core has 48 KB of L1 instruction cache and 32 KB of L1 data cache available, four-way set associative - Each Cortex-A53 core core has 32 KB of instruction cache and 32 KB of L1 data cache available, four-way set associative - The big (A72) cluster has 1 MB of unified L2 cache available - The little (A53) cluster has 512 KB of unified L2 cache available This patch allows /proc/cpuinfo and lscpu(1) to display proper RK3399 cache information, and it eliminates the following error in the kernel log: cacheinfo: Unable to detect cache hierarchy for CPU 0 While there, add a couple of somewhat useful comments, which may help a bit anyone going through the RK3399 SoC dtsi. Co-developed-by: Kyle Copperfield <kmcopper@danwin1210.me> Signed-off-by: Kyle Copperfield <kmcopper@danwin1210.me> Signed-off-by: Dragan Simic <dsimic@manjaro.org> Link: https://lore.kernel.org/r/be3cbcae5c40fa72a52845d30dcc66c847a98cfa.1702616304.git.dsimic@manjaro.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
5d90cb1e |
|
12-Dec-2023 |
Dragan Simic <dsimic@manjaro.org> |
arm64: dts: rockchip: Remove ethernet0 alias from the SoC dtsi for RK3399 Not all supported boards actually use the RK3399's built-in GMAC, while the SoC TRM and the datasheet don't define some standard numbering in this case. Thus, remove the ethernet0 alias from the RK3399 SoC dtsi file, and add the same alias back to the appropriate board dts(i) files. This is quite similar to the already performed migration of the mmcX aliases from the Rockchip SoC dtsi files to the board dts(i) files. Signed-off-by: Dragan Simic <dsimic@manjaro.org> Link: https://lore.kernel.org/r/20879826c01fb9ead71c339866846ea794669802.1702366958.git.dsimic@manjaro.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
99851344 |
|
02-Dec-2023 |
Johan Jonker <jbx6244@gmail.com> |
arm64: dts: rockchip: add gpio alias for gpio dt nodes Rockchip SoC TRM, SoC datasheet and board schematics always refer to the same gpio numbers - even if not all are used for a specific board. In order to not have to re-define them for every board add the aliases to SoC dtsi files. Co-developed-by: Jianqun Xu <jay.xu@rock-chips.com> Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Dragan Simic <dsimic@manjaro.org> Link: https://lore.kernel.org/r/56daeead-1d35-44bb-00c0-614b84a986de@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
f5680445 |
|
27-Nov-2023 |
Lukasz Luba <lukasz.luba@arm.com> |
arm64: dts: rockchip: Add dynamic-power-coefficient to rk3399 GPU Add dynamic-power-coefficient to the GPU node. That will create Energy Model for the GPU based on the coefficient and OPP table information. It will enable mechanism such as DTMP or IPA to work with the GPU DVFS. In similar way the Energy Model for CPUs in rk3399 is created, so both are aligned in power scale. The maximum power used from this coefficient is 1.5W at 600MHz. Signed-off-by: Lukasz Luba <lukasz.luba@arm.com> Link: https://lore.kernel.org/r/20231127081511.1911706-1-lukasz.luba@arm.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
35938c18 |
|
05-Nov-2023 |
Alex Bee <knaerzche@gmail.com> |
arm64: dts: rockchip: Expand reg size of vdec node for RK3399 Expand the reg size for the vdec node to include cache/performance registers the rkvdec driver writes to. Also add missing clocks to the related power-domain. Fixes: cbd7214402ec ("arm64: dts: rockchip: Define the rockchip Video Decoder node on rk3399") Signed-off-by: Alex Bee <knaerzche@gmail.com> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20231105233630.3927502-10-jonas@kwiboo.se Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
f57ef11e |
|
18-Oct-2023 |
Sascha Hauer <s.hauer@pengutronix.de> |
arm64: dts: rockchip: Always enable DFI on rk3399 the DFI unit can provide useful data for measuring DDR utilization and works without any configuration from the board, so enable it in the dtsi file directly. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.kernel.org/r/20231018061714.3553817-25-s.hauer@pengutronix.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
3975e72b |
|
12-Oct-2023 |
Christopher Obbard <chris.obbard@collabora.com> |
arm64: dts: rockchip: Add i2s0-2ch-bus-bclk-off pins to RK3399 Commit 0efaf8078393 ("arm64: dts: rockchip: add i2s0-2ch-bus pins on rk3399") introduced a pinctl for i2s0 in two-channel mode. Commit 91419ae0420f ("arm64: dts: rockchip: use BCLK to GPIO switch on rk3399") modified i2s0 to switch the corresponding pins off when idle. Although an idle pinctrl node was added for i2s0 in 8-channel mode, a similar idle pinctrl node for i2s0 in 2-channel mode was not added. Add it. Fixes: 91419ae0420f ("arm64: dts: rockchip: use BCLK to GPIO switch on rk3399") Signed-off-by: Christopher Obbard <chris.obbard@collabora.com> Link: https://lore.kernel.org/r/20231013114737.494410-2-chris.obbard@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
c0f0fb55 |
|
18-Apr-2023 |
Rick Wertenbroek <rick.wertenbroek@gmail.com> |
arm64: dts: rockchip: Add dtsi entry for RK3399 PCIe endpoint core Add dtsi entry for RK3399 PCIe endpoint core in the device tree. The status is "disabled" by default, so it will not be loaded unless explicitly chosen to. The RK3399 PCIe endpoit core should be enabled with the RK3399 PCIe root complex disabled because the RK3399 PCIe controller can only work one mode at the time, either in "root complex" mode or in "endpoint" mode. Tested-by: Damien Le Moal <dlemoal@kernel.org> Signed-off-by: Rick Wertenbroek <rick.wertenbroek@gmail.com> Link: https://lore.kernel.org/r/20230418074700.1083505-6-rick.wertenbroek@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
d94024bd |
|
22-Dec-2022 |
Johan Jonker <jbx6244@gmail.com> |
arm64: dts: rockchip: fix rk3399 dp node Use generic node name for rk3399.dtsi dp node. With the conversion of rockchip,analogix-dp.yaml a port@1 node is required, so add a node with label edp_out. Also restyle. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/f6008819-db9b-0944-3f5b-5522b7cd8a8d@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
f82fe7ad |
|
22-Dec-2022 |
Johan Jonker <jbx6244@gmail.com> |
arm64: dts: rockchip: fix rk3399 dsi node Use generic node name for rk3399.dtsi dsi node. With the conversion of rockchip,dw-mipi-dsi.yaml a port@1 node is required, so add a node with label mipi_out. Also restyle. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/1e019e9e-a8da-3d57-2770-f6b81bbbf591@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
0643bedf |
|
07-Feb-2023 |
Rob Herring <robh@kernel.org> |
arm64: dts: rockchip: Fix rk3399 GICv3 ITS node name The GICv3 ITS is an MSI controller, therefore its node name should be 'msi-controller'. Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230207234750.202154-1-robh@kernel.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
6f515b66 |
|
15-Dec-2022 |
Arnaud Ferraris <arnaud.ferraris@collabora.com> |
arm64: dts: rockchip: fix input enable pinconf on rk3399 When the input enable pinconf was introduced, a default drive-strength value of 2 was set for the pull up/down configs. However, this parameter is unneeded when configuring the pin as input, and having a single hardcoded value here is actually harmful: GPIOs on the RK3399 have various same drive-strength capabilities depending on the bank and port they belong to. As an example, trying to configure the GPIO4_PD3 pin as an input with pull-up enabled fails with the following output: [ 10.706542] rockchip-pinctrl pinctrl: unsupported driver strength 2 [ 10.713661] rockchip-pinctrl pinctrl: pin_config_set op failed for pin 155 (acceptable drive-strength values for this pin being 3, 6, 9 and 12) Let's drop the drive-strength property from all input pinconfs in order to solve this issue. Fixes: ec48c3e82ca3 ("arm64: dts: rockchip: add an input enable pinconf to rk3399") Signed-off-by: Arnaud Ferraris <arnaud.ferraris@collabora.com> Reviewed-by: Caleb Connolly <kc@postmarketos.org> Link: https://lore.kernel.org/r/20221215101947.254896-1-arnaud.ferraris@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
8c3313e8 |
|
11-Dec-2022 |
Corentin Labbe <clabbe@baylibre.com> |
arm64: dts: rockchip: use correct reset names for rk3399 crypto nodes The reset names does not follow the binding, use the correct ones. Fixes: 8c701fa6e38c ("arm64: dts: rockchip: rk3399: add crypto node") Signed-off-by: Corentin Labbe <clabbe@baylibre.com> Link: https://lore.kernel.org/r/20221212124423.1239748-1-clabbe@baylibre.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
8c701fa6 |
|
27-Sep-2022 |
Corentin Labbe <clabbe@baylibre.com> |
arm64: dts: rockchip: rk3399: add crypto node The rk3399 has a crypto IP handled by the rk3288 crypto driver so adds a node for it. Tested-by Diederik de Haas <didi.debian@cknow.org> Signed-off-by: Corentin Labbe <clabbe@baylibre.com> Link: https://lore.kernel.org/r/20220927075511.3147847-29-clabbe@baylibre.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
3a524712 |
|
19-Oct-2021 |
Hugh Cole-Baker <sigmaris@gmail.com> |
arm64: dts: rockchip: enable gamma control on RK3399 Define the memory region on RK3399 VOPs containing the gamma LUT at base+0x2000. Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com> Tested-by: Linus Heckemann <git@sphalerite.org> Link: https://lore.kernel.org/r/20211019215843.42718-4-sigmaris@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
91419ae0 |
|
08-Jul-2022 |
Judy Hsiao <judyhsiao@chromium.org> |
arm64: dts: rockchip: use BCLK to GPIO switch on rk3399 We discoverd that the state of BCLK on, LRCLK off and SD_MODE on may cause the speaker melting issue. Removing LRCLK while BCLK is present can cause unexpected output behavior including a large DC output voltage as described in the Max98357a datasheet. In order to: 1. prevent BCLK from turning on by other component. 2. keep BCLK and LRCLK being present at the same time This patch adjusts the device tree to allow BCLK to switch to GPIO func before LRCLK output, and switch back during LRCLK is output. Signed-off-by: Judy Hsiao <judyhsiao@chromium.org> Reviewed-by: Brian Norris <briannorris@chromium.org> Link: https://lore.kernel.org/r/20220708080726.4170711-1-judyhsiao@chromium.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
2d56af33 |
|
07-Jun-2022 |
Brian Norris <briannorris@chromium.org> |
arm64: dts: rockchip: Assign RK3399 VDU clock rate Before commit 9998943f6dfc ("media: rkvdec: Stop overclocking the decoder"), the rkvdec driver was forcing the VDU clock rate. After that commit, we rely on the default clock rate. That rate works OK on many boards, with the default PLL settings (CPLL is 800MHz, VDU dividers leave it at 400MHz); but some boards change PLL settings. Assign the expected default clock rate explicitly, so that the rate is consistent, regardless of PLL configuration. This was particularly broken on RK3399 Gru Scarlet systems, where the rk3399-gru-scarlet.dtsi assigns PLL_CPLL to 1.6 GHz, and so the VDU clock ends up at 800 MHz (twice the expected rate), and causes video artifacts and other issues. Note: I assign the clock rate in the clock controller instead of the vdec node, because there are multiple nodes that use this clock, and per the clock.yaml specification: Configuring a clock's parent and rate through the device node that consumes the clock can be done only for clocks that have a single user. Specifying conflicting parent or rate configuration in multiple consumer nodes for a shared clock is forbidden. Configuration of common clocks, which affect multiple consumer devices can be similarly specified in the clock provider node. Fixes: 9998943f6dfc ("media: rkvdec: Stop overclocking the decoder") Cc: <stable@vger.kernel.org> Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com> Link: https://lore.kernel.org/r/20220607141535.1.Idafe043ffc94756a69426ec68872db0645c5d6e2@changeid Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
bd820bc5 |
|
22-Apr-2022 |
Sascha Hauer <s.hauer@pengutronix.de> |
arm64: dts: rockchip: rename HDMI ref clock to 'ref' on rk3399 The reference clock for the HDMI controller has been renamed to 'ref', the previous 'vpll' name is only left for compatibility in the driver. Rename the clock to the new name. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Tested-by: Michael Riesch <michael.riesch@wolfvision.net> Link: https://lore.kernel.org/r/20220422072841.2206452-7-s.hauer@pengutronix.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
ec48c3e8 |
|
27-Mar-2022 |
Caleb Connolly <kc@postmarketos.org> |
arm64: dts: rockchip: add an input enable pinconf to rk3399 Add a pinconf to configure pins as input-enable. Signed-off-by: Caleb Connolly <kc@postmarketos.org> Link: https://lore.kernel.org/r/20220328005005.72492-5-kc@postmarketos.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
1b3f3685 |
|
08-Mar-2022 |
Lin Huang <hl@rock-chips.com> |
arm64: dts: rockchip: Add dfi and dmc nodes to rk3399 These are required to support DDR DVFS on RK3399 platforms. Change since Daniel's posting: reordered by unit address, per existing style Signed-off-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Gaƫl PORTAY <gael.portay@collabora.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Brian Norris <briannorris@chromium.org> Link: https://lore.kernel.org/r/20220308110825.v4.11.Ie97993621975c5463d7928a8646f3737c9f2921d@changeid Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
14fc86b9 |
|
29-Mar-2022 |
Johan Jonker <jbx6244@gmail.com> |
arm64: dts: rockchip: add clocks property to cru nodes rk3399 Add clocks property to rk3399 cru nodes to fix warnings like: 'clocks' is a dependency of 'assigned-clocks'. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20220329150742.22093-6-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
e03774ff |
|
29-Mar-2022 |
Johan Jonker <jbx6244@gmail.com> |
arm64: dts: rockchip: use generic node name for pmucru on rk3399 The node names should be generic, so fix this for the rk3399 pmucru node and rename it to "clock-controller". Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20220329150742.22093-5-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
4246d0ba |
|
15-Mar-2022 |
Shawn Lin <shawn.lin@rock-chips.com> |
arm64: dts: rockchip: Move drive-impedance-ohm to emmc phy on rk3399 drive-impedance-ohm is introduced for emmc phy instead of pcie phy. Fixes: fb8b7460c995 ("arm64: dts: rockchip: Define drive-impedance-ohm for RK3399's emmc-phy.") Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Link: https://lore.kernel.org/r/1647336426-154797-1-git-send-email-shawn.lin@rock-chips.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
2e8a8b59 |
|
26-Jan-2022 |
Sascha Hauer <s.hauer@pengutronix.de> |
arm64: dts: rockchip: reorder rk3399 hdmi clocks The binding specifies the clock order to "cec", "grf", "vpll". Reorder the clocks accordingly. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.kernel.org/r/20220126145549.617165-19-s.hauer@pengutronix.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
43f9699b |
|
01-Oct-2021 |
Daniel Lezcano <daniel.lezcano@linaro.org> |
arm64: dts: rockchip: Add idle cooling devices to rk3399 The thermal framework accepts now the cpu idle cooling device as an alternative when the cpufreq cooling device fails. Add the node in the DT so the cooling devices will be present and the platforms can extend the thermal zone definition to add them. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20211001161728.1729664-1-daniel.lezcano@linaro.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
ec3028e7 |
|
07-Oct-2021 |
Johan Jonker <jbx6244@gmail.com> |
arm64: dts: rockchip: change gpio nodenames Currently all gpio nodenames are sort of identical to there label. Nodenames should be of a generic type, so change them all. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20211007144019.7461-3-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
75dccea5 |
|
08-Sep-2021 |
Brian Norris <briannorris@chromium.org> |
arm64: dts: rockchip: add Coresight debug range for RK3399 Per Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt. This IP block can be used for sampling the PC of any given CPU, which is useful in certain panic scenarios where you can't get the CPU to stop cleanly (e.g., hard lockup). Reviewed-by: Leo Yan <leo.yan@linaro.org> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Brian Norris <briannorris@chromium.org> Link: https://lore.kernel.org/r/20210908111337.v2.3.Ibc87b4785709543c998cc852c1edaeb7a08edf5c@changeid Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
87543bb6 |
|
22-Aug-2021 |
Alex Bee <knaerzche@gmail.com> |
arm64: dts: rockchip: Re-add interrupt-names for RK3399's vpu Commit 53a05c8f6e8e ("arm64: dts: rockchip: remove interrupt-names from iommu nodes") intended to remove the interrupt-names property for mmu nodes, but it also removed it for the vpu node in rk3399.dtsi. That makes the driver fail probing currently. Fix this by re-adding the property for this node. Fixes: 53a05c8f6e8e ("arm64: dts: rockchip: remove interrupt-names from iommu nodes") Signed-off-by: Alex Bee <knaerzche@gmail.com> Link: https://lore.kernel.org/r/20210822115755.3171937-1-knaerzche@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
c349ae38 |
|
09-Feb-2021 |
Heiko Stuebner <heiko.stuebner@theobroma-systems.com> |
arm64: dts: rockchip: add isp1 node on rk3399 ISP1 is supplied by the tx1rx1 dphy, that is controlled from inside the dsi1 controller, so include the necessary phy-link for it. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Tested-by: Sebastian Fricke <sebastian.fricke@posteo.net> Acked-by: Helen Koike <helen.koike@collabora.com> Link: https://lore.kernel.org/r/20210210111020.2476369-7-heiko@sntech.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
f1400702 |
|
09-Feb-2021 |
Heiko Stuebner <heiko.stuebner@theobroma-systems.com> |
arm64: dts: rockchip: add cif clk-control pinctrl for rk3399 This enables variant a of the clkout signal for camera applications and also the cifclkin pinctrl setting. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Tested-by: Sebastian Fricke <sebastian.fricke@posteo.net> Acked-by: Helen Koike <helen.koike@collabora.com> Link: https://lore.kernel.org/r/20210210111020.2476369-6-heiko@sntech.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
8d47d12e |
|
09-Feb-2021 |
Heiko Stuebner <heiko.stuebner@theobroma-systems.com> |
arm64: dts: rockchip: add #phy-cells to mipi-dsi1 on rk3399 The dsi controller includes access to the dphy which might be used not only for dsi output but also for csi input on dsi1, so add the necessary #phy-cells to allow it to be used as phy. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Tested-by: Sebastian Fricke <sebastian.fricke@posteo.net> Acked-by: Helen Koike <helen.koike@collabora.com> Link: https://lore.kernel.org/r/20210210111020.2476369-5-heiko@sntech.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
5d54ea4e |
|
11-Jul-2021 |
Johan Jonker <jbx6244@gmail.com> |
arm64: dts: rockchip: remove interrupt-names from iommu nodes The iommu driver gets the interrupts by platform_get_irq(), so remove interrupt-names property from iommu nodes. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20210711143430.14347-2-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
8efe01b4 |
|
07-Jun-2021 |
Punit Agrawal <punitagrawal@gmail.com> |
arm64: dts: rockchip: Update RK3399 PCI host bridge window to 32-bit address memory The PCIe host bridge on RK3399 advertises a single 64-bit memory address range even though it lies entirely below 4GB. Previously the OF PCI range parser treated 64-bit ranges more leniently (i.e., as 32-bit), but since commit 9d57e61bf723 ("of/pci: Add IORESOURCE_MEM_64 to resource flags for 64-bit memory addresses") the code takes a stricter view and treats the ranges as advertised in the device tree (i.e, as 64-bit). The change in behaviour causes failure when allocating bus addresses to devices connected behind a PCI-to-PCI bridge that require non-prefetchable memory ranges. The allocation failure was observed for certain Samsung NVMe drives connected to RockPro64 boards. Update the host bridge window attributes to treat it as 32-bit address memory. This fixes the allocation failure observed since commit 9d57e61bf723. Reported-by: Alexandru Elisei <alexandru.elisei@arm.com> Link: https://lore.kernel.org/r/7a1e2ebc-f7d8-8431-d844-41a9c36a8911@arm.com Suggested-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Punit Agrawal <punitagrawal@gmail.com> Tested-by: Alexandru Elisei <alexandru.elisei@arm.com> Link: https://lore.kernel.org/r/20210607112856.3499682-5-punitagrawal@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
8c3d6425 |
|
01-Jun-2021 |
Johan Jonker <jbx6244@gmail.com> |
arm64: dts: rockchip: rename nodename for phy-rockchip-inno-usb2 The pattern: "^(|usb-|usb2-|usb3-|pci-|pcie-|sata-)phy(@[0-9a-f,]+)*$" in phy-provider.yaml has required "#phy-cells" for phy nodes. The "phy-cells" in rockchip-inno-usb2 nodes are located in subnodes. Rename the nodename to pattern "usb2phy@[0-9a-f]+$" to prevent notifications. make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=~/.local/lib/python3.5/site-packages/dtschema/schemas/ phy/phy-provider.yaml Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20210601164800.7670-5-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
837188d4 |
|
17-Apr-2021 |
Johan Jonker <jbx6244@gmail.com> |
arm64: dts: rockchip: add #power-domain-cells to power domain nodes Add #power-domain-cells to power domain nodes, because they are required by power-domain.yaml Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20210417112952.8516-9-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
148bbe29 |
|
17-Apr-2021 |
Elaine Zhang <zhangqing@rock-chips.com> |
arm64: dts: rockchip: Fix power-controller node names for rk3399 Use more generic names (as recommended in the device tree specification or the binding documentation) Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20210417112952.8516-8-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
a7ecfad4 |
|
25-Jan-2021 |
Johan Jonker <jbx6244@gmail.com> |
arm64: dts: rockchip: fix pinctrl sleep nodename for rk3399.dtsi A test with the command below aimed at powerpc generates notifications in the Rockchip arm64 tree. Fix pinctrl "sleep" nodename by renaming it to "suspend" for rk3399.dtsi make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/powerpc/sleep.yaml Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20210126110221.10815-2-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
ba0d527b |
|
12-Apr-2021 |
Johan Jonker <jbx6244@gmail.com> |
arm64: dts: rockchip: Remove clock-names from PWM nodes A test with the command below gives this error: /arch/arm64/boot/dts/rockchip/rk3368-evb-act8846.dt.yaml: pwm@ff680030: clock-names: ['pwm'] is too short Devices with only one PWM clock use it to both to derive the functional clock for the device and as the bus clock. The driver does not need "clock-names" to get a handle, so remove them all. make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/pwm/pwm-rockchip.yaml Signed-off-by: Johan Jonker <jbx6244@gmail.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
|
#
5dcbe7e3 |
|
24-Mar-2021 |
Heiko Stuebner <heiko.stuebner@theobroma-systems.com> |
arm64: dts: rockchip: move mmc aliases to board dts on rk3399 As suggested by Arnd Bergmann, the newly added mmc aliases should be board specific, so move them from the general dtsi to the individual boards. Suggested-by: Arnd Bergmann <arnd@kernel.org> Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Link: https://lore.kernel.org/r/20210324122235.1059292-7-heiko@sntech.de
|
#
6b5c5086 |
|
18-Dec-2020 |
Johan Jonker <jbx6244@gmail.com> |
arm64: dts: rockchip: add new watchdog compatible to rk3399.dtsi The watchdog compatible strings are suppose to be SoC orientated. In the more recently added Rockchip rk3399.dtsi file only the fallback string "snps,dw-wdt" is used, so add the new compatible string: "rockchip,rk3399-wdt", "snps,dw-wdt" make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20201218120534.13788-7-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
9e824449 |
|
20-Jan-2021 |
Robin Murphy <robin.murphy@arm.com> |
arm64: dts: rockchip: Remove bogus "amba" bus nodes The "amba" bus nodes wrapping all the DMA-330 nodes serve no useful purpose, and certainly bear no relation at all to the actual underlying interconnect topology. They appear to be cargo-cult copying from a design misstep in the very early days of FDT adoption on ARM, which was righted with the "arm,primecell" compatible, and the last trace of the idea finally purged by commit 2ef7d5f342c1 ("ARM, ARM64: dts: drop "arm,amba-bus" in favor of "simple-bus""). As such, they can simply be removed and the DMA-330 nodes fitted into the normal sort order. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Link: https://lore.kernel.org/r/131e0ea065109760ea3b59c4bb90cf4fac7826f7.1611186142.git.robin.murphy@arm.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
5b931210 |
|
22-Jan-2021 |
Johan Jonker <jbx6244@gmail.com> |
arm64: dts: rockchip: fix ranges property format for rk3399 pcie node A test with the command below gives for example this error: /arch/arm64/boot/dts/rockchip/rk3399-evb.dt.yaml: pcie@f8000000: ranges: 'oneOf' conditional failed, one must be fixed: The pcie ranges property is an array. The dt-check expects that each array item is wrapped with angle brackets, so fix that ranges property format for the rk3399 pcie node. make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=~/.local/lib/python3.5/site-packages/dtschema/ schemas/pci/pci-bus.yaml Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20210122171243.16138-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
e58061b5 |
|
17-Jan-2021 |
Johan Jonker <jbx6244@gmail.com> |
arm64: dts: rockchip: rename thermal subnodes for rk3399 A test with the command below gives for example this error: /arch/arm64/boot/dts/rockchip/rk3399-evb.dt.yaml: thermal-zones: 'cpu', 'gpu' do not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-]{1,12}-thermal$', 'pinctrl-[0-9]+' Rename Rockchip rk3399 thermal subnodes so that it ends with "-thermal" make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/ thermal/thermal-zones.yaml Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20210117150953.16475-3-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
bd3fd049 |
|
06-Dec-2020 |
Johan Jonker <jbx6244@gmail.com> |
arm64: dts: rockchip: add QoS register compatibles for rk3399 With the conversion of syscon.yaml minItems for compatibles was set to 2. Current Rockchip dtsi files only use "syscon" for QoS registers. Add Rockchip QoS compatibles for rk3399 to reduce notifications produced with: make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/mfd/syscon.yaml Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20201206103711.7465-3-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
94a5400f |
|
17-Jan-2021 |
Johan Jonker <jbx6244@gmail.com> |
arm64: dts: rockchip: remove interrupt-names property from rk3399 vdec node A test with the command below gives this error: /arch/arm64/boot/dts/rockchip/rk3399-evb.dt.yaml: video-codec@ff660000: 'interrupt-names' does not match any of the regexes: 'pinctrl-[0-9]+' The rkvdec driver gets it irq with help of the platform_get_irq() function, so remove the interrupt-names property from the rk3399 vdec node. make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/ media/rockchip,vdec.yaml Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20210117181653.24886-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
43f20b1c |
|
15-Aug-2020 |
Marc Zyngier <maz@kernel.org> |
arm64: dts: rockchip: Fix PCIe DT properties on rk3399 It recently became apparent that the lack of a 'device_type = "pci"' in the PCIe root complex node for rk3399 is a violation of the PCI binding, as documented in IEEE Std 1275-1994. Changes to the kernel's parsing of the DT made such violation fatal, as drivers cannot probe the controller anymore. Add the missing property makes the PCIe node compliant. While we are at it, drop the pointless linux,pci-domain property, which only makes sense when there are multiple host bridges. Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200815125112.462652-3-maz@kernel.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
97a0115c |
|
20-Oct-2020 |
Shunqian Zheng <zhengsq@rock-chips.com> |
arm64: dts: rockchip: add isp0 node for rk3399 RK3399 has two ISPs, but only isp0 was tested. Add isp0 node in rk3399 dtsi Verified with: make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/media/rockchip-isp1.yaml Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com> Signed-off-by: Helen Koike <helen.koike@collabora.com> Link: https://lore.kernel.org/r/20201020193850.1460644-9-helen.koike@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
9a9f6427 |
|
16-Nov-2020 |
Johan Jonker <jbx6244@gmail.com> |
arm64: dts: rockchip: rename sdhci nodename to mmc on rk3399 A test with the command below gives for example this error: /arch/arm64/boot/dts/rockchip/rk3399-evb.dt.yaml: sdhci@fe330000: $nodename:0: 'sdhci@fe330000' does not match '^mmc(@.*)?$' Fix it by renaming sdhci to mmc. make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/ mmc/arasan,sdhci.yaml Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20201116132311.8318-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
0011c6d1 |
|
04-Nov-2020 |
Markus Reichl <m.reichl@fivetechno.de> |
arm64: dts: rockchip: Assign a fixed index to mmc devices on rk3399 boards. Recently introduced async probe on mmc devices can shuffle block IDs. Pin them to fixed values to ease booting in environments where UUIDs are not practical. Use newly introduced aliases for mmcblk devices from [1]. [1] https://patchwork.kernel.org/patch/11747669/ Signed-off-by: Markus Reichl <m.reichl@fivetechno.de> Reviewed-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20201104162356.1251-1-m.reichl@fivetechno.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
505af918 |
|
29-Jun-2020 |
Sugar Zhang <sugar.zhang@rock-chips.com> |
arm64: dts: rockchip: Add 'arm,pl330-periph-burst' for dmac This patch Add the quirk to specify to use burst transfer for better compatible and higher performance. Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com> Link: https://lore.kernel.org/r/1593439935-68540-1-git-send-email-sugar.zhang@rock-chips.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
e4bfde13 |
|
03-Apr-2020 |
Shunqian Zheng <zhengsq@rock-chips.com> |
arm64: dts: rockchip: add rx0 mipi-phy for rk3399 Designware MIPI D-PHY, used for ISP0 in rk3399. Verified with: make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/phy/rockchip-mipi-dphy-rx0.yaml Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com> Signed-off-by: Helen Koike <helen.koike@collabora.com> Link: https://lore.kernel.org/r/20200403161538.1375908-9-helen.koike@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
2bc65fef |
|
24-May-2020 |
Johan Jonker <jbx6244@gmail.com> |
arm64: dts: rockchip: rename label and nodename pinctrl subnodes that end with gpio A test with the command below gives for example this error: arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dt.yaml: tsadc: tsadc-otp-gpio: {'phandle': [[90]], 'rockchip,pins': [[0, 6, 0, 123]]} is not of type 'array' 'gpio' is a sort of reserved nodename and should not be used for pinctrl in combination with 'rockchip,pins', so change nodes that end with 'gpio' to end with 'pin' or 'pins'. make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=~/.local/lib/python3.5/site-packages/ dtschema/schemas/gpio/gpio.yaml Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20200524160636.16547-2-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
2b99e619 |
|
28-Apr-2020 |
Johan Jonker <jbx6244@gmail.com> |
arm64: dts: rockchip: fix pd_tcpc0 and pd_tcpc1 node position on rk3399 The pd_tcpc0 and pd_tcpc1 nodes are currently a sub node of pd_vio. In the rk3399 TRM figure of the 'Power Domain Partition' and in the table of 'Power Domain and Voltage Domain Summary' these power domains are positioned directly under VD_LOGIC, so fix that in 'rk3399.dtsi'. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Caesar Wang <wxt@rock-chips.com> Link: https://lore.kernel.org/r/20200428203003.3318-2-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
84836ded |
|
28-Apr-2020 |
Johan Jonker <jbx6244@gmail.com> |
arm64: dts: rockchip: fix defines in pd_vio node for rk3399 A test with the command below gives for example this error: arch/arm64/boot/dts/rockchip/rk3399-evb.dt.yaml: pd_vio@15: 'pd_tcpc0@RK3399_PD_TCPC0', 'pd_tcpc1@RK3399_PD_TCPC1' do not match any of the regexes: '.*-names$', '.*-supply$', '^#.*-cells$', '^#[a-zA-Z0-9,+\\-._]{0,63}$', '^[a-zA-Z][a-zA-Z0-9,+\\-._]{0,63}$', '^[a-zA-Z][a-zA-Z0-9,+\\-._]{0,63}@[0-9a-fA-F]+(,[0-9a-fA-F]+)*$', '^__.*__$', 'pinctrl-[0-9]+' Fix error by replacing the wrong defines by the ones mentioned in 'rk3399-power.h'. make -k ARCH=arm64 dtbs_check Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20200428203003.3318-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
cbd72144 |
|
03-Apr-2020 |
Boris Brezillon <boris.brezillon@collabora.com> |
arm64: dts: rockchip: Define the rockchip Video Decoder node on rk3399 RK3399 has a Video decoder, define the node in the dtsi. We also add the missing power-domain in mmu node and enable the block. Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com> Link: https://lore.kernel.org/r/20200403221345.16702-6-ezequiel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
c604fd81 |
|
25-Apr-2020 |
Johan Jonker <jbx6244@gmail.com> |
arm64: dts: rockchip: swap interrupts interrupt-names rk3399 gpu node Dts files with Rockchip rk3399 'gpu' nodes were manually verified. In order to automate this process arm,mali-midgard.txt has been converted to yaml. In the new setup dtbs_check with arm,mali-midgard.yaml expects interrupts and interrupt-names values in the same order. Fix this for rk3399. make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/gpu/ arm,mali-midgard.yaml Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20200425143837.18706-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
190c7f6f |
|
26-Mar-2020 |
Chen-Yu Tsai <wens@csie.org> |
arm64: dts: rockchip: Rename dwc3 device nodes on rk3399 to make dtc happy The device tree compiler complains that the dwc3 nodes have regs properties but no matching unit addresses. Add the unit addresses to the device node name. While at it, also rename the nodes from "dwc3" to "usb", as guidelines require device nodes have generic names. Fixes: 7144224f2c2b ("arm64: dts: rockchip: support dwc3 USB for rk3399") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Link: https://lore.kernel.org/r/20200327030414.5903-7-wens@kernel.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
59782311 |
|
26-Mar-2020 |
Chen-Yu Tsai <wens@csie.org> |
arm64: dts: rockchip: drop #address-cells, #size-cells from rk3399 pmugrf node The device tree compiler gives the following warning: /syscon@ff100000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Since the pmygrf node only has an io-domains child node that has no reg property, remove the two properties from the pmugrf node to silence the warning. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Link: https://lore.kernel.org/r/20200327030414.5903-6-wens@kernel.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
77460b3d |
|
12-Mar-2020 |
Johan Jonker <jbx6244@gmail.com> |
arm64: dts: rockchip: remove clock-names property from 'generic-ohci' nodes A test with the command below gives for example this error: arch/arm64/boot/dts/rockchip/rk3328-evb.dt.yaml: usb@ff5d0000: 'clock-names' does not match any of the regexes: 'pinctrl-[0-9]+' 'clock-names' is not a valid property name for usb_host nodes with compatible string 'generic-ohci', so remove them. make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/usb/generic-ohci.yaml Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20200312171441.21144-4-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
6a92e52b |
|
12-Mar-2020 |
Johan Jonker <jbx6244@gmail.com> |
arm64: dts: rockchip: remove clock-names property from 'generic-ehci' nodes A test with the command below gives for example this error: arch/arm64/boot/dts/rockchip/rk3328-evb.dt.yaml: usb@ff5c0000: 'clock-names' does not match any of the regexes: 'pinctrl-[0-9]+' 'clock-names' is not a valid property name for usb_host nodes with compatible string 'generic-ehci', so remove them. make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/usb/generic-ehci.yaml Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20200312171441.21144-3-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
b2411bef |
|
02-Mar-2020 |
Johan Jonker <jbx6244@gmail.com> |
arm64: dts: add bus to rockchip amba nodenames A test with the command below gives for example this error: arch/arm64/boot/dts/rockchip/rk3399-evb.dt.yaml: amba: $nodename:0: 'amba' does not match '^(bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' AMBA is a open standard for the connection and management of functional blocks in a SoC. It's compatible with 'simple-bus', so fix this error by adding 'bus' to all Rockchip 'amba' nodes. make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=~/.local/lib/python3.5/site-packages/dtschema/ schemas/simple-bus.yaml Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20200302153047.17101-2-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
8a469ee3 |
|
18-Feb-2020 |
Carlos de Paula <me@carlosedp.com> |
arm64: dts: rockchip: Add txpbl node for RK3399/RK3328 Some rockchip SoCs like the RK3399 and RK3328 exhibit an issue where tx checksumming does not work with packets larger than 1498. The default Programmable Buffer Length for TX in these GMAC's is not suitable for MTUs higher than 1498. The workaround is to disable TX offloading with 'ethtool -K eth0 tx off rx off' causing performance impacts as it disables hardware checksumming. This patch sets snps,txpbl to 0x4 which is a safe number tested ok for the most popular MTU value of 1500. For reference, see https://lkml.org/lkml/2019/4/1/1382. Signed-off-by: Carlos de Paula <me@carlosedp.com> Link: https://lore.kernel.org/r/20200218221040.10955-1-me@carlosedp.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
3ef7c255 |
|
15-Jan-2020 |
Johan Jonker <jbx6244@gmail.com> |
arm64: dts: rockchip: rename dwmmc node names to mmc Current dts files with 'dwmmc' nodes are manually verified. In order to automate this process rockchip-dw-mshc.txt has to be converted to yaml. In the new setup rockchip-dw-mshc.yaml will inherit properties from mmc-controller.yaml and synopsys-dw-mshc-common.yaml. 'dwmmc' will no longer be a valid name for a node, so change them all to 'mmc' Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20200115185244.18149-2-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
36be9111 |
|
28-Nov-2019 |
Robin Murphy <robin.murphy@arm.com> |
arm64: dts: rockchip: Add GPU cooling device for RK3399 As for RK3288, now that we have a binding for the GPU we can hook up the missing cooling device for the thermal zone. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Link: https://lore.kernel.org/r/cb905e17526d846d6d35fb86fbd3c8ba4af4cdaf.1574974673.git.robin.murphy@arm.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
85dd7638 |
|
17-Sep-2019 |
Heiko Stuebner <heiko@sntech.de> |
arm64: dts: rockchip: add missing #msi-cells to rk3399 The rk3399 gic-its was missing the #msi-cells property as found by dt-schema checks, so add it. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20190917083625.25818-1-heiko@sntech.de
|
#
e6d237fd |
|
13-Jun-2019 |
Enric Balletbo i Serra <enric.balletbo@collabora.com> |
arm64: dts: rockchip: Update DWC3 modules on RK3399 SoCs As per binding documentation [1], the DWC3 core should have the "ref", "bus_early" and "suspend" clocks. As explained in the binding, those clocks are required for new platforms but not for existing platforms before commit fe8abf332b8f ("usb: dwc3: support clocks and resets for DWC3 core"). However, as those clocks are really treated as required, this ends with having some annoying messages when the "rockchip,rk3399-dwc3" is used: [ 1.724107] dwc3 fe800000.dwc3: Failed to get clk 'ref': -2 [ 1.731893] dwc3 fe900000.dwc3: Failed to get clk 'ref': -2 [ 2.495937] dwc3 fe800000.dwc3: Failed to get clk 'ref': -2 [ 2.647239] dwc3 fe900000.dwc3: Failed to get clk 'ref': -2 In order to remove those annoying messages, update the DWC3 hardware module node and add all the required clocks. With this change, both, the glue node and the DWC3 core node, have the clocks defined, but that's not really a problem and there isn't a side effect on do this. So, we can get rid of the annoying get clk error messages. [1] Documentation/devicetree/bindings/usb/dwc3.txt Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
95f231f8 |
|
04-Jun-2019 |
Daniel Lezcano <daniel.lezcano@linaro.org> |
arm64: dts: rockchip: Fix multiple thermal zones conflict in rk3399.dtsi Currently the common thermal zones definitions for the rk3399 assumes multiple thermal zones are supported by the governors. This is not the case and each thermal zone has its own governor instance acting individually without collaboration with other governors. As the cooling device for the CPU and the GPU thermal zones is the same, each governors take different decisions for the same cooling device leading to conflicting instructions and an erratic behavior. As the cooling-maps is about to become an optional property, let's remove the cpu cooling device map from the GPU thermal zone. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
c432a29d |
|
03-Jun-2019 |
Helen Koike <helen.koike@collabora.com> |
arm64: dts: rockchip: fix isp iommu clocks and power domain isp iommu requires wrapper variants of the clocks. noc variants are always on and using the wrapper variants will activate {A,H}CLK_ISP{0,1} due to the hierarchy. Tested using the pending isp patch set (which is not upstream yet). Without this patch, streaming from the isp stalls. Also add the respective power domain and remove the "disabled" status. Refer: RK3399 TRM v1.4 Fig. 2-4 RK3399 Clock Architecture Diagram RK3399 TRM v1.4 Fig. 8-1 RK3399 Power Domain Partition Signed-off-by: Helen Koike <helen.koike@collabora.com> Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
40a0dd42 |
|
06-Apr-2019 |
Katsuhiro Suzuki <katsuhiro@katsuster.net> |
arm64: dts: rockchip: fix cts, rts pin assign of UART3 for rk3399 This patch fixes pin assign of cts and rts signal of UART3. Currently GPIO3_C2 and C3 pins are assigned but TRM says that GPIO3_C0 and C1 are correct. Refer: RK3399 TRM v1.4 - Table 19-1 UART Interface Description Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
d64420e8 |
|
02-Apr-2019 |
Heiko Stuebner <heiko@sntech.de> |
arm64: dts: rockchip: bulk convert gpios to their constant counterparts Rockchip SoCs use 2 different numbering schemes. Where the gpio- controllers just count 0-31 for their 32 gpios, the underlying iomux controller splits these into 4 separate entities A-D. Device-schematics always use these iomux-values to identify pins, so to make mapping schematics to devicetree easier Andy Yan introduced named constants for the pins but so far we only used them on new additions. Using a sed-script created by Emil Renner Berthing bulk-convert the remaining raw gpio numbers into their descriptive counterparts and also gets rid of the unhelpful RK_FUNC_x -> x and RK_GPIOx -> x mappings: /rockchip,pins *=/bcheck b # to end of script :append-next-line N :check /^[^;]*$/bappend-next-line s/<RK_GPIO\([0-9]\) /<\1 /g s/<\([^ ][^ ]* *\)0 /<\1RK_PA0 /g s/<\([^ ][^ ]* *\)1 /<\1RK_PA1 /g s/<\([^ ][^ ]* *\)2 /<\1RK_PA2 /g s/<\([^ ][^ ]* *\)3 /<\1RK_PA3 /g s/<\([^ ][^ ]* *\)4 /<\1RK_PA4 /g s/<\([^ ][^ ]* *\)5 /<\1RK_PA5 /g s/<\([^ ][^ ]* *\)6 /<\1RK_PA6 /g s/<\([^ ][^ ]* *\)7 /<\1RK_PA7 /g s/<\([^ ][^ ]* *\)8 /<\1RK_PB0 /g s/<\([^ ][^ ]* *\)9 /<\1RK_PB1 /g s/<\([^ ][^ ]* *\)10 /<\1RK_PB2 /g s/<\([^ ][^ ]* *\)11 /<\1RK_PB3 /g s/<\([^ ][^ ]* *\)12 /<\1RK_PB4 /g s/<\([^ ][^ ]* *\)13 /<\1RK_PB5 /g s/<\([^ ][^ ]* *\)14 /<\1RK_PB6 /g s/<\([^ ][^ ]* *\)15 /<\1RK_PB7 /g s/<\([^ ][^ ]* *\)16 /<\1RK_PC0 /g s/<\([^ ][^ ]* *\)17 /<\1RK_PC1 /g s/<\([^ ][^ ]* *\)18 /<\1RK_PC2 /g s/<\([^ ][^ ]* *\)19 /<\1RK_PC3 /g s/<\([^ ][^ ]* *\)20 /<\1RK_PC4 /g s/<\([^ ][^ ]* *\)21 /<\1RK_PC5 /g s/<\([^ ][^ ]* *\)22 /<\1RK_PC6 /g s/<\([^ ][^ ]* *\)23 /<\1RK_PC7 /g s/<\([^ ][^ ]* *\)24 /<\1RK_PD0 /g s/<\([^ ][^ ]* *\)25 /<\1RK_PD1 /g s/<\([^ ][^ ]* *\)26 /<\1RK_PD2 /g s/<\([^ ][^ ]* *\)27 /<\1RK_PD3 /g s/<\([^ ][^ ]* *\)28 /<\1RK_PD4 /g s/<\([^ ][^ ]* *\)29 /<\1RK_PD5 /g s/<\([^ ][^ ]* *\)30 /<\1RK_PD6 /g s/<\([^ ][^ ]* *\)31 /<\1RK_PD7 /g s/<\([^ ][^ ]* *[^ ][^ ]* *\)0 /<\1RK_FUNC_GPIO /g s/<\([^ ][^ ]* *[^ ][^ ]* *\)RK_FUNC_\([1-9]\) /<\1\2 /g Suggested-by: Emil Renner Berthing <esmil@mailme.dk> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Katsuhiro Suzuki <katsuhiro@katsuster.net> Acked-by: Robin Murphy <robin.murphy@arm.com>
|
#
fb8b7460 |
|
21-Mar-2019 |
Christoph Muellner <christoph.muellner@theobroma-systems.com> |
arm64: dts: rockchip: Define drive-impedance-ohm for RK3399's emmc-phy. A previous patch introduced the property 'drive-impedance-ohm' for the RK3399's emmc phy node. This patch sets this value explicitly to the default value of 50 Ohm. Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
a3eec13b |
|
21-Mar-2019 |
Christoph Muellner <christoph.muellner@theobroma-systems.com> |
arm64: dts: rockchip: Disable DCMDs on RK3399's eMMC controller. When using direct commands (DCMDs) on an RK3399, we get spurious CQE completion interrupts for the DCMD transaction slot (#31): [ 931.196520] ------------[ cut here ]------------ [ 931.201702] mmc1: cqhci: spurious TCN for tag 31 [ 931.206906] WARNING: CPU: 0 PID: 1433 at /usr/src/kernel/drivers/mmc/host/cqhci.c:725 cqhci_irq+0x2e4/0x490 [ 931.206909] Modules linked in: [ 931.206918] CPU: 0 PID: 1433 Comm: irq/29-mmc1 Not tainted 4.19.8-rt6-funkadelic #1 [ 931.206920] Hardware name: Theobroma Systems RK3399-Q7 SoM (DT) [ 931.206924] pstate: 40000005 (nZcv daif -PAN -UAO) [ 931.206927] pc : cqhci_irq+0x2e4/0x490 [ 931.206931] lr : cqhci_irq+0x2e4/0x490 [ 931.206933] sp : ffff00000e54bc80 [ 931.206934] x29: ffff00000e54bc80 x28: 0000000000000000 [ 931.206939] x27: 0000000000000001 x26: ffff000008f217e8 [ 931.206944] x25: ffff8000f02ef030 x24: ffff0000091417b0 [ 931.206948] x23: ffff0000090aa000 x22: ffff8000f008b000 [ 931.206953] x21: 0000000000000002 x20: 000000000000001f [ 931.206957] x19: ffff8000f02ef018 x18: ffffffffffffffff [ 931.206961] x17: 0000000000000000 x16: 0000000000000000 [ 931.206966] x15: ffff0000090aa6c8 x14: 0720072007200720 [ 931.206970] x13: 0720072007200720 x12: 0720072007200720 [ 931.206975] x11: 0720072007200720 x10: 0720072007200720 [ 931.206980] x9 : 0720072007200720 x8 : 0720072007200720 [ 931.206984] x7 : 0720073107330720 x6 : 00000000000005a0 [ 931.206988] x5 : ffff00000860d4b0 x4 : 0000000000000000 [ 931.206993] x3 : 0000000000000001 x2 : 0000000000000001 [ 931.206997] x1 : 1bde3a91b0d4d900 x0 : 0000000000000000 [ 931.207001] Call trace: [ 931.207005] cqhci_irq+0x2e4/0x490 [ 931.207009] sdhci_arasan_cqhci_irq+0x5c/0x90 [ 931.207013] sdhci_irq+0x98/0x930 [ 931.207019] irq_forced_thread_fn+0x2c/0xa0 [ 931.207023] irq_thread+0x114/0x1c0 [ 931.207027] kthread+0x128/0x130 [ 931.207032] ret_from_fork+0x10/0x20 [ 931.207035] ---[ end trace 0000000000000002 ]--- The driver shows this message only for the first spurious interrupt by using WARN_ONCE(). Changing this to WARN() shows, that this is happening quite frequently (up to once a second). Since the eMMC 5.1 specification, where CQE and CQHCI are specified, does not mention that spurious TCN interrupts for DCMDs can be simply ignored, we must assume that using this feature is not working reliably. The current implementation uses DCMD for REQ_OP_FLUSH only, and I could not see any performance/power impact when disabling this optional feature for RK3399. Therefore this patch disables DCMDs for RK3399. Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Fixes: 84362d79f436 ("mmc: sdhci-of-arasan: Add CQHCI support for arasan,sdhci-5.1") Cc: stable@vger.kernel.org [the corresponding code changes are queued for 5.2 so doing that as well] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
97df3aa7 |
|
02-Mar-2019 |
Marc Zyngier <maz@kernel.org> |
arm64: dts: rockchip: Add capacity-dmips-mhz attributes to rk3399 The RK3399 has the interesting property to be a so called "big-little" system, where not all the CPUs are equal (the A53s are much weaker than the A72s). So far, we're not telling the OS that there is such a difference in processing capacity, and Linux assumes that they are equal. Too bad. Let's tell the OS about this by using the capacity-dmips-mhz property. The values used here are those used on the Juno platform, which is quite similar. This leads to the scheduler knowing that it can pack more tasks on the A72s, and leads to a better interactive experience. Tested-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
31af04cd |
|
14-Jan-2019 |
Rob Herring <robh@kernel.org> |
arm64: dts: Remove inconsistent use of 'arm,armv8' compatible string The 'arm,armv8' compatible string is only for software models. It adds little value otherwise and is inconsistently used as a fallback on some platforms. Remove it from those platforms. This fixes warnings generated by the DT schema. Reported-by: Michal Simek <michal.simek@xilinx.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will.deacon@arm.com> Acked-by: Antoine Tenart <antoine.tenart@bootlin.com> Acked-by: Nishanth Menon <nm@ti.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Chanho Min <chanho.min@lge.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Tero Kristo <t-kristo@ti.com> Acked-by: Wei Xu <xuwei5@hisilicon.com> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Acked-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Scott Branden <scott.branden@broadcom.com> Acked-by: Kevin Hilman <khilman@baylibre.com> Acked-by: Chunyan Zhang <zhang.lyra@gmail.com> Acked-by: Robert Richter <rrichter@cavium.com> Acked-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Acked-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
#
5cd4c31a |
|
30-Nov-2018 |
Ezequiel Garcia <ezequiel@collabora.com> |
arm64: dts: rockchip: add VPU device node for RK3399 Add the Video Processing Unit node for the RK3399 SoC. Also, fix the VPU IOMMU node, which was disabled and lacking its power domain property. Reviewed-by: Tomasz Figa <tfiga@chromium.org> Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
cdd46460 |
|
16-Nov-2018 |
Viresh Kumar <viresh.kumar@linaro.org> |
arm64: dts: rockchip: Add all CPUs in cooling maps Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures. Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations. Update cooling maps to include all devices affected by individual trip points. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
b0fe0f47 |
|
10-Oct-2018 |
Emil Renner Berthing <kernel@esmil.dk> |
arm64: dts: rockchip: add rk3399 SPI DMAs Add spi dma channels as specified by the rk3399 TRM. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Tested-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
91e75bde |
|
22-Aug-2018 |
Heiko Stuebner <heiko@sntech.de> |
arm64: dts: rockchip: add missing address and size cells for rk3399 mipi dsi DSI controllers are also the hosts of their dsi bus and therefore contain nodes describing the attached panels with their reg properties containing the virtual ids. The dsi controller nodes on rk3399 lacked the #address-cells and #size-cells for these subnodes, so add them. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
f888da16 |
|
24-Aug-2018 |
Tony Xie <tony.xie@rock-chips.com> |
arm64: dts: rockchip: Add idle-states to device tree for rk3399 Add idle-states for cpu and cluster sleep states. Signed-off-by: Tony Xie <tony.xie@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
5b64d061 |
|
09-Jul-2018 |
Enric Balletbo i Serra <enric.balletbo@collabora.com> |
arm64: dts: rockchip: remove deprecated Type-C PHY properties on rk3399 Commit 0fbc47d9e426 ("phy: rockchip-typec: deprecate some DT properties for various register fields.") deprecates some Rockchip Type-C properties. As these are now not needed, remove from the device tree file. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
b4102328 |
|
21-Jun-2018 |
Randy Li <ayaka@soulik.info> |
arm64: dts: rockchip: add some common pin-settings to rk3399 Those pins would be used by many boards. Signed-off-by: Randy Li <ayaka@soulik.info> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
4486baca |
|
16-Jun-2018 |
Heiko Stuebner <heiko@sntech.de> |
arm64: dts: rockchip: generalize rk3399 #sound-dai-cells The soc spdif and i2s controllers always only have one compontent, so always require #sound-dai-cells to be 0. Therefore there is no need to duplicate this property in individual boards. So move them to rk3399.dtsi. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
cc9b0918 |
|
24-May-2018 |
Viresh Kumar <viresh.kumar@linaro.org> |
arm64: dts: rockchip: Add missing cooling device properties for CPUs The cooling device properties, like "#cooling-cells" and "dynamic-power-coefficient", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can register a cooling device. Add such missing properties. Do minor rearrangement as well to keep ordering consistent. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
0d60d48c |
|
02-Jun-2018 |
Vicente Bergas <vicencb@gmail.com> |
arm64: dts: rockchip: connect hdmi sound in rk3399 Everything is in place and working, it only needed to be wired up. Signed-off-by: Vicente Bergas <vicencb@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
4ee99ceb |
|
14-Dec-2017 |
Klaus Goger <klaus.goger@theobroma-systems.com> |
arm64: dts: rockchip: use SPDX-License-Identifier Update all 64bit rockchip devicetree files to use SPDX-License-Identifiers. All devicetrees claim to be either GPL or X11 while the actual license text is MIT. Therefore we use MIT for the SPDX tag as X11 is clearly wrong. Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com> Acked-by: Brian Norris <briannorris@chromium.org> Acked-by: Matthias Brugger <mbrugger@suse.com> Acked-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
df3bcde7 |
|
23-Mar-2018 |
Jeffy Chen <jeffy.chen@rock-chips.com> |
arm64: dts: rockchip: add clocks in iommu nodes Add clocks in iommu nodes, since we are going to control clocks in rockchip iommu driver. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
bfdca173 |
|
14-Dec-2017 |
Enric Balletbo i Serra <enric.balletbo@collabora.com> |
arm64: dts: rockchip: add usb3-phy otg-port support for rk3399 Add the usb3 phyter for the USB3.0 OTG controller. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
e702e13f |
|
19-Mar-2018 |
Lin Huang <hl@rock-chips.com> |
arm64: dts: rockchip: assign clock rate for cpll child clocks on rk3399 These clocks do not assign default clock frequency, and use the default cru register value to get frequency, so if cpll increase frequency, these clocks also increase their frequency, that may exceed their signed off frequency. So assign default clock for them to avoid it. NOTE: on none of the boards currently in mainline do we expect CPLL to be anything other than 800 MHz, but some future boards might have it. It's still good to be explicit about the clock rates to make diffing against future boards easier and also to rely less on BIOS muxing. Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
3f7f3b0f |
|
11-Mar-2018 |
Shunqian Zheng <zhengsq@rock-chips.com> |
arm64: dts: rockchip: assign clock rate for ACLK_VIO on rk3399 The ACLK_VIO is a parent clock used by a several children, its suggested clock rate is 400MHz. Right now it gets 400MHz because it sources from CPLL(800M) and divides by 2 after reset. It's good not to rely on default values like this, so let's explicitly set it. NOTE: it's expected that at least one board may override cru node and set the CPLL to 1.6 GHz. On that board it will be very important to be explicit about aclk-vio being 400 MHz. Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
835a1d5c |
|
02-Mar-2018 |
Heiko Stuebner <heiko@sntech.de> |
Revert "arm64: dts: rockchip: add usb3-phy otg-port support for rk3399" This reverts commit c301b327aea898af558b2387252a2f5fc0117dee. While this works splendidly on rk3399-gru devices using the cros-ec extcon, other rk3399-based devices using the fusb302 or no power-delivery controller at all don't probe at all anymore, as the typec-phy currently always expects the extcon to be available and therefore defers probing indefinitly on these. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
2d3c2d56 |
|
13-Feb-2018 |
Chris Zhong <zyw@rock-chips.com> |
arm64: dts: rockchip: add cdn-dp node for rk3399. Add a node for the cdn DP controller which is embedded in the rk3399 SoC. Signed-off-by: Chris Zhong <zyw@rock-chips.com> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> [fixed whitespaces instead of tabs, dropped unnecessary address+size-cells and fixed the number of interrupt cells] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
0efaf807 |
|
03-Feb-2018 |
Klaus Goger <klaus.goger@theobroma-systems.com> |
arm64: dts: rockchip: add i2s0-2ch-bus pins on rk3399 Add pin definition for I2S0 if used as a 2-channel only bus. Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
ba2b043e |
|
08-Jan-2018 |
Shunqian Zheng <zhengsq@rock-chips.com> |
arm64: dts: rockchip: Add cif test clocks for rk3399 There are three pins can act as cif test clock for rk3399. They're sourced from 24M and output 24M by default and some boards may use them as camera 24M xvclk. Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
7b0390ea |
|
07-Feb-2018 |
Yakir Yang <kuankuan.y@gmail.com> |
arm64: dts: rockchip: introduce pclk_vio_grf in rk3399-eDP device node The pclk_vio_grf supply power for VIO GRF IOs, if it is disabled, driver would failed to operate the VIO GRF registers. The clock is optional but one of the side effects of don't have this clk is that the Samsung Chromebook Plus fails to recover display after a suspend/resume with following errors: rockchip-dp ff970000.edp: Input stream clock not detected. rockchip-dp ff970000.edp: Timeout of video streamclk ok rockchip-dp ff970000.edp: unable to config video Signed-off-by: Yakir Yang <ykk@rock-chips.com> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> [this should also fix display failures when building rockchip-drm as module] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
c301b327 |
|
14-Dec-2017 |
Enric Balletbo i Serra <enric.balletbo@collabora.com> |
arm64: dts: rockchip: add usb3-phy otg-port support for rk3399 Add the usb3 phyter for the USB3.0 OTG controller. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
b7e63d95 |
|
14-Dec-2017 |
Enric Balletbo i Serra <enric.balletbo@collabora.com> |
arm64: dts: rockchip: add reset property for dwc3 controllers on rk3399 After commit '06c47e6286d usb: dwc3: of-simple: Add support to get resets for the device' you can add the reset property to the dwc3 node, the reset is required for the controller to work properly, otherwise bind / unbind stress testing of the USB controller on rk3399 we'd often end up with lots of failures that looked like this: phy phy-ff800000.phy.9: phy poweron failed --> -110 dwc3 fe900000.dwc3: failed to initialize core dwc3: probe of fe900000.dwc3 failed with error -110 Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
9df8a2d9 |
|
14-Dec-2017 |
Enric Balletbo i Serra <enric.balletbo@collabora.com> |
arm64: dts: rockchip: add the aclk_usb3 clocks for USB3 on rk3399 The aclk_usb3 must be enabled to support USB3 for rk3399. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
a1bbaaa4 |
|
14-Dec-2017 |
Enric Balletbo i Serra <enric.balletbo@collabora.com> |
arm64: dts: rockchip: add pd_usb3 power-domain node for rk3399 Add the usb3 power-domain, its qos area and assign it to the usb device node. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
c856cb5d |
|
29-Nov-2017 |
Nickey Yang <nickey.yang@rock-chips.com> |
arm64: dts: rockchip: update mipi cells for RK3399 We might include additional ports in derivative device trees, so the 'port' node should have an address, and the parent 'ports' node needs /#{addres,size}-cells. Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com> Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
1df5d2ab |
|
29-Nov-2017 |
Nickey Yang <nickey.yang@rock-chips.com> |
arm64: dts: rockchip: add mipi_dsi1 support for rk3399 This patch adds the information for the secondary MIPI DSI controller, e.g., interrupts, grf, clocks, ports and so on. Mirrors the existing definition for dsi0. Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com> Signed-off-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
3813a10a |
|
29-Nov-2017 |
Brian Norris <briannorris@chromium.org> |
arm64: dts: rockchip: add rk3399 DSI0 reset We've documented this one already, but we didn't add it to the DTSI yet. Suggested-by: Nickey Yang <nickey.yang@rock-chips.com> Signed-off-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
ec5ccfd7 |
|
11-Oct-2017 |
Jacob Chen <jacob-chen@iotwrt.com> |
arm64: dts: rockchip: add RGA device node for RK3399 This patch add the RGA dt config of RK3399 SoC. Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
db2fd26d |
|
13-Oct-2017 |
Pierre-Hugues Husson <phh@phh.me> |
arm64: dts: rockchip: add the cec clk for dw-mipi-hdmi on rk3399 Add the HDMI CEC controller main clock coming from the CRU. Signed-off-by: Pierre-Hugues Husson <phh@phh.me> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
0bc15d85 |
|
26-Sep-2017 |
Nickey Yang <nickey.yang@rock-chips.com> |
arm64: dts: rockchip: add the grf clk for dw-mipi-dsi on rk3399 The clk of grf must be enabled before writing grf register for rk3399. Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com> [the grf clock is already part of the binding since march 2017] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
bb4e6ff0 |
|
18-Sep-2017 |
Nickey Yang <nickey.yang@rock-chips.com> |
arm64: dts: rockchip: Correct MIPI DPHY PLL clock on rk3399 There is a further gate in between the mipidphy reference clock and the actual ref-clock input to the dsi host, making the clock hirarchy look like clk_24m --> Gate11[14] --> clk_mipidphy_ref --> Gate21[0] --> clk_dphy_pll Fix the clock reference so that the whole clock subtree gets enabled when the dsi host needs it. Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com> [amended commit message] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
e9a60cac |
|
19-Jul-2017 |
Shawn Lin <shawn.lin@rock-chips.com> |
arm64: dts: rockchip: convert PCIe to use per-lane PHYs for rk3339 Convert all RK3399 platforms to use per-lane PHY model in order to save more power by idling unused lane(s). Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
|
#
ae4fdcca |
|
23-Jul-2017 |
Simon Xue <xxm@rock-chips.com> |
arm64: dts: rockchip: add more rk3399 iommu nodes Add VPU/VDEC/IEP/ISP0/ISP1 iommu nodes Signed-off-by: Simon Xue <xxm@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
617f4472 |
|
15-Aug-2017 |
Kever Yang <kever.yang@rock-chips.com> |
arm64: dts: rockchip: init rk3399 vop clock rates We need to init vop aclk and hclk incase the U-Boot does not do the initialize. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Mark Yao <mark.yao@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
1d5bcbbd |
|
17-Aug-2017 |
William Wu <william.wu@rock-chips.com> |
arm64: dts: rockchip: disable tx ipgap linecheck for rk3399 dwc3 RK3399 USB DWC3 controller has a issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. It's because that the inter-packet delay between the SSPLIT token to SETUP token is about 566ns, more then the USB spec requirement. This patch adds a quirk "snps,dis-tx-ipgap-linecheck-quirk" to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns. Signed-off-by: William Wu <william.wu@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
81e923dd |
|
31-Jul-2017 |
Jacob Chen <jacob-chen@iotwrt.com> |
arm64: dts: rockchip: add rk3399 hdmi nodes Add an hdmi node, and also add hdmi endpoints to vopb and vopl output port nodes. Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
d3f51f49 |
|
17-Jul-2017 |
Jacob Chen <jacob-chen@iotwrt.com> |
arm64: dts: rockchip: add rk3399 mipi nodes Add an mipi node, and also add mipi endpoints to vopb and vopl output port nodes. Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
f7a29e30 |
|
17-Jul-2017 |
Yakir Yang <kuankuan.y@gmail.com> |
arm64: dts: rockchip: add rk3399 edp nodes Add an edp node, and also add edp endpoints to vopb and vopl output port nodes. Signed-off-by: Yakir Yang <ykk@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
3cf04a4e |
|
17-Jul-2017 |
Elaine Zhang <zhangqing@rock-chips.com> |
arm64: dts: rockchip: add pd_edp node for rk3399 1. add pd node for RK3399 Soc 2. create power domain tree 3. add qos node for domain Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
fbd4cc0e |
|
17-Jul-2017 |
Mark Yao <markyao0591@gmail.com> |
arm64: dts: rockchip: Add rk3399 vop and display-subsystem Add devicetree nodes for rk3399 VOP (Video Output Processors), and the top level display-subsystem root node. Later patches add endpoints (eDP, HDMI, MIPI, etc) that attach to the VOPs' output ports. Signed-off-by: Mark Yao <mark.yao@rock-chips.com> Signed-off-by: Yakir Yang <ykk@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
45a995c0 |
|
25-Jul-2017 |
Caesar Wang <wxt@rock-chips.com> |
arm64: dts: rockchip: update dynamic-power-coefficient for rk3399 This patch updates the dynamic-power-coefficient for big cluster on rk3399 SoCs. The dynamic power consumption of the CPU is proportional to the square of the Voltage (V) and the clock frequency (f). The coefficient is used to calculate the dynamic power as below - Pdyn = dynamic-power-coefficient * V^2 * f Where Voltage is in uV, frequency is in MHz. As the following is the tested data on rk3399's big cluster. frequency(MHz) Voltage(V) Current(mA) Dynamic-power-coefficient 24 0.8 15 48 0.8 23 ~417 96 0.8 40 ~443 216 0.8 82 ~438 312 0.8 115 ~430 408 0.8 150 ~455 So the dynamic-power-coefficient average value is about 436. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
461a00bb |
|
02-Jul-2017 |
Shawn Lin <shawn.lin@rock-chips.com> |
arm64: dts: rockchip: kill pcie_clkreqn and pcie_clkreqnb for rk3399 Kill these two pinctrl reference totally from rk3399 as it never work indeed. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
68d19331 |
|
17-Jul-2017 |
Caesar Wang <wxt@rock-chips.com> |
arm64: dts: rockchip: add ARM Mali GPU node for RK3399 SoCs Add Mali GPU device tree node for the RK3399 SoCs, with devfreq opp table. RK3399 and RK3399-OP1 SoCs have a different recommendation table with gpu opp. Also, the ARM's mali driver found on https://developer.arm.com/products/software/mali-drivers/midgard-kernel. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
b0f2110a |
|
30-Jun-2017 |
Caesar Wang <wxt@rock-chips.com> |
arm64: dts: rockchip: add SdioAudio pd control for rk3399 The SdioAudio power domain includes the i2s/spdif/spi5/sdio. So this patch adds the pd control for rk3399 i2s/spdif/spi5/sdio, in order to save more power consumption. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
f4697bd7 |
|
23-Jun-2017 |
Brian Norris <briannorris@chromium.org> |
arm64: dts: rockchip: set rk3399 dynamic CPU power coefficients Provide the dynamic power coefficient of the big and little CPU clusters. These numbers are currently in use on the Samsung Chromebook Plus ("Kevin"). The power allocator thermal governor doesn't know how to do anything if it doesn't get power parameters from its cooling devices (in this case, CPUfreq). So this effectively enables the power-allocator governor. Signed-off-by: Brian Norris <briannorris@chromium.org> [set the property in each core node] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
6122308e |
|
27-Jun-2017 |
Klaus Goger <klaus.goger@theobroma-systems.com> |
arm64: dts: rockchip: fix typo in mmc pinctrl replace all occurrences of sdmcc with sdmmc in the arm64 rockchip devicetree files. Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
2eca8411 |
|
09-May-2017 |
Heiko Stuebner <heiko@sntech.de> |
arm64: dts: rockchip: add ethernet0 alias on rk3399 This is used by bootloaders to override the mac address in the devicetree if needed. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
81f66606 |
|
16-May-2017 |
Shawn Lin <shawn.lin@rock-chips.com> |
arm64: dts: rockchip: extent IORESOURCE_MEM_64 of PCIe for rk3399 Make full use of 32 regions and increase IORESOURCE_MEM_64 so that we could have more chance to support PCIe switch with more endpoints attached to our RC. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
d633becc |
|
16-May-2017 |
Shawn Lin <shawn.lin@rock-chips.com> |
arm64: dts: rockchip: extent bus-ranges of PCIe for rk3399 In order to support multiple hierarchy of PCIe buses, for instance, PCIe switch, we need to extent bus-ranges to as max as possible. We have 32 regions and could support up to 31 buses except bus 0 for our root bridge. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
b74a2e98 |
|
12-Apr-2017 |
Kever Yang <kever.yang@rock-chips.com> |
arm64: dts: rockchip: add pinctrl settings for some rk3399 peripherals Add pinctrl for sdio, sdmmc, pcie, spdif, hdmi. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
65f1e902 |
|
12-Apr-2017 |
Kever Yang <kever.yang@rock-chips.com> |
arm64: dts: rockchip: add some missing qos nodes on rk3399 Add qos setting reg for some peripheral like sd, usb, pcie. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
41b464ef |
|
19-Mar-2017 |
Shawn Lin <shawn.lin@rock-chips.com> |
arm64: dts: rockchip: fix PCIe domain number for rk3399 It's suggested to fix the domain number for all PCIe host bridges or not set it at all. However, if we don't fix it, the domain number will keep increasing ever when doing unbind/bind test, which makes the bus tree of lspci introduce pointless domain hierarchy. More investigation shows the domain number allocater of PCI doesn't consider the conflict of domain number if we have more than one PCIe port belonging to different domains. So once unbinding/binding one of them and keep others would going to overflow the domain number so that finally it will share the same domain as others, but actually it shouldn't. We should fix the domain number for PCIe or invent new indexing ID mechanisms. However it isn't worth inventing new indexing ID mechanisms personlly, Just look at how other Root Complex drivers did, for instance, broadcom and qualcomm, it seems fixing the domain number was more popular. So this patch gonna fix the domain number of PCIe for rk3399. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Tested-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
04dc7f62 |
|
17-Mar-2017 |
Heiko Stuebner <heiko@sntech.de> |
arm64: dts: rockchip: add rk3399 dw-mmc resets dw-mmc got its reset-properties specified, so add the softresets for it on the rk3399. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
|
#
7144224f |
|
09-Feb-2017 |
Brian Norris <briannorris@chromium.org> |
arm64: dts: rockchip: support dwc3 USB for rk3399 Add the dwc3 usb needed node information for rk3399. Signed-off-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
66aef3cb |
|
09-Feb-2017 |
Brian Norris <briannorris@chromium.org> |
arm64: dts: rockchip: sort rk3399-pcie by unit address f8000000 is less than all the other (top-level) unit addresses. Signed-off-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
8cbb59af |
|
09-Jan-2017 |
Xing Zheng <zhengxing@rock-chips.com> |
arm64: dts: rockchip: add rockchip,grf property for RK3399 PMUCRU/CRU The structure rockchip_clk_provider needs to refer the GRF regmap in somewhere, if the CRU node has not "rockchip,grf" property, calling syscon_regmap_lookup_by_phandle will return an invalid GRF regmap, and the MUXGRF type clock will be not supported. Therefore, we need to add them. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
59cf70be |
|
16-Dec-2016 |
Shawn Lin <shawn.lin@rock-chips.com> |
arm64: dts: rockchip: add aspm-no-l0s for rk3399 Per the discussion of bug fix[1], we now actually leaves the default clock choice for pcie phy is derived from 24MHz OSC to guarantee the least BER. So let's add aspm-no-l0s here and folks could delete this property from their dts. [1] https://patchwork.kernel.org/patch/9470519/ Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
712fa177 |
|
16-Dec-2016 |
Shawn Lin <shawn.lin@rock-chips.com> |
arm64: dts: rockchip: add max-link-speed for rk3399 Per the errata of TRM, rk3399 won't support gen2 from now on, so let's set max-link-speed to 1 in order not to doing training for gen2. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
b5d1c572 |
|
21-Dec-2016 |
William wu <wulf@rock-chips.com> |
arm64: dts: rockchip: add u2phy clock for ehci and ohci of rk3399 We found that the suspend process was blocked when it run into ehci/ohci module due to clk-480m of usb2-phy was disabled. The root cause is that usb2-phy suspended earlier than ehci/ohci (usb2-phy will be auto suspended if no devices plug-in). and the clk-480m provided by it was disabled if no module used. However, some suspend process related ehci/ohci are base on this clock, so we should refer it into ehci/ohci driver to prevent this case. The u2phy clock flow like this: === u2phy ________________ | | |-----> UTMI_CLK ---------> | EHCI | OSC_24M ---|---> PHY_PLL----|----| |________^_______| |-----> 480M_CLK ---|G|---> | USBPHY_480M_SRC| ----> USBPHY_480M for SoC | | GRF === Signed-off-by: William wu <wulf@rock-chips.com> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
8742466a |
|
01-Dec-2016 |
Brian Norris <briannorris@chromium.org> |
arm64: dts: rockchip: add rk3399 eDP HPD pinctrl We haven't enabled eDP support yet, but we might as well describe the pin now. Signed-off-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
647cea2e |
|
01-Dec-2016 |
Brian Norris <briannorris@chromium.org> |
arm64: dts: rockchip: add rk3399 thermal_zones phandle We're going to need to amend this table in board files. Signed-off-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
e6186820 |
|
04-Oct-2016 |
Brian Norris <briannorris@chromium.org> |
arm64: dts: rockchip: Arch counter doesn't tick in system suspend The "arm,no-tick-in-suspend" property was introduced to note implementations where the system counter does not quite follow the ARM specification that it "must be implemented in an always-on power domain". Particularly, RK3399's counter stops ticking when we switch from the 24MHz clock to the 32KHz clock in low-power suspend, so let's mark it as such. Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
|
#
fe7f2de1 |
|
07-Nov-2016 |
William Wu <wulf@rock-chips.com> |
arm64: dts: rockchip: add usb2-phy otg-port support for rk3399 Add otg-port nodes for both u2phy0 and u2phy1. The otg-port can be used for USB2.0 part of USB3.0 OTG controller. Signed-off-by: William Wu <wulf@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
1bc60bee |
|
09-Nov-2016 |
Elaine Zhang <zhangqing@rock-chips.com> |
arm64: dts: rockchip: add pd_sd power-domain node for rk3399 Add the sd power-domain, its qos area and assign it to the sdmmc device node. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Tested-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
a1907df2 |
|
09-Nov-2016 |
Elaine Zhang <zhangqing@rock-chips.com> |
arm64: dts: rockchip: add eMMC's power domain support for rk3399 Control power domain for eMMC via genpd to reduce power consumption. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Tested-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
2afc1db0 |
|
13-Nov-2016 |
Jeffy Chen <jeffy.chen@rock-chips.com> |
arm64: dts: rockchip: add gmac needed pclk for rk3399 pd This patch fixes that sometimes hang at start-up time of the system. As the below log: ... [ 11.136543] calling pm_genpd_debug_init+0x0/0x60 @ 1 [ 11.141602] initcall pm_genpd_debug_init+0x0/0x60 returned 0 after 11 usecs [ 11.148558] calling genpd_poweroff_unused+0x0/0x84 @ 1 <hang> In some cases, the rk3399 should turn off the gmac power domain to save power if some boards didn't register the gmac device node for rk3399. Then, rk3399 need to make sure the gmac's pclk enabled if we need operate the gmac power domain. (Due to the NOC had enabled always) Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
4d3222f7 |
|
10-Nov-2016 |
Shawn Lin <shawn.lin@rock-chips.com> |
arm64: dts: rockchip: add three new resets for rk3399 PCIe controller pm_rst, aclk_rst and pclk_rst should be controlled by driver, so we need to add these three resets for PCIe controller. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Heiko Stuebner <heiko@sntech.de>
|
#
c4959069 |
|
03-Nov-2016 |
Jaehoon Chung <jh80.chung@samsung.com> |
arm64: dts: rockchip: replace to "max-frequency" instead of "clock-freq-min-max" In drivers/mmc/core/host.c, there is "max-freqeuncy" property. It should be same behavior, So Use the "max-frequency" instead of "clock-freq-min-max". Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
0d326927 |
|
29-Oct-2016 |
Ziyuan Xu <xzy.xu@rock-chips.com> |
arm64: dts: rockchip: add cpu-id nvmem cell node for rk3399 There is a 'cpu-id' field in efuse, export it for other drivers reference. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
06ad4b2f |
|
07-Sep-2016 |
Chris Zhong <zyw@rock-chips.com> |
arm64: dts: rockchip: add powerdomain for typec on rk3399 The tcpc power domain will try to power up/down the power of Type-C PHY. Hence, we need control it in Type-C PHY driver with the pm_runtime helper. Signed-off-by: Chris Zhong <zyw@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
f606193a |
|
23-Aug-2016 |
Chris Zhong <zyw@rock-chips.com> |
arm64: dts: rockchip: add Type-C phy for RK3399 There are 2 Type-C phy on RK3399, they are almost same, except the address of register. They support USB3.0 Type-C and DisplayPort1.3 Alt Mode on USB Type-C. Register a phy, supply it to USB3 controller and DP controller. Signed-off-by: Chris Zhong <zyw@rock-chips.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
eb3a6a6a |
|
01-Sep-2016 |
Roger Chen <roger.chen@rock-chips.com> |
arm64: dts: rockchip: add the gmac needed node for rk3399 The RK3399 GMAC Ethernet Controller provides a complete Ethernet interface from processor to a Reduced Media Independent Interface (RMII) and Reduced Gigabit Media Independent Interface (RGMII) compliant Ethernet PHY. This patch adds the related needed device information. e.g.: interrupts, grf, clocks, pinctrl and so on. The full details are in [0]. [0]: Documentation/devicetree/bindings/net/rockchip-dwmac.txt Signed-off-by: Roger Chen <roger.chen@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
6840eb0d |
|
05-Sep-2016 |
Caesar Wang <wxt@rock-chips.com> |
arm64: dts: rockchip: support the pmu node for rk3399 This patch adds to enable the ARM Performance Monitor Units for rk3399. ARM cores often have a PMU for counting cpu and cache events like cache misses and hits. This uses the new interrupt-partition mechanism to allow the two pmu instances to use the per-cpu interrupt. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
210bbd38 |
|
05-Sep-2016 |
Caesar Wang <wxt@rock-chips.com> |
arm64: dts: rockchip: change all interrupts cells to 4 on rk3399 SoCs Add the interrupts cells value for 4, and the 4th cell is zero. Due to the doc[0] said:" the system requires describing PPI affinity, then the value must be at least 4" The 4th cell is a phandle to a node describing a set of CPUs this interrupt is affine to. The interrupt must be a PPI, and the node pointed must be a subnode of the "ppi-partitions" subnode. For interrupt types other than PPI or PPIs that are not partitionned, this cell must be zero. See the "ppi-partitions" node description below. [0]: Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt Signed-off-by: Caesar Wang <wxt@rock-chips.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
4a3a3d32 |
|
02-Sep-2016 |
Caesar Wang <wxt@rock-chips.com> |
arm64: dts: rockchip: add the tcpc for rk3399 power domain The tcpc is the Type C Port Controller and Type C Port Delivery (tcpd) is part of it, we haven't used them now, add it to save power consumption. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
b7ee3b27 |
|
01-Sep-2016 |
Finley Xiao <finley.xiao@rock-chips.com> |
arm64: dts: rockchip: add efuse0 device node for rk3399 Add a efuse0 node in the device tree for the ARM64 rk3399 SoC. Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
85aaa574 |
|
18-Aug-2016 |
Shawn Lin <shawn.lin@rock-chips.com> |
arm64: dts: rockchip: add the PCIe controller support for RK3399 This patch introduces PCIe support found on RK3399 platform, and specify phys phandle for it. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
29a0be1c |
|
18-Aug-2016 |
Shawn Lin <shawn.lin@rock-chips.com> |
arm64: dts: rockchip: add the PCIe PHY for RK3399 This patch adds PCIe node for RK3399 to support PCIe controller. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
d43c97a5 |
|
01-Sep-2016 |
Caesar Wang <wxt@rock-chips.com> |
arm64: dts: rockchip: add the gmac power domain on rk3399 This patch adds the gmac ppower-domain to save power consumption by letting the driver core handle the power-domain so we can save power on boards not needing Ethernet. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
a8bcaea7 |
|
01-Sep-2016 |
Douglas Anderson <dianders@chromium.org> |
arm64: dts: rockchip: Add pinctrl entry for 32k clock on rk3399 On some rk3399 boards GPIO0_A0 is hooked up to a 32 kHz clock. This can be used as the source for various clocks in the system. Add a pinmux so boards can get this pin properly configured. Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
bb4b6201 |
|
25-Aug-2016 |
Shunqian Zheng <zhengsq@rock-chips.com> |
arm64: dts: rockchip: set to CCI clock of RK3399 to 600M Per testing, this can reduce the memory latency and d8 gets better scores. Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
0895b3a8 |
|
26-Aug-2016 |
Xing Zheng <zhengxing@rock-chips.com> |
arm64: dts: rockchip: fix the address map for WDT0 and WDT1 Due to incorrect description in the TRM, the WDTs base address should be fixed and swap them like this: WDT0 - 0xff848000 WDT1 - 0xff840000 And, it is right that only WDT0 can generate global software reset. We will update the TRM to fix it. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
fe996215 |
|
27-Jul-2016 |
Caesar Wang <wxt@rock-chips.com> |
arm64: dts: rockchip: add the saradc for rk3399 This patch adds saradc needed information on rk3399 SoCs. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
103e9f85 |
|
22-Jul-2016 |
Frank Wang <frank.wang@rock-chips.com> |
arm64: dts: rockchip: add usb2-phy support for rk3399 Add usb2-phy nodes and specify phys phandle for ehci. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
807a2371 |
|
04-Jul-2016 |
Elaine Zhang <zhangqing@rock-chips.com> |
arm64: dts: rockchip: add the power domain node for rk3399 In order to meet low power requirements, a power management unit (PMU) is designed for controlling power resources in RK3399. The RK3399 PMU is dedicated for managing the power of the whole chip. 1. add pd node for RK3399 Soc 2. create power domain tree 3. add qos node for domain From the DT/binds and driver can get more detail information: The driver: drivers/soc/rockchip/pm_domains.c The document: Documentation/devicetree/bindings/soc/rockchip/power_domain.txt Note: As the TRM lists many voltage domains and power domains, then this patch adds some domains for driver. Due to some domains (e.g. emmc, usb, core)...We can't turned off it on bootup, or says some device driver can't handle the power domain enough. Maybe We will add more other domains in the future or later. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-rockchip@lists.infradead.org Cc: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
1e8567d5 |
|
16-Jun-2016 |
Huang Tao <huangtao@rock-chips.com> |
arm64: dts: rockchip: Add rktimer device node for rk3399 Add a 'rktimer' node in the device treee for the ARM64 rk3399 SoC. Signed-off-by: Huang Tao <huangtao@rock-chips.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Heiko Stuebner <heiko@sntech.de> Tested-by: Jianqun Xu <jay.xu@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
|
#
5d26ad9c |
|
14-Jun-2016 |
Douglas Anderson <dianders@chromium.org> |
arm64: dts: rockchip: add ap_pwroff and ddrio_pwroff pins for rk3399 There are two sleep related pins on rk3399: ap_pwroff and ddrio_pwroff. Let's add the definition of these two pins to rk3399's main dtsi file so that boards can use them. These two pins are similar to the global_pwroff and ddrio_pwroff pins in rk3288 and are expected to be used in the same way: boards will likely want to configure these pinctrl settings in their global pinctrl hog list. Note that on rk3288 there were two additional pins in the "sleep" section: "ddr0_retention" and "ddr1_retention". On rk3288 designs these pins appeared to actually route from rk3288 back to rk3288. Presumably on rk3399 this is simply not needed since the pins don't appear to exist there. Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
ed388cdd |
|
20-Jun-2016 |
Douglas Anderson <dianders@chromium.org> |
arm64: dts: rockchip: Provide emmcclk to PHY for rk3399 Previous changes in this series allowed exposing the card clock from the rk3399 SDHCI device and allowed consuming the card clock in the rk3399 eMMC PHY. Hook things up in the main rk3399 dtsi file. Signed-off-by: Douglas Anderson <dianders@chromium.org> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
64e3481c |
|
20-Jun-2016 |
Douglas Anderson <dianders@chromium.org> |
arm64: dts: rockchip: Add soc-ctl-syscon to sdhci for rk3399 On rk3399 we'd like to be able to properly set corecfg registers in the Arasan SDHCI component. Specify the syscon to enable that. Signed-off-by: Douglas Anderson <dianders@chromium.org> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
69e5a8fe |
|
16-May-2016 |
David Wu <david.wu@rock-chips.com> |
arm64: dts: rockchip: add i2c nodes for rk3399 We've got 9 (count em!) i2c controllers on rk3399, some of which are in the PMU power domain and some of which are normal peripherals. Add them all to the main rk3399 dtsi file so future patches can turn them on in the board dts files. Note: by default we try to set the i2c clock rate to 200 MHz so that we can achieve good i2c functional clock rates. 200 MHz gives us the ability to make very close to 100 kHz / 400 kHz / 1 MHz rates. If boards want to tune clock rates further they can always override. Possibly boards could want to tune this if: - they wanted to save an infinitesimal amount of power and they knew their i2c bus was slow anyway. Since we gate the functional clock when the i2c bus is not active, power savings would only be while i2c transfers were happening and probably won't be very big anyway. - they wanted to eek out a bit more speed by carefully tuning the source clock to make divisions work out perfectly, accounting for the rise / fall time measured on an actual board. Note also that we still request 200 MHz for the PMU i2c busses even though we expect that we won't make that exactly (currently PPLL is 676 MHz which gives us 169 MHz). Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> [dianders: wrote desc; put in assigned-clocks; reordered nodes] Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
95c27ba7 |
|
25-May-2016 |
Caesar Wang <wxt@rock-chips.com> |
arm64: dts: rockchip: add thermal nodes for rk3399 SoCs This adds thermal zone and tsadc nodes to rk3399 dtsi, rk3399 thermal data is including the cpu and gpu sensor zone node. The thermal zone node is the node containing all the required info for describing a thermal zone, including its cooling device bindings. The thermal zone node must contain, apart from its own properties, one sub-node containing trip nodes and one sub-node containing all the zone cooling maps. The following is the parameter is introduced: * polling-delay: The maximum number of milliseconds to wait between polls * polling-delay-passive: The maximum number of milliseconds to wait between polls when performing passive cooling. * trips: A sub-node which is a container of only trip point nodes required to describe the thermal zone. * cooling-maps: A sub-node which is a container of only cooling device map nodes, used to describe the relation between trips and cooling devices. * cooling-device: A phandle of a cooling device with its specifier, referring to which cooling device is used in this cooling specifier binding. In the cooling specifier, the first cell is the minimum cooling state and the second cell is the maximum cooling state used in this map. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
15b7cc78 |
|
29-May-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
arm64: dts: drop "arm,amba-bus" in favor of "simple-bus" part 2 Tree-wide replacement was done by commit 2ef7d5f342c1 (ARM, ARM64: dts: drop "arm,amba-bus" in favor of "simple-bus"), but we have some new users of "arm,amba-bus" at Linux 4.7-rc1. Eliminate them now. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Chanho Min <chanho.min@lge.com> Signed-off-by: Olof Johansson <olof@lixom.net>
|
#
6d0e3a45 |
|
21-May-2016 |
Heiko Stuebner <heiko@sntech.de> |
arm64: dts: rockchip: add rk3399 io-domain core nodes Add the core io-domain nodes to grf and pmugrf which individual boards than just have to enable and add the necessary supplies to. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
b4e87c09 |
|
13-May-2016 |
Brian Norris <briannorris@chromium.org> |
arm64: dts: rockchip: add sdhci/emmc for rk3399 Add description for the SDHCI v5.1 eMMC controller on rk3399. Fix it to 200 MHz, to support all supported timing modes. Note that 'rockchip,rk3399-sdhci-5.1' is not documented; we presumably have a compliant Arasan controller, but let's have a rockchip property as the canonical backup/precautionary measure. Per Heiko's previous suggestion, let's not clutter the arasan doc with it. Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
16759262 |
|
13-May-2016 |
Brian Norris <briannorris@chromium.org> |
arm64: dts: rockchip: make rk3399's grf a "simple-mfd" Per the examples in Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt, we need the grf node to be a simple-mfd in order to properly enumerate child devices like our eMMC PHY. Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> [directly mimic for the pmugrf, which will need the same change later and there is no need to pollute commit history with another patch] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
a09906cd |
|
13-May-2016 |
Xing Zheng <zhengxing@rock-chips.com> |
arm64: dts: rockchip: assign default rates for core rk3399 clocks These clocks are all core clocks used by many blocks/peripherals, many of whose drivers don't set their clock rates at all. Let's assign reasonable default clock rates for these core clocks, so that these peripherals get something reasonable by default, and also so that if child devices want to select a clock rate themselves, their muxes have some reasonable parent clock rates to branch off of (rather than just the boot-time defaults). This helps the eMMC PHY, for one, to get a reasonable ACLK rate. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
#
f048b9a4 |
|
27-Apr-2016 |
Jianqun Xu <jay.xu@rock-chips.com> |
arm64: dts: rockchip: add core dtsi file for RK3399 SoCs This patch adds core dtsi file for Rockchip RK3399 SoCs. The RK3399 has big/little architecture, which needs a separate node for the PMU of each microarchitecture, for now it missing the pmu node since the old one could not work well. Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Tested-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|