arm64: dts: qcom: sm8350: Add PCIe bridge node

On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-4-1eb790c53e43@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sm8350: Add interconnects to UFS

To ensure that UFS doesn't get disconnected from NoC, add interconnect properties
to the UFS controller.

Fixes: 59c7cf814783 ("arm64: dts: qcom: sm8350: Add UFS nodes")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240313-sm8350-ufs-icc-v1-1-73fa2da99779@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: replace underscores in node names

Underscores should not be used in node names (dtc with W=2 warns about
them), so replace them with hyphens.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20240213145124.342514-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sm8350: Fix UFS PHY clocks

QMP PHY used in SM8350 requires 3 clocks:

* ref - 19.2MHz reference clock from RPMh
* ref_aux - Auxiliary reference clock from GCC
* qref - QREF clock from GCC

While at it, let's move 'clocks' property before 'clock-names' to match
the style used commonly.

Fixes: 59c7cf814783 ("arm64: dts: qcom: sm8350: Add UFS nodes")
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-15-58a49d2f4605@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: split PCIe interrupt-names entries per lines

Other PCIe nodes in SM8250 and SM8350 have one interrupt name per
line, so adjust PCIe0 to match the style.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240126-b4-dt-bindings-pci-qcom-split-dts-v2-7-0bb067f73adb@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sm8350: describe all PCI MSI interrupts

Each group of MSI interrupts is mapped to the separate host interrupt.
Describe each of interrupts in the device tree for PCIe hosts. Not
tested on hardware.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240126-b4-dt-bindings-pci-qcom-split-dts-v2-3-0bb067f73adb@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sm8350: Hook up GPU cooling device

In order to allow for throttling the GPU, hook up the cooling device
to the respective thermal zones. Also, update the trip point label
to be more telling, while at it.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240102-topic-gpu_cooling-v1-9-fda30c57e353@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: Fix hs_phy_irq for non-QUSB2 targets

On non-QUSB2 targets (like the ones that use femto phys, M31 phy, eusb2
phy), many of the QCOM DTs are missing the IRQ for either hs_phy_irq or
pwr_event. In one case, the hs_phy_irq was incorrectly defined with the
latter's IRQ number. Since the DT must describe the hw whether or not
the driver uses these interrupts, fix and add the missing entries in order
to describe the HW completely and accurately.

Also modify order of interrupts in accordance to bindings update.

Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
Link: https://lore.kernel.org/r/20240125185921.5062-3-quic_kriskura@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: Use "pcie" as the node name instead of "pci"

Qcom SoCs doesn't support the legacy PCI, but only PCIe. So use the correct
node name for the controller instances.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20231206135540.17068-3-manivannan.sadhasivam@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sm8350: switch UFS QMP PHY to new style of bindings

Change the UFS QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes).

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20231205032552.1583336-9-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sm8350: Fix remoteproc interrupt type

In a similar vein to
https://lore.kernel.org/lkml/20220530080842.37024-3-manivannan.sadhasivam@linaro.org/,
the remote processors on sm8350 fail to initialize with the 'correct'
(i.e., specified in downstream) IRQ type. Change this to EDGE_RISING.

Signed-off-by: Nia Espera <nespera@igalia.com>
Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231111-nia-sm8350-for-upstream-v4-4-3a638b02eea5@igalia.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sm8350: Fix DMA0 address

DMA0 node downstream is specified at 0x900000, so fix the typo. Without
this, enabling any i2c node using DMA0 causes a hang.

Fixes: bc08fbf49bc8 ("arm64: dts: qcom: sm8350: Define GPI DMA engines")
Fixes: 41d6bca799b3 ("arm64: dts: qcom: sm8350: correct DMA controller unit address")
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Nia Espera <nespera@igalia.com>
Link: https://lore.kernel.org/r/20231111-nia-sm8350-for-upstream-v4-2-3a638b02eea5@igalia.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sm8350: move DPU opp-table to its node

The Qualcomm MDSS bindings expect that DPU opp-table is defined within
DPU node:

sm8350-hdk.dtb: display-subsystem@ae00000: Unevaluated properties are not allowed ('opp-table' was unexpected)

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20231107103540.27353-3-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sm8350: Add TCSR halt register space

Enable download mode for sm8350 which can help collect
ramdump for this SoC.

Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/1698253601-11957-3-git-send-email-quic_mojha@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sm8350: switch USB QMP PHY to new style of bindings

Change the USB QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes).

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230824211952.1397699-15-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sm8350: fix pinctrl for UART18

On sm8350 QUP18 uses GPIO 68/69, not 58/59. Fix correponding UART18
pinconf configuraion.

Fixes: 98374e6925b8 ("arm64: dts: qcom: sm8350: Set up WRAP2 QUPs")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230825214550.1650938-1-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: Use QCOM_SCM_VMID defines for qcom,vmid

Since we have those defines available in a header, let's use them
everywhere where qcom,vmid property is used.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Link: https://lore.kernel.org/r/20230818-qcom-vmid-defines-v1-1-45b610c96b13@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sm8350: add APR and LPASS TLMM

Add audio-related nodes: the APR in the ADSP (same as on SM8250) and
LPASS TLMM pin controller.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230719192809.434709-3-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sm8350: Update the RPMHPD bindings entry

Update the RPMHPD bindings entry as per the new generic bindings defined in
rpmhpd.h for SM8350 SoC.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Link: https://lore.kernel.org/r/1689840545-5094-3-git-send-email-quic_rohiagar@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sm8350: Use proper CPU compatibles

The Kryo names (once again) turned out to be fake. The CPUs report:

0x412fd050 (CA55 r2p0) (0 - 3)
0x411fd410 (CA78 r1p1) (4 - 6)
0x411fd440 (CX1 r1p1) (7)

Use the compatibles that reflect that.

Fixes: b7e8f433a673 ("arm64: dts: qcom: Add basic devicetree support for SM8350 SoC")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230706-topic-sm8350-cpu-compat-v1-1-f8d6a1869781@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sm8350: Add missing LMH interrupts to cpufreq

Add the missing interrupts that communicate the hardware-managed
throttling to Linux.

Fixes: ccbb3abb23a5 ("arm64: dts: qcom: sm8350: Add cpufreq node")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230705-topic-sm8350_fixes-v1-3-0f69f70ccb6a@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sm8350: Fix CPU idle state residency times

The present values look to have been copypasted from 8150 or 8180.
Fix that.

Fixes: 07ddb302811e ("arm64: dts: qcom: sm8350: Add CPU topology and idle-states")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230705-topic-sm8350_fixes-v1-2-0f69f70ccb6a@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sm8350: Add missing cluster sleep state

SM8350's cores can be shut off, without engaging full-on SoC-wide power
collapse. Add the missing idle state to allow for that.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230705-topic-sm8350_fixes-v1-1-0f69f70ccb6a@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: minor whitespace cleanup around '='

The DTS code coding style expects exactly one space before and after '='
sign.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230702185051.43867-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sm8350: fix BAM DMA crash and reboot

SM8350 HDK and MTP boards were silently dying and rebooting during BAM
DMA probe, probably during reading BAM_REVISION register:

[ 1.574304] vreg_bob: Setting 3008000-3960000uV
[ 1.576918] bam-dFormat: Log Type - Time(microsec) - Message -
Optional Info
Log Type: B - Since Boot(Power On Reset), D - Delta, S - Statistic
S - QC_IMAGE_VERSION_STRING=BOOT.MXF.1.0-00637.1-LAHAINA-1
S - IMAGE_VARIANT_STRING=SocLahainaLAA
S - OEM_IMAGE_VERSION_STRING=crm-ubuntu77
S - Boot Interface: UFS

It seems that BAM DMA is not yet operational, thus mark it as failed and
disable also QCE because it won't work without BAM DMA.

Fixes: f1040a7fe8f0 ("arm64: dts: qcom: sm8350: Add Crypto Engine support")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230626145959.646747-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

arm64: dts: qcom: sm8350: Add missing interconnect paths to USB HCs

The USB HCs nodes are missing the interconnect paths, so add them.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230602062016.1883171-5-abel.vesa@linaro.org

arm64: dts: qcom: sm8350: Add Crypto Engine support

Add crypto engine (CE) and CE BAM related nodes and definitions to
'sm8350.dtsi'.

Co-developed-by and Signed-off-by: Robert Foss <rfoss@kernel.org>
[Bhupesh: Switch to '#interconnect-cells = <2>', available since commit 4f287e31ff5f]

Tested-by: Anders Roxell <anders.roxell@linaro.org>
Tested-by: Linux Kernel Functional Testing <lkft@linaro.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230526192210.3146896-11-bhupesh.sharma@linaro.org

arm64: dts: qcom: sm8350: correct USB phy unit address

Match unit-address to reg entry to fix dtbs W=1 warnings:

Warning (simple_bus_reg): /soc@0/phy@88e9000: simple-bus unit address format error, expected "88e8000"

Fixes: 2458a305e80e ("arm64: dts: qcom: sm8350: switch to combo usb3/dp phy")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230419211856.79332-15-krzysztof.kozlowski@linaro.org

arm64: dts: qcom: sm8350: correct PCI phy unit address

Match unit-address to reg entry to fix dtbs W=1 warnings:

Warning (simple_bus_reg): /soc@0/phy@1c0f000: simple-bus unit address format error, expected "1c0e000"

Fixes: 6daee40678a0 ("arm64: dts: qcom: sm8350: add PCIe devices")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230419211856.79332-14-krzysztof.kozlowski@linaro.org

arm64: dts: qcom: sm8350: correct DMA controller unit address

Match unit-address to reg entry to fix dtbs W=1 warnings:

Warning (simple_bus_reg): /soc@0/dma-controller@900000: simple-bus unit address format error, expected "9800000"

Fixes: bc08fbf49bc8 ("arm64: dts: qcom: sm8350: Define GPI DMA engines")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230419211856.79332-13-krzysztof.kozlowski@linaro.org

arm64: dts: qcom: sm8350: add ports subnodes in usb1 qmpphy node

Add the USB3+DP Combo QMP PHY port subnodes in the SM8350 SoC DTSI
to avoid duplication in the devices DTs.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230503-topic-sm8450-graphics-dp-next-v3-1-6c43d293995f@linaro.org

arm64: dts: qcom: add missing cache properties

Add required cache-level and cache-unified properties to fix warnings
like:

qdu1000-idp.dtb: l3-cache: 'cache-unified' is a required property
qdu1000-idp.dtb: l2-cache: 'cache-level' is a required property

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230416101134.95686-3-krzysztof.kozlowski@linaro.org

arm64: dts: qcom: fix indentation

Correct indentation to use only tabs.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230416101134.95686-1-krzysztof.kozlowski@linaro.org

arm64: dts: qcom: Remove "iommus" property from PCIe nodes

Currently, most of the Qualcomm SoCs specify both "iommus" and "iommu-map"
properties for the PCIe nodes. First one passes the SMR mask to the iommu
driver and the latter specifies the SID for each PCIe device.

But with "iommus" property, the PCIe controller will be added to the
iommu group along with the devices. This makes no sense because the
controller will not initiate any DMA transaction on its own. And moreover,
it is not strictly required to pass the SMR mask to the iommu driver. If
the "iommus" property is not present, then the default mask of "0" would be
used which should work for all PCIe devices.

On the other side, if the SMR mask specified doesn't match the one expected
by the hypervisor, then all the PCIe transactions will end up triggering
"Unidentified Stream Fault" by the SMMU.

So to get rid of these hassles and also prohibit PCIe controllers from
adding to the iommu group, let's remove the "iommus" property from PCIe
nodes.

Reported-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/linux-arm-msm/20230227195535.GA749409-robh@kernel.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308075648.134119-1-manivannan.sadhasivam@linaro.org

arm64: dts: qcom: sm8350: drop incorrect domain idle states properties

Domain idle states do not use 'idle-state-name' and 'local-timer-stop':

sm8350-mtp.dtb: domain-idle-states: cluster-sleep-0: 'idle-state-name', 'local-timer-stop' do not match any of the regexes: 'pinctrl-[0-9]+'

Reported-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/all/20230323-topic-sm8450-upstream-dt-bindings-fixes-v1-4-3ead1e418fe4@linaro.org/
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230324073813.22158-5-krzysztof.kozlowski@linaro.org

arm64: dts: qcom: sm8350: add dp controller

Add the Display Port controller subnode to the MDSS node.

Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> #SM8350-HDK
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230206-topic-sm8450-upstream-dp-controller-v6-3-d78313cbc41d@linaro.org

arm64: dts: qcom: sm8350: switch to combo usb3/dp phy

The first QMP PHY is an USB3/DP combo phy, switch to the newly
documented bindings and register the clocks to the GCC
and DISPCC controllers.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> #SM8350-HDK
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230206-topic-sm8450-upstream-dp-controller-v6-2-d78313cbc41d@linaro.org

arm64: dts: qcom: drop redundant line breaks

Remove trailing, redundant line breaks.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230306081430.28491-2-krzysztof.kozlowski@linaro.org

arm64: dts: qcom: sm8350: add port subnodes in dwc3 node

Add ports subnodes in dwc3 node to avoid repeating the
same description in each board DT.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230130-topic-sm8450-upstream-pmic-glink-v5-6-552f3b721f9e@linaro.org

arm64: dts: qcom: sm8350: Fix the PCI I/O port range

For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are
located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses
(0x60200000, 0x40200000) specified in the ranges property for I/O region.

While at it, let's use the missing 0x prefix for the addresses.

Fixes: 6daee40678a0 ("arm64: dts: qcom: sm8350: add PCIe devices")
Reported-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230228164752.55682-14-manivannan.sadhasivam@linaro.org

arm64: dts: qcom: sm8350: Fix the base addresses of LLCC banks

The LLCC block has several banks each with a different base address
and holes in between. So it is not a correct approach to cover these
banks with a single offset/size. Instead, the individual bank's base
address needs to be specified in devicetree with the exact size.

Reported-by: Parikshit Pareek <quic_ppareek@quicinc.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230314080443.64635-10-manivannan.sadhasivam@linaro.org

arm64: dts: qcom: sm8350: Add qcom,smmu-500 to Adreno SMMU

Add the fallback Qualcomm SMMU500 compatible to the Adreno SMMU.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230216145646.4095336-5-konrad.dybcio@linaro.org

arm64: dts: qcom: sm8350: Supply clock from cpufreq node to CPUs

Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks
to the CPU cores. But this relationship is not represented in DTS so far.

So let's make cpufreq node as the clock provider and CPU nodes as the
consumers. The clock index for each CPU node is based on the frequency
domain index.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230215070400.5901-10-manivannan.sadhasivam@linaro.org

arm64: dts: qcom: sm8350: Mark UFS controller as cache coherent

The UFS controller on SM8350 supports cache coherency, hence add the
"dma-coherent" property to mark it as such.

Fixes: 59c7cf814783 ("arm64: dts: qcom: sm8350: Add UFS nodes")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230307153201.180626-1-manivannan.sadhasivam@linaro.org

arm64: dts: qcom: sm8350: add GPU, GMU, GPU CC and SMMU nodes

Add device nodes required to enable GPU on the SM8350 platform.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
[bjorn: Workaround for lacking RPMH_REGULATOR_LEVEL_LOW_SVS_L1 constant]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230209133839.762631-6-dmitry.baryshkov@linaro.org

arm64: dts: qcom: sm8350: finish reordering nodes

Finish reordering DT nodes by their address. Move PDC, tsens, AOSS,
SRAM, SPMI and TLMM nodes to the proper position.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230209133839.762631-5-dmitry.baryshkov@linaro.org

arm64: dts: qcom: sm8350: move more nodes to correct place

Continue ordering DT nodes by their address. Move RNG, UFS, system NoC
and SLPI nodes to the proper position.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230209133839.762631-4-dmitry.baryshkov@linaro.org

arm64: dts: qcom: sm8350: reorder device nodes

Somehow sm8350 got its device nodes not fully sorted. Start reordering
DT nodes by their address. Move apps SMMU, GIC, timer, apps RSC, cpufreq
ADSP and cDSP nodes to the end to the proper position at the end of
/soc/.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230209133839.762631-3-dmitry.baryshkov@linaro.org

arm64: dts: qcom: sm8350: fixup SDHCI interconnect arguments

After switching interconnects to 2 cells, the SDHCI interconnects need
to get one more argument.

Fixes: 4f287e31ff5f ("arm64: dts: qcom: sm8350: Use 2 interconnect cells")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230119105434.51635-1-krzysztof.kozlowski@linaro.org

arm64: dts: qcom: sm8350: drop incorrect cells from serial

The serial/UART device node does not have children with unit addresses,
so address/size cells are not correct.

Fixes: cf03cd7e12bd ("arm64: dts: qcom: sm8350: Set up WRAP0 QUPs")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230124084951.38195-2-krzysztof.kozlowski@linaro.org

arm64: dts: qcom: sm8350: use qcom,sm8350-dsi-ctrl compatibles

Add the per-SoC (qcom,sm8350-dsi-ctrl) compatible strings to DSI nodes
to follow the pending DSI bindings changes.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230118032024.1715857-1-dmitry.baryshkov@linaro.org

arm64: dts: qcom: sm8350: Hook up DSI1 to MDP

Somehow DSI1 was not hooked up to MDP resulting in it not working.
Fix it.

Fixes: d4a4410583ed ("arm64: dts: qcom: sm8350: Add display system nodes")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230120210101.2146852-8-konrad.dybcio@linaro.org

arm64: dts: qcom: sm8350: Add mdss_ prefix to DSIn out labels

Add the mdss_ prefix to DSIn labels, so that the hardware blocks can
be organized near each other while retaining the alphabetical order
in device DTs when referencing by label.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230120210101.2146852-7-konrad.dybcio@linaro.org

arm64: dts: qcom: sm8350: Fix DSI PLL size

As downstream indicates, DSI PLL is actually 0x27c and not 0x260-
wide. Fix that to reserve the correct registers.

Fixes: d4a4410583ed ("arm64: dts: qcom: sm8350: Add display system nodes")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230120210101.2146852-6-konrad.dybcio@linaro.org

arm64: dts: qcom: sm8350: Fix DSI PHY compatibles

The compatibles were wrong, resulting in the driver not probing. Fix
that.

Fixes: d4a4410583ed ("arm64: dts: qcom: sm8350: Add display system nodes")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230120210101.2146852-5-konrad.dybcio@linaro.org

arm64: dts: qcom: sm8350: Feed DSI1 PHY clocks to DISPCC

This was omitted but is necessary for DSI1 to function. Fix it.

Fixes: d4a4410583ed ("arm64: dts: qcom: sm8350: Add display system nodes")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230120210101.2146852-4-konrad.dybcio@linaro.org

arm64: dts: qcom: sm8350: Fix DSI1 interrupt

The interrupt was wrong, likely copypasted from DSI0. Fix it.

Fixes: d4a4410583ed ("arm64: dts: qcom: sm8350: Add display system nodes")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230120210101.2146852-3-konrad.dybcio@linaro.org

arm64: dts: qcom: sm8350: Add missing #address/size-cells to DSIn

Panels/DRM bridges definitely don't need 64bits of address space and
are usually not 32-bit wide. Set address-cells to 1 and size-cells to
0.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230120210101.2146852-2-konrad.dybcio@linaro.org

arm64: dts: qcom: sm8350: Pad addresses to 8 hex digits

Some addresses were 7-hex-digits long, or less. Fix that.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230102094642.74254-12-konrad.dybcio@linaro.org

arm64: dts: qcom: sm8350: Use 2 interconnect cells

Use two interconnect cells in order to optionally
support a path tag.

Signed-off-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230117115712.1054613-1-rfoss@kernel.org

arm64: dts: qcom: sm8350: Add display system nodes

Add mdss, mdss_mdp, dsi0, dsi0_phy nodes. With these
nodes the display subsystem is configured to support
one DSI output.

Signed-off-by: Robert Foss <robert.foss@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230117120223.1055225-2-rfoss@kernel.org

arm64: dts: qcom: sm8350: drop unused dispcc power-domain-names

Display clock controller bindings do not allow power-domain-names:

sm8350-hdk.dtb: clock-controller@af00000: 'power-domain-names' does not match any of the regexes: 'pinctrl-[0-9]+'
From schema: Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221227163158.102737-1-krzysztof.kozlowski@linaro.org

arm64: dts: qcom: use UFS symbol clocks provided by PHY

Remove manually created symbol clocks and replace them with clocks
provided by PHY.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221123104443.3415267-5-dmitry.baryshkov@linaro.org

arm64: dts: qcom: sm8350: add PCIe devices

Add PCIe0 and PCIe1 (and corresponding PHY) devices found on SM8350
platform. The PCIe0 is a 1-lane Gen3 host, PCIe1 is a 2-lane Gen3 host.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221118233242.2904088-8-dmitry.baryshkov@linaro.org

arm64: dts: qcom: add missing space before {

Add missingh whitespace between node name/label and opening {.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221230140133.57885-2-krzysztof.kozlowski@linaro.org

arm64: dts: qcom: sm8350: Drop standalone smem node

SM8350 is one of the last SoCs whose DTSI escaped the smem node
conversion. Use the newer memory-node binding instead of a memory *and*
smem node.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221219162618.873117-1-konrad.dybcio@linaro.org

arm64: dts: qcom: replace underscores in node names

Underscores should not be used in node names (dtc with W=2 warns about
them), so replace them with hyphens. In few places adjust the name to
match other nodes (e.g. xxx-regulator).

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221214110448.86268-1-krzysztof.kozlowski@linaro.org

arm64: dts: qcom: rename AOSS QMP nodes

The Always On Subsystem (AOSS) QMP is not a power domain controller
since commit 135780456218 ("arm64: dts: qcom: sc7180: Use QMP property
to control load state") and few others. In fact, it was never a power
domain controller but rather control of power state of remote
processors. This power state control is now handled differently, thus
the AOSS QMP nodes do not have power-domain-cells:

sc7280-idp.dtb: power-controller@c300000: '#power-domain-cells' is a required property
From schema: Documentation/devicetree/bindings/power/power-domain.yaml

AOSS QMP is an interface to the actuall AOSS subsystem responsible for
some of power management functions, thus let's call the nodes as
"power-management".

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221213101921.47924-4-krzysztof.kozlowski@linaro.org

arm64: dts: qcom: sm8350: align PSCI domain names with DT schema

Bindings expect power domains to follow generic naming pattern:

sm8350-hdk.dtb: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6',
'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+'

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230102085452.10753-5-krzysztof.kozlowski@linaro.org

arm64: dts: qcom: sm8350: align MMC node names with DT schema

The bindings expect "mmc" for MMC/SDHCI nodes:

sm8350-sony-xperia-sagami-pdx214.dtb: sdhci@8804000: $nodename:0: 'sdhci@8804000' does not match '^mmc(@.*)?$'

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221223161835.112079-4-krzysztof.kozlowski@linaro.org

arm64: dts: qcom: Update cache properties

The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).

Update the Device Trees accordingly.

About msm8953.dtsi:
According to the Devicetree Specification v0.3,
s3.7.3 'Internal (L1) Cache Properties',
cache-unified:
If present, specifies the cache has a unified or-
ganization. If not present, specifies that the
cache has a Harvard architecture with separate
caches for instructions and data.
Plus, the 'cache-level' property seems to be reserved to higher
cache levels (cf s3.8).

To describe a l1 data/instruction cache couple, no cache
information should be described. Remove the l1 cache nodes.

Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
[bjorn: Moved "qcom" to $subject prefix]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221107155825.1644604-17-pierre.gondois@arm.com

arm64: dts: qcom: sm8350: correct SDHCI interconnect arguments

The interconnect providers accept only one argument (cells == 1), so fix
a copy&paste from SM8450:

sm8350-hdk.dtb: mmc@8804000: interconnects: [[74, 9, 0], [75, 1, 0], [76, 2, 0], [77, 36, 0]] is too long

Fixes: 60477435e4de ("arm64: dts: qcom: sm8350: Add SDHCI2")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221224214351.18215-1-krzysztof.kozlowski@linaro.org

arm64: dts: qcom: sm8350: Add SDHCI2

Add and configure the SDHCI host responsible for (mostly) SD Card and
its corresponding pins' sleep states.

The setup is *literally* 1:1 with 8450 (bar SDR50/104 may not be
broken).

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221116123612.34302-2-konrad.dybcio@linaro.org

arm64: dts: qcom: trim addresses to 8 digits

Hex numbers in addresses and sizes should be rather eight digits, not
nine. Drop leading zeros. No functional change (same DTB).

Suggested-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221115105046.95254-1-krzysztof.kozlowski@linaro.org

arm64: dts: qcom: Add power-domains property for apps_rsc

Add power-domains property which allows apps_rsc device to attach
to cluster power domain on sm8150, sm8250, sm8350 and sm8450.

Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # SM8450
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221018152837.619426-4-ulf.hansson@linaro.org

arm64: dts: qcom: sm8350: fix UFS PHY registers

The sizes of the UFS PHY register regions are too small and does
specifically not cover all registers used by the Linux driver.

As Linux maps these regions as full pages this is currently not an issue
on Linux, but let's update the sizes to match the vendor driver.

Fixes: 59c7cf814783 ("arm64: dts: qcom: sm8350: Add UFS nodes")
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221024091507.20342-4-johan+linaro@kernel.org

arm64: dts: qcom: sm8350: Add GPI DMA compatible fallback

Use SM6350 as fallback for GPI DMA, to indicate devices are compatible
and that drivers can bind with only one compatible.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221018230352.1238479-5-krzysztof.kozlowski@linaro.org

arm64: dts: qcom: sm8350: align TLMM pin configuration with DT schema

DT schema expects TLMM pin configuration nodes to be named with '-state'
suffix and their optional children with '-pins' suffix.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220912061746.6311-38-krzysztof.kozlowski@linaro.org

arm64: dts: qcom: sm8350: fix UFS PHY serdes size

The size of the UFS PHY serdes register region is 0x1c4 and the
corresponding 'reg' property should specifically not include the
adjacent regions that are defined in the child node (e.g. tx and rx).

Fixes: 59c7cf814783 ("arm64: dts: qcom: sm8350: Add UFS nodes")
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220916093603.24263-1-johan+linaro@kernel.org

arm64: dts: qcom: reorder USB interrupts

Three SoCs did not follow the interrupt order specified by the USB
controller binding.

While keeping the non-SuperSpeed interrupts together seems natural,
reorder the interrupts to match the binding.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
[bjorn: Omitted sdx65 part from this patch]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220715070248.19078-5-johan+linaro@kernel.org

arm64: dts: qcom: sm8250: drop UFS PHY clock-cells

The QMP UFS PHY provides more than one symbol clock and would need an
index to differentiate the clocks, but none of this is described by the
binding currently.

Drop the incorrect '#clock-cells' property for now.

Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220705114032.22787-11-johan+linaro@kernel.org

arm64: dts: qcom: sm8350: drop USB PHY clock index

The QMP USB PHY provides a single clock so drop the redundant clock
index.

Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220705114032.22787-8-johan+linaro@kernel.org

arm64: dts: qcom: sm8350: Replace integers with rpmpd defines

Replace &rpmhpd power domain integers with their respective defines
in order to improve legibility.

Signed-off-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220706152830.2021197-1-robert.foss@linaro.org

arm64: dts: qcom: sm8350: Add DISPCC node

Add the dispcc clock-controller DT node for sm8350.

Signed-off-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220706154337.2026269-6-robert.foss@linaro.org

arm64: dts: qcom: sm8350: Move qup-opp-tables out of soc node

The soc node expects all the nodes to have unit addresses. The
qup-opp-tables do not have that which causes warnings:

arch/arm64/boot/dts/qcom/sm8350.dtsi:640.46-657.5:
Warning (simple_bus_reg): /soc@0/qup-100mhz-opp-table:
missing or empty reg/ranges property
arch/arm64/boot/dts/qcom/sm8350.dtsi:659.46-676.5:
Warning (simple_bus_reg): /soc@0/qup-120mhz-opp-table:
missing or empty reg/ranges property

Move the qup-opp-tables out of soc node to fix these warnings

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
[bjorn: Rebased ontop of Krzysztof's node name update]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220606065035.553533-3-vkoul@kernel.org

arm64: dts: qcom: sm8350: remove duplicated glink-edge interrupt

Specifying interrupts and interrupts-extended is not correct. Keep only
the extended ones, routed towards IPCC mailbox to fix warnings like:

sm8350-sony-xperia-sagami-pdx214.dtb: glink-edge: More than one condition true in oneOf schema:
{'$filename': 'Documentation/devicetree/bindings/remoteproc/qcom,glink-edge.yaml',

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220517070113.18023-12-krzysztof.kozlowski@linaro.org

arm64: dts: qcom: add missing AOSS QMP compatible fallback

The AOSS QMP bindings expect all compatibles to be followed by fallback
"qcom,aoss-qmp" because all of these are actually compatible with each
other. This fixes dtbs_check warnings like:

sm8250-hdk.dtb: power-controller@c300000: compatible: ['qcom,sm8250-aoss-qmp'] is too short

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220504131923.214367-6-krzysztof.kozlowski@linaro.org

arm64: dts: qcom: timer should use only 32-bit size

There's no reason the timer needs > 32-bits of address or size.
Since we using 32-bit size, we need to define ranges properly.

Fixes warnings as:
```
arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dt.yaml: timer@17c90000: #size-cells:0:0: 1 was expected
From schema: Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml
```

Signed-off-by: David Heidelberg <david@ixit.cz>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220626105800.35586-1-david@ixit.cz

arm64: dts: qcom: align OPP table names with DT schema

DT schema expects names of operating points tables to start with
"opp-table":

ipq6018-cp01-c1.dtb: cpu_opp_table: $nodename:0: 'cpu_opp_table' does not match '^opp-table(-[a-z0-9]+)?$'

Use hyphens instead of underscores, fix the names to match DT schema or
remove the prefix entirely when it is not needed.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220627093250.84391-1-krzysztof.kozlowski@linaro.org

arm64: dts: qcom: align DWC3 USB clocks with DT schema

Align order of clocks and their names with Qualcomm DWC3 USB DT schema.
No functional impact expected.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220504131923.214367-13-krzysztof.kozlowski@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

arm64: dts: qcom: sm8350: Add GENI I2C/SPI DMA channels

The GENI I2C and SPI controllers may use the GPI DMA engine, define the
rx and tx channels for these controllers to enable this.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20220412215137.2385831-2-bjorn.andersson@linaro.org

arm64: dts: qcom: sm8350: Define GPI DMA engines

The Qualcomm SM8350 has three GPI DMA engines, add definitions for
these.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20220412215137.2385831-1-bjorn.andersson@linaro.org

arm64: dts: qcom: do not use underscore in BCM node name

Align BCM voter node with DT schema by using hyphen instead of
underscore.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220411085935.130072-3-krzysztof.kozlowski@linaro.org

arm64: dts: qcom: sm8350: drop duplicated ref_clk in UFS

ref_clk clock in UFS node is already there with a <0 0> frequency, which
matches other DTSI files.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220407092725.232463-3-krzysztof.kozlowski@linaro.org

arm64: dts: qcom: add non-secure domain property to fastrpc nodes

FastRPC DSP domain would be set as secure if non-secure dsp property is not
added to the fastrpc DT node. Add this property to DT files of msm8916,
sdm845, sm8150, sm8250 and sm8350 so that nothing is broken after secure
domain patchset.

This patch is purely for backward compatibility reasons.

Signed-off-by: Jeya R <jeyr@codeaurora.org>
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20220214161002.6831-13-srinivas.kandagatla@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

arm64: dts: qcom: add IPA qcom,qmp property

At least three platforms require the "qcom,qmp" property to be
specified, so the IPA driver can request register retention across
power collapse. Update DTS files accordingly.

Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220201140723.467431-1-elder@linaro.org

arm64: dts: qcom: sm8350: Correct TCS configuration for apps rsc

Correct the TCS config by updating the number of TCSes for each type.

Cc: devicetree@vger.kernel.org
Fixes: b7e8f433a673 ("arm64: dts: qcom: Add basic devicetree support for SM8350 SoC")
Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1641749107-31979-4-git-send-email-quic_mkshah@quicinc.com

arm64: dts: qcom: fix thermal zones naming

Rename thermal zones according to dt-schema.
Fixes multiple `make dtbs_check` warnings about name convetion.

Signed-off-by: David Heidelberg <david@ixit.cz>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211214132750.69782-1-david@ixit.cz

arm64: dts: qcom: sm8350: Correct UFS symbol clocks

The introduction of '9a61f813fcc8 ("clk: qcom: regmap-mux: fix parent
clock lookup")' broke UFS support on SM8350.

The cause for this is that the symbol clocks have a specified rate in
the "freq-table-hz" table in the UFS node, which causes the UFS code to
request a rate change, for which the "bi_tcxo" happens to provide the
closest rate. Prior to the change in regmap-mux it was determined
(incorrectly) that no change was needed and everything worked.

The rates of 75 and 300MHz matches the documentation for the symbol
clocks, but we don't represent the parent clocks today. So let's mimic
the configuration found in other platforms, by omitting the rate for the
symbol clocks as well to avoid the rate change.

While at it also fill in the dummy symbol clocks that was dropped from
the GCC driver as it was upstreamed.

Fixes: 59c7cf814783 ("arm64: dts: qcom: sm8350: Add UFS nodes")
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20211222162058.3418902-1-bjorn.andersson@linaro.org

Revert "arm64: dts: qcom: sm8350: Specify clock-frequency for arch timer"

This reverts commit ed9500c1df59437856d43e657f185fb1eb5d817d.

The clock-frequency property was meant to aid platforms with broken firmwares
that don't set up the timer properly on their own. Don't include it where it is
not the case.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211202004328.459899-1-konrad.dybcio@somainline.org

arm64: dts: qcom: sm8350: Add LLCC node

Configure the Last-Level Cache Controller for SM8350.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211114012755.112226-16-konrad.dybcio@somainline.org

arm64: dts: qcom: sm8350: Assign iommus property to QUP WRAPs

Assign the iommus property to allow access to QUP hosts that were not set up by
the bootloader.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211114012755.112226-12-konrad.dybcio@somainline.org

arm64: dts: qcom: sm8350: Set up WRAP2 QUPs

Set up I2C&SPI hosts and UARTs connected to WRAP2 and their respective pins.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211114012755.112226-11-konrad.dybcio@somainline.org

arm64: dts: qcom: sm8350: Set up WRAP1 QUPs

Set up I2C&SPI hosts and UARTs connected to WRAP1 and their respective pins.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211114012755.112226-10-konrad.dybcio@somainline.org

arm64: dts: qcom: sm8350: Set up WRAP0 QUPs

Set up I2C&SPI hosts and UARTs connected to WRAP0 and their respective pins.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211114012755.112226-9-konrad.dybcio@somainline.org

arm64: dts: qcom: sm8350: Describe GCC dependency clocks

Add all the clock names that the GCC driver expects to get via DT, so that the
clock handles can be filled as the development progresses.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211114012755.112226-8-konrad.dybcio@somainline.org

arm64: dts: qcom: sm8350: Shorten camera-thermal-bottom name

Thermal zone names should not be longer than 20 names, which is indicated by
a message at boot. Change "camera-thermal-bottom" to "cam-thermal-bottom" to
fix it.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211114012755.112226-6-konrad.dybcio@somainline.org

arm64: dts: qcom: sm[68]350: Use interrupts-extended with pdc interrupts

Using interrupts = <&pdc X Y> makes the interrupt framework interpret this as
the &pdc-nth range of the main interrupt controller (GIC). Fix it.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211114012755.112226-5-konrad.dybcio@somainline.org

arm64: dts: qcom: sm8350: Specify clock-frequency for arch timer

Arch timer runs at 19.2 MHz. Specify the rate in the timer node.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211114012755.112226-4-konrad.dybcio@somainline.org

arm64: dts: qcom: sm8350: Add redistributor stride to GICv3

The redistributor properties were missing. Add them.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211114012755.112226-3-konrad.dybcio@somainline.org

arm64: dts: qcom: sm8350: Add missing QUPv3 ID2

Add the missing third QUPv3 master node.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211114012755.112226-2-konrad.dybcio@somainline.org

arm64: dts: qcom: sm8350: Move gpio.h inclusion to SoC DTSI

Almost any board that boots and has a way to interact with it
(say for the rare cases of just-pstore or let's-rely-on-bootloader-setup)
needs to set some GPIOs, so it makes no sense to include gpio.h separately
each time. Hence move it to SoC DTSI.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211114012755.112226-1-konrad.dybcio@somainline.org

arm64: dts: qcom: sm8350: Add CPU topology and idle-states

Add CPU topology and define the idle states for the silver and gold
cores as well as the cluster.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Robert Foss <robert.foss@linaro.org>
Link: https://lore.kernel.org/r/20210825221600.1498939-1-bjorn.andersson@linaro.org

arm64: dts: qcom: Drop reg-names from QMP PHY nodes

The 'reg-names' is not a supported/used property. Drop it from QMP PHY
nodes to fix dtbs_check warnings like below.

phy-wrapper@88e9000: 'reg-names' does not match any of the regexes: '^phy@[0-9a-f]+$', 'pinctrl-[0-9]+'
arch/arm64/boot/dts/qcom/sm8350-hdk.dt.yaml
arch/arm64/boot/dts/qcom/sm8350-mtp.dt.yaml

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210929034253.24570-7-shawn.guo@linaro.org

arm64: dts: qcom: Correct QMP PHY child node name

Many child nodes of QMP PHY are named without following bindings schema
and causing dtbs_check warnings like below.

phy@1c06000: 'lane@1c06800' does not match any of the regexes: '^phy@[0-9a-f]+$'
arch/arm64/boot/dts/qcom/msm8998-asus-novago-tp370ql.dt.yaml
arch/arm64/boot/dts/qcom/msm8998-hp-envy-x2.dt.yaml
arch/arm64/boot/dts/qcom/msm8998-lenovo-miix-630.dt.yaml
arch/arm64/boot/dts/qcom/msm8998-mtp.dt.yaml
arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dt.yaml
arch/arm64/boot/dts/qcom/msm8998-oneplus-dumpling.dt.yaml

Correct them to fix the warnings.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210929034253.24570-5-shawn.guo@linaro.org

arm64: dts: qcom: msm8996: Move '#clock-cells' to QMP PHY child node

'#clock-cells' is a required property of QMP PHY child node, not itself.
Move it to fix the dtbs_check warnings.

There are only '#clock-cells' removal from SM8350 QMP PHY nodes, because
child nodes already have the property.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210929034253.24570-4-shawn.guo@linaro.org

arm64: dts: qcom: sm8350: Add fastrpc nodes

Add fastrpc nodes for sDSP, cDSP, and aDSP.

Signed-off-by: Ola Jeppsson <ola@snap.com>
Acked-by: Heinrich Fink <hfink@snap.com>
Acked-by: Olivier Schonken <oschonken@snapchat.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211018085017.1549494-1-ola@snap.com

arm64: dts: qcom: Enable RPMh Sleep stats

Add device node for Sleep stats driver which provides various
low power mode stats on sc7180, sc7280, sm8150, sm8250 and sm8350.

Also update the reg size of aoss_qmp device to 0x400.

Cc: devicetree@vger.kernel.org
Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1634107104-22197-5-git-send-email-mkshah@codeaurora.org

arm64: dts: qcom: sm8350: Use QMP property to control load state

Use the Qualcomm Mailbox Protocol (QMP) property to control the load
state resources on SM8350 SoCs and drop deprecated power-domains exposed
by AOSS QMP node.

Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1631800770-371-11-git-send-email-sibis@codeaurora.org

arm64: dts: qcom: sm8350: fix IPA interconnects

There should only be two interconnects defined for IPA on the
QUalcomm SM8350 SoC. The names should also match those specified by
the IPA Device Tree binding.

Fixes: f11d3e7da32e ("arm64: dts: qcom: sm8350: add IPA information")
Signed-off-by: Alex Elder <elder@linaro.org>
Link: https://lore.kernel.org/r/20210804210214.1891755-5-elder@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sm8350: add qupv3_id_1/i2c13 nodes

Add the qupv3_id_1 node and the i2c13 child node used for i2c devices
connected to gpio0/gpio1.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Link: https://lore.kernel.org/r/20210513181309.12491-2-jonathan@marek.ca
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sm8350: Rename GENI serial engine DT node

In order to conform with downstream and upstream for previous generations
of this hardware, rename dt-node 'qupv3_id_1' to 'qupv3_id_0'.

Fixes: b7e8f433a673 ("arm64: dts: qcom: Add basic devicetree support for SM8350 SoC")
Signed-off-by: Robert Foss <robert.foss@linaro.org>
Link: https://lore.kernel.org/r/20210803125756.93824-1-robert.foss@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sm8350: Add wakeup-parent to tlmm

Now that TLMM has the wakeup table, specify the Power Domain Controller
to be the wakeup-parent of TLMM.

Reviewed-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210312034218.3324410-2-bjorn.andersson@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: Use correct naming for dwc3 usb nodes in dts files

The dwc3 usb nodes in several arm64 qcom dts are currently named
differently, somewhere as 'usb@<addr>' and somewhere as 'dwc3@<addr>',
leading to some confusion when one sees the entries in sysfs or
dmesg:
[ 1.943482] dwc3 a600000.usb: Adding to iommu group 1
[ 2.266127] dwc3 a800000.dwc3: Adding to iommu group 2

Name the usb nodes as 'usb@<addr>' for consistency, which is
the correct convention as per the 'snps,dwc3' dt-binding as
well (see [1]).

[1]. Documentation/devicetree/bindings/usb/snps,dwc3.yaml

Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Link: https://lore.kernel.org/r/20210627114616.717101-2-bhupesh.sharma@linaro.org
[bjorn: Extended to also fix ipq6018]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sm8350: fix the node unit addresses

Some node unit addresses were put wrongly in the dts, resulting in
below warning when run with W=1

arch/arm64/boot/dts/qcom/sm8350.dtsi:693.34-702.5: Warning (simple_bus_reg): /soc@0/thermal-sensor@c222000: simple-bus unit address format error, expected "c263000"
arch/arm64/boot/dts/qcom/sm8350.dtsi:704.34-713.5: Warning (simple_bus_reg): /soc@0/thermal-sensor@c223000: simple-bus unit address format error, expected "c265000"
arch/arm64/boot/dts/qcom/sm8350.dtsi:1180.32-1185.5: Warning (simple_bus_reg): /soc@0/interconnect@90e0000: simple-bus unit address format error, expected "90c0000"

Fix by correcting to the correct address as given in reg node

Reviewed-by: Robert Foss <robert.foss@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210513060733.382420-1-vkoul@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sm8350: use interconnect enums

Add interconnect enums instead of numbers now that interconnect is in
mainline.

Reviewed-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210513060705.382184-1-vkoul@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sm8350: Add label for thermal-zones node

Add label "thermal_zones" for thermal-zones node.

Signed-off-by: satya priya <skakit@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Link: https://lore.kernel.org/r/1621937466-1502-2-git-send-email-skakit@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sm8350: add IPA information

Add IPA-related nodes and definitions to "sm8350.dtsi", which uses
IPA v4.9.

Signed-off-by: Alex Elder <elder@linaro.org>
Link: https://lore.kernel.org/r/20210413170553.1778792-2-elder@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sm8350: Add interconnects

Add interconnect nodes and add them for modem and cdsp nodes

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210401113252.3078466-1-vkoul@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sm8350: Add support for PRNG EE

RNG (Random Number Generator) in SM8350 features PRNG EE (Execution
Environment), hence add devicetree support for it.

Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Robert Foss <robert.foss@linaro.org>
Link: https://lore.kernel.org/r/20210401101536.1014560-1-robert.foss@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sm8350: Add thermal zones and throttling support

sm8350 has 29 thermal sensors split across two tsens controllers. Add
the thermal zones to expose them and wireup the cpus to throttle their
frequencies on crossing passive temperature thresholds.

Signed-off-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210324124308.1265626-2-robert.foss@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sm8350: Add spmi node

Add SPMI node found in SM8350 SoC

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210312052737.3558801-2-vkoul@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sm8350: fix number of pins in 'gpio-ranges'

The last cell of 'gpio-ranges' should be number of GPIO pins, and in
case of qcom platform it should match msm_pinctrl_soc_data.ngpio rather
than msm_pinctrl_soc_data.ngpio - 1.

This fixes the problem that when the last GPIO pin in the range is
configured with the following call sequence, it always fails with
-EPROBE_DEFER.

pinctrl_gpio_set_config()
pinctrl_get_device_gpio_range()
pinctrl_match_gpio_range()

Fixes: b7e8f433a673 ("arm64: dts: qcom: Add basic devicetree support for SM8350 SoC")
Cc: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Link: https://lore.kernel.org/r/20210303033106.549-5-shawn.guo@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sm8350: Add cpufreq node

Add cpufreq node and reference it for the CPUs.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210216111703.1838663-1-vkoul@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sm8350: Use enums for GCC

Now that we have GCC define, use the enums instead of numbers in the DTS

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210212115532.1339942-8-vkoul@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sm8350: Add remoteprocs

Add remoteproc nodes for the audio, compute and sensor cores, define
glink for each one.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210212115532.1339942-6-vkoul@kernel.org
[bjorn: Replaced rpmhpd defines with constants, for now]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sm8350: Add SMP2P nodes

SMP2P is used for interrupting and being interrupted about remoteproc
state changes related to the audio, compute, modem and sensor subsystems.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210212115532.1339942-5-vkoul@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sm8350: Add rmtfs node

Add the rmtfs as a reserved memory node.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210212115532.1339942-4-vkoul@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sm8350: Add rpmhpd node

This adds RPMH power domain found in SM8350 SoC

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210212115532.1339942-3-vkoul@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sm8350: fix typo

Fix the typo s/Limaited/Limited

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210212115532.1339942-2-vkoul@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sm8350: Add UFS nodes

This adds UFS HC and UFS phy nodes to the SM8350 DTS

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210204170907.63545-5-vkoul@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sm8350: add USB and PHY device nodes

Add device nodes for the two instances each of USB3 controllers,
QMP SS PHYs and SNPS HS PHYs.

Signed-off-by: Jack Pham <jackp@codeaurora.org>
Link: https://lore.kernel.org/r/20210116013802.1609-2-jackp@codeaurora.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210204170907.63545-3-vkoul@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sm8350: Add apss_smmu node

This adds apss_smmu node to SM8350 DTS

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210204170907.63545-2-vkoul@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sm8350: Fix level triggered PMU interrupt polarity

As per interrupt documentation for SM8350 SoC, the polarity
for level triggered PMU interrupt is low, fix this.

Fixes: b7e8f433a673 ("arm64: dts: qcom: Add basic devicetree support for SM8350 SoC")
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Link: https://lore.kernel.org/r/ca57409198477f7815e32a6a7467dcdc9b93dc4f.1613468366.git.saiprakash.ranjan@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sm8350: Rename the qmp node to power-controller

Use the generic DT node name "power-controller" for AOSS message ram
instead of the protocol name QMP(Qualcomm Messaging Protocol) since
it is used for power management requests.

Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Suggested-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Link: https://lore.kernel.org/r/15005f1441594670adcd60a300c88e41d79cad27.1614669585.git.saiprakash.ranjan@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: Add basic devicetree support for SM8350 SoC

Add basic devicetree support for Qualcomm Technologies, Inc SM8350 SoC.
This adds gcc, pinctrl, reserved memory, uart, cpu nodes for this SoC.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210127123054.263231-6-vkoul@kernel.org
[bjorn: Adjusted 4th timer interrupt, per input from Sai]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>