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ae1c0d6e |
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21-Apr-2023 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
arm64: dts: marvell: add missing cache properties As all level 2 and level 3 caches are unified, add required cache-unified properties to fix warnings like: ac5-98dx35xx-rd.dtb: l2-cache: 'cache-unified' is a required property Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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b5d971cf |
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31-Oct-2022 |
Pierre Gondois <pierre.gondois@arm.com> |
arm64: dts: Update cache properties for marvell The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The recently added init_of_cache_level() function checks these properties. Add them if missing. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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664d9ebf |
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09-Feb-2020 |
Vadym Kochan <vadym.kochan@plvision.eu> |
arm64: dts: marvell: fix non-existed cpu referrence in armada-ap806-dual.dtsi armada-ap806-dual.dtsi includes armada-ap806.dtsi which describes thermal zones for 4 cpus but only cpu0 and cpu1 only exists for dual configuration, this makes dtb compilation fail. Fix it by removing thermal zone nodes for non-existed cpus for dual configuration. Signed-off-by: Vadym Kochan <vadym.kochan@plvision.eu> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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ddda8433 |
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04-Oct-2019 |
Grzegorz Jaszczyk <jaz@semihalf.com> |
arm64: dts: marvell: Add AP806-dual cache description Adding appropriate entries to device-tree allows the cache description to show up in sysfs under: /sys/devices/system/cpu/cpuX/cache/. Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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e231c6d4 |
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04-Oct-2019 |
Miquel Raynal <miquel.raynal@bootlin.com> |
arm64: dts: marvell: Add AP806-dual missing CPU clocks CPU clocks have been added to AP806-quad but not to the -dual variant. Fixes: c00bc38354cf ("arm64: dts: marvell: Add cpu clock node on Armada 7K/8K") Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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fe7f7f22 |
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21-May-2019 |
Miquel Raynal <miquel.raynal@bootlin.com> |
arm64: dts: marvell: Enable AP806 thermal throttling with CPUfreq Avoid critical temperatures in the AP806 by adding the relevant trip points/cooling-maps using CPUfreq as cooling device. So far, when the temperature reaches 100°C in the thermal IP of the AP806 (close enough from the 2/4 cores) an overheat interrupt is raised. The thermal core then shutdowns the system to avoid damaging the hardware. Adding CPUfreq as a cooling device could help avoiding such very critical situation. For that, we enable thermal throttling by defining, for each CPU, two trip points with the corresponding cooling 'intensity'. CPU0 and CPU1 are in the same cluster and are driven by the same clock. Same applies for CPU2 and CPU3, if available. So changing the frequency of one will also change the frequency of the other one, hence the use of two cooling devices per core. The heat map is as follow: - Below 85°C: the cluster runs at the highest frequency (e.g: 1200MHz). - Between 85°C and 95°C: there are two trip points at half (e.g: 600MHz) and a third (e.g: 400MHz) of the highest frequency. - Above 95°C the cluster runs at a quarter of the highest frequency (e.g: 300MHz). - At 100°C the platform is shutdown. Suggested-by: Omri Itach <omrii@marvell.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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31af04cd |
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14-Jan-2019 |
Rob Herring <robh@kernel.org> |
arm64: dts: Remove inconsistent use of 'arm,armv8' compatible string The 'arm,armv8' compatible string is only for software models. It adds little value otherwise and is inconsistently used as a fallback on some platforms. Remove it from those platforms. This fixes warnings generated by the DT schema. Reported-by: Michal Simek <michal.simek@xilinx.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will.deacon@arm.com> Acked-by: Antoine Tenart <antoine.tenart@bootlin.com> Acked-by: Nishanth Menon <nm@ti.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Chanho Min <chanho.min@lge.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Tero Kristo <t-kristo@ti.com> Acked-by: Wei Xu <xuwei5@hisilicon.com> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Acked-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Scott Branden <scott.branden@broadcom.com> Acked-by: Kevin Hilman <khilman@baylibre.com> Acked-by: Chunyan Zhang <zhang.lyra@gmail.com> Acked-by: Robert Richter <rrichter@cavium.com> Acked-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Acked-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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92e5d4e9 |
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21-Sep-2018 |
Gregory CLEMENT <gregory.clement@bootlin.com> |
arm64: dts: marvell: Add node labels for the cpus Aligned with what we have done for the others nodes. It will also allow to easily modify the cpu configuration at board (or sub-SoC) level. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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292816a6 |
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14-Feb-2018 |
Gregory CLEMENT <gregory.clement@bootlin.com> |
arm64: dts: marvell: use SPDX-License-Identifier for Armada SoCs Follow the recent trend for the license description, and also fix the wrongly stated X11 to MIT. As already pointed on the DT ML, the X11 license text [1] is explicitly for the X Consortium and has a couple of extra clauses. The MIT license text [2] is actually what the current DT files claim. [1] https://spdx.org/licenses/X11.html [2] https://spdx.org/licenses/MIT.html Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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d8bcaabe |
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12-Oct-2017 |
Rob Herring <robh@kernel.org> |
arm64: dts: fix unit-address leading 0s Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm64/boot/dts -type -f -name '*.dts*' Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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037ad463 |
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26-Apr-2016 |
Andreas Färber <afaerber@suse.de> |
arm64: dts: marvell: clean up armada-7040-db Instead of duplicating the node hierarchy, reference the nodes by label, adding labels where necessary. Drop some trailing or inconsistent white lines while at it. Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Andreas Färber <afaerber@suse.de> [Thomas: drop Fixes tag as it is not a bug fix.] Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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ec7e5a56 |
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18-Feb-2016 |
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
arm64: dts: marvell: add Device Tree files for Armada 7K/8K This commit adds the base Device Tree files for the Armada 7K and 8K SoCs, as well as the Armada 8040 DB board. The Armada 7020, 7040 (7K family) and 8020, 8040 (8K family) are composed of: - An AP806 block that contains the CPU core and a few basic peripherals. The AP806 is available in dual core configurations (used in 7020 and 8020) and quad core configurations (used in 8020 and 8040). - One or two CP110 blocks that contain all the high-speed interfaces (SATA, PCIe, Ethernet, etc.). The 7K family chips have one CP110, and the 8K family chips have two CP110, giving them twice the number of HW interfaces. In order to represent this from a Device Tree point of view, this commit creates the following hierarchy: * armada-ap806.dtsi - definitions common to dual/quad ap806 * armada-ap806-dual.dtsi - description of the two CPUs * armada-7020.dtsi - description of the 7020 SoC * armada-8020.dtsi - description of the 8020 SoC * armada-ap806-quad.dtsi - description of the four CPUs * armada-7040.dtsi - description of the 7040 SoC * armada-7040-db.dts - description of the 7040 board * armada-8040.dtsi - description of the 8040 SoC The CP110 blocks are not described yet, and will be part of future patch series. [gregory.clement@free-electrons.com: Fix commit title by adding ' dts:'] Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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