arm64: dts: marvell: keep SMMU disabled by default for Armada 7040 and 8040

FW has to configure devices' StreamIDs so that SMMU is able to lookup
context and do proper translation later on. For Armada 7040 & 8040 and
publicly available FW, most of the devices are configured properly,
but some like ap_sdhci0, PCIe, NIC still remain unassigned which
results in SMMU faults about unmatched StreamID (assuming
ARM_SMMU_DISABLE_BYPASS_BY_DEFAUL=y).

Since there is dependency on custom FW let SMMU be disabled by default.
People who still willing to use SMMU need to enable manually and
use ARM_SMMU_DISABLE_BYPASS_BY_DEFAUL=n (or via kernel command line)
with extra caution.

Fixes: 83a3545d9c37 ("arm64: dts: marvell: add SMMU support")
Cc: <stable@vger.kernel.org> # 5.9+
Signed-off-by: Tomasz Nowicki <tn@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

arm64: dts: marvell: add SMMU support

Add IOMMU node for Marvell AP806 based SoCs together with platform
and PCI device Stream ID mapping.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Signed-off-by: Tomasz Nowicki <tn@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

arm64: dts: marvell: use SPDX-License-Identifier for Armada SoCs

Follow the recent trend for the license description, and also fix the
wrongly stated X11 to MIT.

As already pointed on the DT ML, the X11 license text [1] is explicitly
for the X Consortium and has a couple of extra clauses. The MIT
license text [2] is actually what the current DT files claim.

[1] https://spdx.org/licenses/X11.html
[2] https://spdx.org/licenses/MIT.html

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

arm64: dts: marvell: replace cpm by cp0, cps by cp1

In preparation for the introduction of more than 2 CPs in upcoming
SoCs, it makes sense to move away from the "CP master" (cpm) and "CP
slave" (cps) naming, and use instead cp0/cp1.

This commit is the result of:

sed 's%cpm%cp0g%' arch/arm64/boot/dts/marvell/*
sed 's%cps%cp1g%' arch/arm64/boot/dts/marvell/*

So it is a purely mechaninal change.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Suggested-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

arm64: dts: marvell: add pinctrl support for Armada 7K/8K

Enable pinctrl support for CP and AP on the Armada 7K/8K SoCs.

The CP master being different between Armada 7k and Armada 8k. This
commit introduces the intermediates files armada-70x0.dtsi and
armada-80x0.dtsi.

These new files will provide different compatible strings depending of
the SoC family. They will also be the location for the pinmux
configuration at the SoC level.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

arm64: dts: marvell: add RTC description for Armada 7K/8K

This RTC IP is found in the CP110 master and slave which are part of the
Armada 8K SoCs and of the subset family the Armada 7K.

There is one RTC in each CP but the RTC requires an external
oscillator. However on the Armada 80x0, the RTC clock in CP master is not
connected (by package) to the oscillator. So this one is disabled for the
Armada 8020 and the Armada 8040.

As the RTC clock in CP slave is connected to the oscillator this one is
let enabled. and will be used on these SoCs (80x0).

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

arm64: dts: marvell: add description for the slave CP110 in Armada 8K

The Armada 8K platforms (8020 and 8040) have two CP110 HW blocks: one
master, one slave. So far, only the master CP110 was described. This
commit adds the Device Tree description for the slave CP110, and hooks
it up in the DT description of the Armada 8020 and Armada 8040 SoCs.

The slave CP110 description is somewhat similar to the master CP110
description except for a number of things like register offsets,
interrupt numbers, references to clocks, etc.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

arm64: dts: marvell: initial DT description of Armada 7K/8K CP110 master

This commit adds an initial Device Tree description for the CP110
master that is found in the Armada 7K and 8K SoCs. This initial
description describes:

- the system controller (to provide clocks)
- three PCIe interfaces
- the SATA interface
- the I2C controllers
- the SPI controllers

For the record, the organization of the SoCs is as follows:

- 7020: dual-core AP, one CP110 (master)
- 7040: quad-core AP, one CP110 (master)
- 8020: dual-core AP, two CP110s (master and slave)
- 8040: quad-core AP, two CP110s (master and slave)

For this reason, all of the 7020, 7040, 8020 and 8040 include
armada-cp110-master.dtsi. When support for the second CP110 (slave)
used in 8020 and 8040 will be added, the .dtsi files for those SoCs
will in addition include armada-cp110-slave.dtsi.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

arm64: dts: marvell: add Device Tree files for Armada 7K/8K

This commit adds the base Device Tree files for the Armada 7K and 8K
SoCs, as well as the Armada 8040 DB board.

The Armada 7020, 7040 (7K family) and 8020, 8040 (8K family) are
composed of:

- An AP806 block that contains the CPU core and a few basic
peripherals. The AP806 is available in dual core configurations
(used in 7020 and 8020) and quad core configurations (used in 8020
and 8040).

- One or two CP110 blocks that contain all the high-speed interfaces
(SATA, PCIe, Ethernet, etc.). The 7K family chips have one CP110,
and the 8K family chips have two CP110, giving them twice the
number of HW interfaces.

In order to represent this from a Device Tree point of view, this
commit creates the following hierarchy:

* armada-ap806.dtsi - definitions common to dual/quad ap806
* armada-ap806-dual.dtsi - description of the two CPUs
* armada-7020.dtsi - description of the 7020 SoC
* armada-8020.dtsi - description of the 8020 SoC
* armada-ap806-quad.dtsi - description of the four CPUs
* armada-7040.dtsi - description of the 7040 SoC
* armada-7040-db.dts - description of the 7040 board
* armada-8040.dtsi - description of the 8040 SoC

The CP110 blocks are not described yet, and will be part of future
patch series.

[gregory.clement@free-electrons.com: Fix commit title by adding ' dts:']
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>