arm64: dts: ls1012a: Add serial alias for ls1012a-rdb

U-boot atempts to read serial alias value for ls1012a-rdb but couldn't
do so as it is not initialised and thus, FDT_ERR_NOTFOUND error is
reported while booting linux.

Loading fdt from FIT Image at a0000000 ...
Description: ls1012ardb-dtb
Type: Flat Device Tree
Data Start: 0xab111474
Data Size: 11285 Bytes = 11 KiB
Architecture: AArch64
Load Address: 0x90000000
Loading fdt from 0xab111474 to 0x90000000
Booting using the fdt blob at 0x90000000
Uncompressing Kernel Image
Loading Device Tree to 000000008fffa000, end 000000008ffffc14 ... OK
WARNING: fdt_fixup_stdout: could not read serial0 alias: FDT_ERR_NOTFOUND
NOTICE: RNG: INSTANTIATED

Starting kernel ...

Fix the above error by specifying serial value to duart.

Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

arm64: dts: fsl-ls1012a-rdb: add i2c devices

LS1012A-RDB equipped in some i2c devices:
- 3x GPIO Expander: PCAL9555A (NXP)
- Gyro: FXAS21002 (NXP)
- Accelerometer: FXOS8700 (NXP)
- Current & Power Monitor: INA220 (TI)

This patch add listed devices to dts.

Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

arm64: dts: freescale: use fixed index mmcN for NXP layerscape reference boards

The eSDHC driver has converted to use asynchronous probe.
Let's use fixed index mmcN for eSDHC controllers, so that
we can ignore the effect on usage, and avoid problem on
previous use cases with fixed index mmcblkN.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

arm64: dts: ls1012a: Add QSPI node properties

Add support for QSPI on NXP layerscape LS1012A-RDB, LS1012A-QDS,
LS1012A-FRDM and LS1012A-FRWY boards.

LS1012A-RDB has 2 Spansion "s25fs512s" flashes of size 64M each and only
one can be accessed at a time.
LS1012A-QDS/FRDM has 1 spansion "s25fs512s" flash of size 64M.
LS1012A-FRWY has one winbond "w25q16dw" flash of size 2M.

Use generic compatibles as "jedec,spi-nor" for automatic detection of
flash. Configure RX and TX buswidth values as 2 as only two I/O lines are
available for data transfer.

Add ls1012a(si) node alongwith flash nodes.

Signed-off-by: Ashish Kumar <Ashish.kumar@nxp.com>
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

arm64: dts: freescale: Update to use SPDX identifiers

Replace license text with corresponding SPDX identifiers and update the
format of existing SPDX identifiers to follow the new guideline
Documentation/process/license-rules.rst.

Note that some of the files mentioned X11 license previously but the
license text actually matches MIT license.

Signed-off-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

arm64: dts: ls1012a: add eSDHC nodes

There are two eSDHC controllers in LS1012A. This patch is to add
eSDHC nodes for ls1012a dts. Also enable eSDHC for RDB/QDS boards.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

arm64: dts: freescale: update the copyright claims

Update the copyright claims to comply with company policy.

Signed-off-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

arm64: dts: updated sata node on ls1012a platform

Updated sata node to add ecc register address and dma coherence
property.
Enable sata on ls1012a platforms as well.

Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

arm64: dts: Add support for FSL's LS1012A SoC

LS1012A features an advanced 64-bit ARM v8 CortexA53 processor
with 32 KB of parity protected L1-I cache, 32 KB of ECC protected
L1-D cache, as well as 256 KB of ECC protected L2 cache.

Features summary
One 64-bit ARM-v8 Cortex-A53 core with the following capabilities
- Arranged as a cluster of one core supporting a 256 KB L2 cache with ECC
protection
- Speed up to 800 MHz
- Parity-protected 32 KB L1 instruction cache and 32 KB L1 data cache
- Neon SIMD engine
- ARM v8 cryptography extensions
One 16-bit DDR3L SDRAM memory controller
ARM core-link CCI-400 cache coherent interconnect
Cryptography acceleration (SEC)
One Configurable x3 SerDes
One PCI Express Gen2 controller, supporting x1 operation
One serial ATA (SATA Gen 3.0) controller
One USB 3.0/2.0 controller with integrated PHY

Following levels of DTSI/DTS files have been created for the LS1012A
SoC family:

- fsl-ls1012a.dtsi:
DTS-Include file for FSL LS1012A SoC.

- fsl-ls1012a-frdm.dts:
DTS file for FSL LS1012A FRDM board.

- fsl-ls1012a-qds.dts:
DTS file for FSL LS1012A QDS board.

- fsl-ls1012a-rdb.dts:
DTS file for FSL LS1012A RDB board.

Signed-off-by: Harninder Rai <harninder.rai@nxp.com>
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>