History log of /linux-master/arch/arm64/boot/dts/bitmain/bm1880.dtsi
Revision Date Author Comments
# 0b137caa 12-Jul-2023 Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

arm64: dts: bitmain: lowercase unit addresses

Unit addresses are expected to be lower case. Pointed also by W=1
builds:

Warning (simple_bus_reg): /soc/serial@5801A000: simple-bus unit address format error, expected "5801a000"

Link: https://lore.kernel.org/r/20230712074611.35952-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


# 43ffe817 10-Dec-2020 Jisheng Zhang <Jisheng.Zhang@synaptics.com>

arm64: dts: bitmain: Use generic "ngpios" rather than "snps,nr-gpios"

This is to remove similar errors as below:

OF: /.../gpio-port@0: could not find phandle

Commit 7569486d79ae ("gpio: dwapb: Add ngpios DT-property support")
explained the reason of above errors well and added the generic
"ngpios" property, let's use it.

Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20201210094056.54553-1-manivannan.sadhasivam@linaro.org'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>


# dee0be5c 13-Jan-2020 Manivannan Sadhasivam <mani@kernel.org>

arm64: dts: bitmain: Source common clock for UART controllers

Remove fixed clock and source common clock for UART controllers.

Link: https://lore.kernel.org/r/20200114040311.6599-3-manivannan.sadhasivam@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>


# e1cd7b80 13-Jan-2020 Manivannan Sadhasivam <mani@kernel.org>

arm64: dts: bitmain: Add clock controller support for BM1880 SoC

Add clock controller support for Bitmain BM1880 SoC.

Link: https://lore.kernel.org/r/20200114040311.6599-2-manivannan.sadhasivam@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>


# ca33f735 16-May-2019 Manivannan Sadhasivam <mani@kernel.org>

arm64: dts: bitmain: Modify pin controller memory map

Earlier, the PWM registers were included as part of the pinctrl memory
map, but this turned to be useless as the muxing is being handled by the
SoC pin controller itself. Hence, this commit removes the pwm register
mapping from the pinctrl node to make it more clean.

Fixes: af2ff87de413 ("arm64: dts: bitmain: Add pinctrl support for BM1880 SoC")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>


# 7d545e77 03-Aug-2019 Manivannan Sadhasivam <mani@kernel.org>

arm64: dts: bitmain: Add reset controller support for BM1880 SoC

Add reset controller support for Bitmain BM1880 SoC. This commit also
adds reset support to UART peripherals.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>


# c1294fb5 24-Apr-2019 Manivannan Sadhasivam <mani@kernel.org>

arm64: dts: bitmain: Add pinctrl support for BM1880 SoC

Add pinctrl support for Bitmain BM1880 SoC. This SoC only supports
pinmuxing and the pinctrl registers are part of the sctrl block.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>


# 367e5927 26-Feb-2019 Manivannan Sadhasivam <mani@kernel.org>

arm64: dts: bitmain: Add GPIO support for BM1880 SoC

Add GPIO support for Bitmain BM1880 SoC based on Designware APB GPIO
controller IP. IP exposes 3 GPIO controllers with a total of 72 pins.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>


# c8ec3743 25-Jan-2019 Manivannan Sadhasivam <mani@kernel.org>

arm64: dts: bitmain: Add BM1880 SoC support

Add devicetree support for Bitmain BM1880 SoC, consisting of a Dual
core ARM Cortex A53 subsystem, a Single core RISC-V subsystem and a Tensor
Processor subsystem. Only ARM Cortex A53 Application processor subsystem
support is enabled for now.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>