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67327f12 |
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06-Dec-2022 |
Asahi Lina <lina@asahilina.net> |
arm64: dts: apple: t6002: Fix GPU power domains On t6002 (M1 Ultra), each die contains a self-contained GPU block. However, only the coprocessor and global management circuitry of the first die are used. This is what is represented by the "gpu" PS (the one in die1 is disabled). Nonetheless, this shared component drives the processing blocks in both dies, and therefore depends on the AFR fabric being powered up on both dies. Add an explicit dependency from the GPU block on die0 to AFR on die1, next to the existing die0 AFR dependency. Fixes: fa86294eb355 ("arm64: dts: apple: Add initial t6000/t6001/t6002 DTs") Signed-off-by: Asahi Lina <lina@asahilina.net> Reviewed-by: Janne Grunau <j@jannau.net> Signed-off-by: Hector Martin <marcan@marcan.st>
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d32c1530 |
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15-Feb-2022 |
Hector Martin <marcan@marcan.st> |
arm64: dts: apple: Add CPU topology & cpufreq nodes for t600x Add the missing CPU topology/capacity information and the cpufreq nodes, so we can have CPU frequency scaling and the scheduler has the information it needs to make the correct decisions. As with t8103, boost states are commented out pending PSCI/etc support for deep sleep states. Reviewed-by: Sven Peter <sven@svenpeter.dev> Signed-off-by: Hector Martin <marcan@marcan.st>
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83fb5b55 |
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22-Nov-2022 |
Rob Herring <robh@kernel.org> |
arm64: dts: apple: Add t600x L1/L2 cache properties and nodes The t600x CPU nodes are missing the cache hierarchy information. The cache hierarchy on Arm can not be detected and needs to be described in DT. The OS scheduler can make use of this information for scheduling decisions. The cache size information is based on various articles about the processors. There's also an L3 system level cache (SLC). It's not described here because SLCs typically have some MMIO interface which would need to be described. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Hector Martin <marcan@marcan.st>
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7b0b0191 |
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16-Sep-2022 |
Hector Martin <marcan@marcan.st> |
arm64: dts: apple: Add initial t6000/t6001/t6002 DTs These SoCs are found in Apple devices with M1 Pro (t6000), M1 Max (t6001) and M1 Ultra (t6002). t6000 is a cut-down version of t6001, so the former just includes the latter and disables the missing bits (This is currently just one PMGR node and all of its domains. t6002 is two connected t6001 dies. The implementation seems to use t6001 with blocks disabled (mostly on the second die). MMIO addresses on the second die have a constant offset. The interrupt controller is multi-die aware. This setup can be represented in the device tree with two top level "soc" nodes. The MMIO offset is applied via "ranges" and devices are included with preproceesor macros to make the node labels unique and to specify the die number for the interrupt definition. Device nodes are distributed over dtsi files based on whether they are present on both dies or just on the first die. The only execption is the NVMe controller which resides on the second die. Its nodes are in a separate file. Co-developed-by: Janne Grunau <j@jannau.net> Signed-off-by: Janne Grunau <j@jannau.net> Acked-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Hector Martin <marcan@marcan.st>
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