arm/arm64: dts: Drop "arm,armv8-pmuv3" compatible usage

The "arm,armv8-pmuv3" compatible is intended only for s/w models. Primarily,
it doesn't provide any detail on uarch specific events.

There's still remaining cases for CPUs without any corresponding PMU
definition and for big.LITTLE systems which only have a single PMU node
(there should be one per core type).

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Acked-by: Dinh Nguyen <dinguyen@kernel.org>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Bjorn Andersson <andersson@kernel.org>
Acked-by: Florian Fainelli <florian.fainelli@broadcom.com>
Acked-by: Alim Akhtar <alim.akhtar@samsung.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Link: https://lore.kernel.org/r/20240417203853.3212103-1-robh@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

arm64: dts: socfpga: stratix10: add unit address to soc node

The "soc" node has ranges with addresses, so it is should have unit
address to fix dtc W=1 warnings like:

socfpga_stratix10.dtsi:128.6-636.4: Warning (unit_address_vs_reg): /soc: node has a reg or ranges property, but no unit name

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

arm64: dts: socfpga: stratix10: move firmware out of soc node

The "soc" node is supposed to have only MMIO children, so move the
firmware/svc node to top level to fix dtc W=1 warnings like:

socfpga_stratix10.dtsi:625.12-635.5: Warning (simple_bus_reg): /soc@0/firmware: missing or empty reg/ranges property

The node should still be instantiated by drivers/of/platform.c, just
like in all other platforms.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

arm64: dts: socfpga: stratix10: move FPGA region out of soc node

The "soc" node is supposed to have only MMIO children, so move the FPGA
region node to top level to fix dtc W=1 warnings like:

socfpga_stratix10.dtsi:136.20-141.5: Warning (simple_bus_reg): /soc@0/base_fpga_region: missing or empty reg/ranges property

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

arm64: dts: socfpga: stratix10: add clock-names to DWC2 USB

The DWC2 USB bindings require clock-names property, to provide such to
fix warnings like:

socfpga_stratix10_swvp.dtb: usb@ffb40000: 'clock-names' is a required property

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

arm64: dts: socfpga: change the reset-name of "stmmaceth-ocp" to "ahb"

The "stmmaceth-ocp" reset line on the SoCFPGA stmmac ethernet driver is
the same as the "ahb" reset on a standard stmmac ethernet.

commit ("843f603762a5 dt-bindings: net: snps,dwmac: Add 'ahb'
reset/reset-name") documented the second reset signal as 'ahb' instead
of 'stmmaceth-ocp'. Change the reset-names of the SoCFPGA DWMAC driver to
'ahb'. In order not to break ABI, we will keep support in thedwmac-socfpga
driver to still make use of "stmmaceth-ocp".

This also fixes the dtbs_check warning:
ethernet@ff802000: reset-names:1: 'ahb' was expected

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v2: update commit message to further describe the reason for the change

arm64: dts: socfpga: stratix10: fix dtbs_check warning for usbphy

soc: usbphy@0: 'anyOf' conditional failed, one must be fixed:

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

arm64: dts: socfpga: agilex/stratix10: fix dtbs_check warnings for sram

sram@ffe00000: 'ranges' is a required property
sram@ffe00000: '#size-cells' is a required property
sram@ffe00000: '#address-cells' is a required property

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

arm64: dts: socfpga: change address-cells to support 64-bit addressing

Update the address-cells and size-cells to 2 in order to support 64-bit
addressing.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

arm64: dts: add pinctrl-single property for Stratix10/Agilex

The Stratix10/Agilex has a pin control IP that can make use of the
pinctrl-single driver.

Add the pinctrl-single dts property for the Stratix10/Agilex
platforms.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v2: no changes

arm64: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node

The sdmmc controller's CIU(Card Interface Unit) clock's phase can be
adjusted through the register in the system manager. Add the binding
"altr,sysmgr-syscon" to the SDMMC node for the driver to access the
system manager. Add the "clk-phase-sd-hs" property in the SDMMC node to
designate the smpsel and drvsel properties for the CIU clock.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

arm64: dts: altera: socfpga_stratix10: move clocks out of soc node

The clocks are not part of the SoC but provided on the board
(external oscillators). Moving them out of soc node.

Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

arm64: dts: altera: adjust whitespace around '='

Fix whitespace coding style: use single space instead of tabs or
multiple spaces around '=' sign in property assignment. No functional
changes (same DTB).

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

arm64: dts: stratix10/agilex: drop useless 'dma-channels/requests' properties

The pl330 DMA controller provides number of DMA channels and requests
through its registers, so duplicating this information (with a chance of
mistakes) in DTS is pointless. Additionally the DTS used always wrong
property names which causes DT schema check failures - the bindings
documented 'dma-channels' and 'dma-requests' properties without leading
hash sign.

Reported-by: Rob Herring <robh@kernel.org>
Suggested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220430121902.59895-4-krzysztof.kozlowski@linaro.org

arm64: dts: agilex/stratix10: add clock-names to USB DWC2 node

USB DWC2 requires clock-names:

arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dt.yaml:
usb@ffb00000: 'clock-names' is a required property

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

arm64: dts: stratix10: align pl330 node name with dtschema

Fixes dtbs_check warnings like:

pdma@ffda0000: $nodename:0: 'pdma@ffda0000' does not match '^dma-controller(@.*)?$'

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

arm64: dts: stratix10: align mmc node names with dtschema

The Synopsys DW MSHC bindings require node name to be 'mmc':

dwmmc0@ff808000: $nodename:0: 'dwmmc0@ff808000' does not match '^mmc(@.*)?$'

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

arm64: dts: stratix10: move ARM timer out of SoC node

The ARM timer is usually considered not part of SoC node, just like
other ARM designed blocks (PMU, PSCI). This fixes dtbs_check warning:

arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dt.yaml: soc: timer:
{'compatible': ['arm,armv8-timer'], 'interrupts': [[1, 13, 3848], [1, 14, 3848], [1, 11, 3848], [1, 10, 3848]]} should not be valid under {'type': 'object'}
From schema: dtschema/schemas/simple-bus.yaml

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

ARM: dts: socfpga: change qspi to "intel,socfpga-qspi"

Because of commit 9cb2ff111712 ("spi: cadence-quadspi: Disable Auto-HW polling"),
which does a write to the CQSPI_REG_WR_COMPLETION_CTRL register
regardless of any condition. Well, the Cadence QuadSPI controller on
Intel's SoCFPGA platforms does not implement the
CQSPI_REG_WR_COMPLETION_CTRL register, thus a write to this register
results in a crash!

So starting with v5.16, I introduced the patch
98d948eb833 ("spi: cadence-quadspi: fix write completion support"),
which adds the dts compatible "intel,socfpga-qspi" that is specific for
versions that doesn't have the CQSPI_REG_WR_COMPLETION_CTRL register implemented.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v3: revert back to "intel,socfpga-qspi"
v2: use both "cdns,qspi-nor" and "cdns,qspi-nor-0010"

arm64: dts: socfpga: Use generic "ngpios" rather than "snps,nr-gpios"

This is to remove similar errors as below:

OF: /.../gpio-port@0: could not find phandle

Commit 7569486d79ae ("gpio: dwapb: Add ngpios DT-property support")
explained the reason of above errors well and added the generic
"ngpios" property, let's use it.

Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

arm64: dts: stratix10/agilex: add the ptp_ref clock

Add the ptp_ref clock for the GMACs.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

arm: dts: socfpga: add reset-names to spi node

Add reset-names = "spi" to spi dts nodes.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

arm64: dts: spcfpga: Align GIC, NAND and UART nodenames with dtschema

Fix dtschema validator warnings like:
intc@fffc1000: $nodename:0:
'intc@fffc1000' does not match '^interrupt-controller(@[0-9a-f,]+)*$'

Fixes: 78cd6a9d8e15 ("arm64: dts: Add base stratix 10 dtsi")
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

arm64: dts: agilex/stratix10: fix pmu interrupt numbers

Fix up the correct interrupt numbers for the PMU unit on Agilex
and Stratix10.

Fixes: 78cd6a9d8e15 ("arm64: dts: Add base stratix 10 dtsi")
Cc: linux-stable <stable@vger.kernel.org>
Reported-by: Meng Li <Meng.Li@windriver.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

arm64: dts: stratix10: Add NAND device node

Add the NAND device node to the base Stratix10 DTS.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

arm64: dts: agilex/stratix10: Add reset properties for DMA

Add both the reset and reset-ocp properties for the DMA node on the
Stratix10 and Agilex platforms.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

arm64: dts: stratix10: Add OCRAM EDAC node

Add the OCRAM ECC node with Stratix10 compatible string.

Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Acked-by: Dinh Nguyen <dinguyen@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: James Morse <james.morse@arm.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: mchehab@kernel.org
Cc: Rob Herring <robh+dt@kernel.org>
Link: https://lkml.kernel.org/r/1556030197-24534-3-git-send-email-thor.thayer@linux.intel.com

arm64: dts: stratix10: use the "altr,socfpga-stmmac-a10-s10" binding

Because of register and bits difference for setting PHY modes, PTP reference
clock, and FPGA signalling, the Stratix10 SoC needs to use the
"altr,socfpga-stmmac-a10-s10" binding to set the correct modes.

On Stratix10, each EMAC has its own register for PHY modes, and they all have
the same offset, thus we can use the 2nd parameter to specify the offsets
for the FPGA signal bits.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201

Based on 1 normalized pattern(s):

this program is free software you can redistribute it and or modify
it under the terms and conditions of the gnu general public license
version 2 as published by the free software foundation this program
is distributed in the hope it will be useful but without any
warranty without even the implied warranty of merchantability or
fitness for a particular purpose see the gnu general public license
for more details you should have received a copy of the gnu general
public license along with this program if not see http www gnu org
licenses

extracted by the scancode license scanner the SPDX license identifier

GPL-2.0-only

has been chosen to replace the boilerplate/reference in 228 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Steve Winslow <swinslow@gmail.com>
Reviewed-by: Richard Fontana <rfontana@redhat.com>
Reviewed-by: Alexios Zavras <alexios.zavras@intel.com>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190528171438.107155473@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

arm64: dts: stratix10: Use new Stratix10 EDAC bindings

Use the new Stratix10 binding format for EDAC nodes.

Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Acked-by: Dinh Nguyen <dinguyen@kernel.org>
Cc: James Morse <james.morse@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: mark.rutland@arm.com
Cc: mchehab@kernel.org
Link: https://lkml.kernel.org/r/1554388597-28019-4-git-send-email-thor.thayer@linux.intel.com

arm64: dts: stratix10: New System Manager compatible

Use the new compatible string defined for the Stratix10
System Manager. Remove syscon since it is not correct
on this platform.

Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Lee Jones <lee.jones@linaro.org>

arm64: dts: stratix10: add the sysmgr-syscon property from the gmac's

The gmac ethernet driver uses the "altr,sysmgr-syscon" property to
configure phy settings for the gmac controller.

Add the "altr,sysmgr-syscon" property to all gmac nodes.

This patch fixes:

[ 0.917530] socfpga-dwmac ff800000.ethernet: No sysmgr-syscon node found
[ 0.924209] socfpga-dwmac ff800000.ethernet: Unable to parse OF data

Cc: stable@vger.kernel.org
Reported-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

arm64: dts: Remove inconsistent use of 'arm,armv8' compatible string

The 'arm,armv8' compatible string is only for software models. It adds
little value otherwise and is inconsistently used as a fallback on some
platforms. Remove it from those platforms.

This fixes warnings generated by the DT schema.

Reported-by: Michal Simek <michal.simek@xilinx.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Acked-by: Antoine Tenart <antoine.tenart@bootlin.com>
Acked-by: Nishanth Menon <nm@ti.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Chanho Min <chanho.min@lge.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Wei Xu <xuwei5@hisilicon.com>
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Scott Branden <scott.branden@broadcom.com>
Acked-by: Kevin Hilman <khilman@baylibre.com>
Acked-by: Chunyan Zhang <zhang.lyra@gmail.com>
Acked-by: Robert Richter <rrichter@cavium.com>
Acked-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Acked-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

arm64: dts: stratix10: Add Stratix10 SMMU support

Now there are device tree clocks for the ARM64 SMMU,
add SMMU support to the Stratix10 Device Tree which
includes adding the SMMU node and adding IOMMU stream
ids to the SMMU peripherals.

Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

arm64: dts: stratix10: use "altr,stratix10-rst-mgr" binding

The standard reset-simple driver the uses the "altr,rst-mgr" binding is
not getting initialized early enough in the boot process, so timers
that the kernel needs are still left in reset. Thus an early
reset driver was created. This early reset driver is only for the
SoCFPGA 32-bit platform.

The Stratix10 platform does not need any of the timers that in reset to
boot, thus we don't need to early reset driver. Therefore, use the
"altr,stratix10-rst-mgr" binding for the reset-simple platform driver on
the Stratix10 platform.

Also remove the "altr,modrst-offset" property because the driver no
longer needs it.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

arm64: dts: stratix10: add fpga manager and region

Add the Stratix10 FPGA manager and a FPGA region to the
device tree.

Signed-off-by: Alan Tull <atull@kernel.org>
Signed-off-by: Richard Gong <richard.gong@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

arm64: dts: stratix10: add stratix10 service driver binding to base dtsi

Add Intel Stratix10 service layer to the device tree

Signed-off-by: Richard Gong <richard.gong@intel.com>
Signed-off-by: Alan Tull <atull@kernel.org>
Acked-by: Moritz Fischer <mdf@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

arm64: dts: stratix10: fix multicast filtering

On Stratix 10, the EMAC has 256 hash buckets for multicast filtering. This
needs to be specified in DTS, otherwise the stmmac driver defaults to 64
buckets and initializes the filter incorrectly. As a result, e.g. valid
IPv6 multicast traffic ends up being dropped.

Fixes: 78cd6a9d8e15 ("arm64: dts: Add base stratix 10 dtsi")
Cc: stable@vger.kernel.org
Signed-off-by: Aaro Koskinen <aaro.koskinen@nokia.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

arm64: dts: stratix10: Support Ethernet Jumbo frame

Properly specify the RX and TX FIFO size which is important
for Jumbo frames.
Update the max-frame-size to support Jumbo frames.

Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

arm64: dts: stratix10: Correct System Manager register size

Correct the register size of the System Manager node.

Cc: stable@vger.kernel.org
Fixes: 78cd6a9d8e154 ("arm64: dts: Add base stratix 10 dtsi")
Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

arm64: dts: stratix10: Add peripheral EDAC nodes

Add the usb and ethernet peripheral ECC nodes using the rria10 format.

Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Acked-by: Dinh Nguyen <dinguyen@kernel.org>
Cc: robh+dt@kernel.org
Cc: mark.rutland@arm.com
Cc: mchehab@kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-edac@vger.kernel.org
Link: https://lkml.kernel.org/r/1537883342-30180-7-git-send-email-thor.thayer@linux.intel.com

arm64: dts: stratix10: Add SDRAM node

Add the SDRAM node to follow the Arria10 layout and bindings. The
Arria10 SDRAM functions expect this node.

Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Acked-by: Dinh Nguyen <dinguyen@kernel.org>
Cc: robh+dt@kernel.org
Cc: mark.rutland@arm.com
Cc: mchehab@kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-edac@vger.kernel.org
Link: https://lkml.kernel.org/r/1537883342-30180-4-git-send-email-thor.thayer@linux.intel.com

arm64: dts: stratix10: Additions to EDAC System Manager

Add the phandle, address, size and ranges to the Stratix10 System
Manager node to match the existing Arria10 EDAC implementation.

Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Acked-by: Dinh Nguyen <dinguyen@kernel.org>
Cc: robh+dt@kernel.org
Cc: mark.rutland@arm.com
Cc: mchehab@kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-edac@vger.kernel.org
Link: https://lkml.kernel.org/r/1537883342-30180-2-git-send-email-thor.thayer@linux.intel.com

arm64: dts: stratix10: Add SPI node clocks for Stratix10

Add the required clocks for the new Stratix10 clock bindings
to the SPI nodes.

Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

arm64: dts: stratix10: add OCP reset property for ethernet

Add the additional OCP reset property for the ethernet nodes.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

arm64: dts: stratix10: fill in clocks field for usb and watchdog

Populate the clocks field for USB and watchdog.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

arm64: dts: stratix10: Add QSPI support for Stratix10

Add qspi_clock
The qspi_clk frequency is updated by U-Boot before starting Linux.
Add QSPI interface node.
Add QSPI flash memory child node.
Setup the QSPI memory in 2 partitions.

Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

arm64: dts: stratix10: Fix SPI nodes for Stratix10

Remove the unused bus-num node and change num-chipselect
to num-cs to match SPI bindings.

Cc: stable@vger.kernel.org
Fixes: 78cd6a9d8e154 ("arm64: dts: Add base stratix 10 dtsi")
Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Olof Johansson <olof@lixom.net>

arm64: dts: stratix10: add sdram ecc

Add the Stratix10 ECC Manager and SDRAM EDAC nodes to the
device tree.

Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

arm64: dts: stratix10: Add PL330 DMAC to Stratix10 dts

The Stratix10 SoCFPGA uses the PL330 DMAC. This patch adds the PL330
DMAC to the Stratix10 device tree.

Signed-off-by: Graham Moore <graham.moore@linux.intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

arm64: dts: stratix10: enable i2c, add i2c periperals

Add clock for i2c
Enable i2c1
Set the i2c bus speed to 100KHz
Add the following i2c peripherals
* ds1339 RTC
* 24c32 EEPROM
* max1619 temperature monitor
* ltc2497 ADC
* Add a fixed regulator for the ADC's Vref.

This requires Dinh Nguyen's Stratix10 clock driver
("clk: socfpga: stratix10: add clock driver for Stratix10 platform")

Signed-off-by: Alan Tull <atull@kernel.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

arm64: dts: stratix10: use clock bindings for the Stratix10 platform

Use the clock bindings for the Stratix10 SoC. This includes changing the old
binding of "intc,clk-s10-mgr" to "intel,stratix10-clkmgr". The reason that
this can be done is that there are currently no clock driver for Stratix10,
thus there are no consumers of the old binding. So changing the binding will
not break any legacy code.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v7:
- move PLL out of clkmgr node and into DT root
v6:
- no changes
v5:
- no changes
v4:
- remove '_' in name of clock nodes
- use clock-controller in SoCDK node in dts file
v3:
- use the correct vendor prefix
- explain the binding change
v2:
- use a single clock binding for the clock controller

arm64: dts: stratix10: fix SPI settings

Correct the SPI Master node settings.

Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

arm64: dts: stratix10: add USB ECC reset bit

The USB IP on the Stratix10 SoC needs the USB OCP(ecc) bit to get de-asserted
as well for the USB IP to work properly.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

arm64: dts: socfpga: add missing interrupt-parent

The PMU node has no working interrupt, as shown by this dtc warning:

arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dtb: Warning (interrupts_property): Missing interrupt-parent for /pmu

This adds an interrupt-parent property so we can correct parse
that interrupt number.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Olof Johansson <olof@lixom.net>

arm64: dts: stratix10: fix interrupt number for gpio1

The gpio1 node's interrupt number should be 111.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

arm64: dts: stratix10: add gpio header

Add the gpio header to the base stratix10 dtsi.

Signed-off-by: Alan Tull <atull@kernel.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

arm64: dts: stratix10: add reset property for various peripherals

Add reset property for emac, gpio, i2c, sdmmc, timers, and watchdog.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

arm64: dts: stratix10: add the 'altr,modrst-off' property

Update the Stratix10 reset manager with the 'altr,modrst-offset' property.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

arm64: dts: stratix10: include the reset manager bindings

Add the reset manager includes for Stratix10. Need to use the '#include'
instead of '/include/' to avoid a DTC syntax error.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

arm64: dts: stratix10: fix up the gic register for the Stratix10 platform

The register entries for the ARM GIC-400 should have a 2nd set of address.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

arm64: dts: Fix broken architected timer interrupt trigger

The ARM architected timer specification mandates that the interrupt
associated with each timer is level triggered (which corresponds to
the "counter >= comparator" condition).

A number of DTs are being remarkably creative, declaring the interrupt
to be edge triggered. A quick look at the TRM for the corresponding ARM
CPUs clearly shows that this is wrong, and I've corrected those.
For non-ARM designs (and in the absence of a publicly available TRM),
I've made them active low as well, which can't be completely wrong
as the GIC cannot disinguish between level low and level high.

The respective maintainers are of course welcome to prove me wrong.

While I was at it, I took the liberty to fix a couple of related issue,
such as some spurious affinity bits on ThunderX, and their complete
absence on ls1043a (both of which seem to be related to copy-pasting
from other DTs).

Acked-by: Duc Dang <dhdang@apm.com>
Acked-by: Carlo Caione <carlo@endlessm.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

arm64: dts: Add base stratix 10 dtsi

Add the base DTS for Altera's SoCFPGA Stratix 10 platform.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
v4: Add a non-zero ranges property for /soc node
v3: change #address-cells and #size-cells to <2>
change the GIC address to 0xfffc1000
update the GIC virtual CPU reg length to 0x2000
v2: use interrupt-affinity for pmu node