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2560cffd |
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07-Dec-2023 |
Linus Walleij <linus.walleij@linaro.org> |
ARM: Delete ARM11MPCore (ARM11 ARMv6K SMP) support This ARM11 SMP configuration was one of the first SMP configurations the ARM kernel supported, but it has the downside of odd DMA handling, odd cache tagging, and often (as of recent) completely broken cache handling on the ARM RealView PB11MPCore test chips. To boot the platform it was necessary to completely disable the cache. When it comes to the EB 11MPCore it is unclear if this ever worked. These reference designs are now the only ARMv6K SMP platforms. As only reference designs of purely academic interest remain, and since the special-cased DMA and PMU code is hard to maintain and doesn't really work, it is not really worth our time. Delete the ARM11MPCore support along with: - The special DMA quirk CONFIG_DMA_CACHE_RWFO that is only used on ARMv6K SMP, and we are the last ARMV6K system leaving the building and the cache handling is awkward, so good-bye. - The special PMU handling that was only used by ARM11MPCore. The following is left behind: - TIMER_OF_DECLARE(arm_twd_11mp, "arm,arm11mp-twd-timer", ...) in arch/arm/kernel/smp_twd.c, this is still in use by Marvell MMP3 arch/arm/boot/dts/marvell/mmp3.dtsi - IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", ...) in drivers/irqchip/irq-gic.c, this is still in use by Marvell MMP3 arch/arm/boot/dts/marvell/mmp3.dtsi - A compatible for the arm11mpcore SCU, since this was mistakedly used for the Cortex-A9 version of RealView EB. These are unfortunate but will need to be kept around for compatibility. New Marvell-specific compatibles should however probably be added. Acked-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Link: https://lore.kernel.org/r/20231207-drop-11mpcore-v2-1-560b396f3bf5@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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#
e318b36e |
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03-May-2023 |
Jonathan Corbet <corbet@lwn.net> |
arm: update in-source documentation references The Arm documentation has moved to Documentation/arch/arm; update references within arch/arm to match. Cc: Russell King <linux@armlinux.org.uk> Cc: Alim Akhtar <alim.akhtar@samsung.com> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: linux-doc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-arch@vger.kernel.org Signed-off-by: Jonathan Corbet <corbet@lwn.net>
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#
252309ad |
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17-Mar-2023 |
Marc Zyngier <maz@kernel.org> |
ARM: Make CONFIG_CPU_V7 valid for 32bit ARMv8 implementations ARMv8 is a superset of ARMv7, and all the ARMv8 features are discoverable with a set of ID registers. It means that we can use CPU_V7 to guard ARMv8 features at compile time. This commit simply amends the CPU_V7 configuration symbol comment to reflect that CPU_V7 also covers ARMv8. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Zaid Al-Bassam <zalbassam@google.com> Tested-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20230317195027.3746949-7-zalbassam@google.com Signed-off-by: Will Deacon <will@kernel.org>
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cfb1076d |
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24-Jan-2023 |
Randy Dunlap <rdunlap@infradead.org> |
ARM: 9288/1: Kconfigs: fix spelling & grammar Fix spelling (reported by codespell) and grammar in Arm Kconfig files. Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Cc: linux-arm-kernel@lists.infradead.org Cc: patches@armlinux.org.uk Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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#
2bf62042 |
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19-Jun-2022 |
Linus Walleij <linus.walleij@linaro.org> |
ARM: 9212/1: domain: Modify Kconfig help text After the removal of set_fs() the reference to set_fs() is stale. Alter the helptext to reflect what the config option really does. Fixes: 8ac6f5d7f84b ("ARM: 9113/1: uaccess: remove set_fs() implementation") Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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5d6f5267 |
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04-Apr-2022 |
Arnd Bergmann <arnd@arndb.de> |
ARM: rework endianess selection Choosing big-endian vs little-endian kernels in Kconfig has not worked correctly since the introduction of CONFIG_ARCH_MULTIPLATFORM a long time ago. The problems is that CONFIG_BIG_ENDIAN depends on ARCH_SUPPORTS_BIG_ENDIAN, which can set by any one platform in the config, but would actually have to be supported by all of them. This was mostly ok for ARMv6/ARMv7 builds, since these are BE8 and tend to just work aside from problems in nonportable device drivers. For ARMv4/v5 machines, CONFIG_BIG_ENDIAN and CONFIG_ARCH_MULTIPLATFORM were never set together, so this was disabled on all those machines except for IXP4xx. As IXP4xx can now become part of ARCH_MULTIPLATFORM, it seems better to formalize this logic: all ARMv4/v5 platforms get an explicit dependency on being either big-endian (ixp4xx) or little-endian (the rest). We may want to fix ixp4xx in the future to support both, but it does not work in LE mode at the moment. For the ARMv6/v7 platforms, there are two ways this could be handled a) allow both modes only for platforms selecting 'ARCH_SUPPORTS_BIG_ENDIAN' today, but only LE mode for the others, given that these were added intentionally at some point. b) allow both modes everwhere, given that it was already possible to build that way by e.g. selecting ARCH_VIRT, and that the list is not an accurate reflection of which platforms may or may not work. Out of these, I picked b) because it seemed slighly more logical to me. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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#
7b9896c3 |
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25-Nov-2021 |
Ard Biesheuvel <ardb@kernel.org> |
ARM: percpu: add SMP_ON_UP support Permit the use of the TPIDRPRW system register for carrying the per-CPU offset in generic SMP configurations that also target non-SMP capable ARMv6 cores. This uses the SMP_ON_UP code patching framework to turn all TPIDRPRW accesses into reads/writes of entry #0 in the __per_cpu_offset array. While at it, switch over some existing direct TPIDRPRW accesses in asm code to invocations of a new helper that is patched in the same way when necessary. Note that CPU_V6+SMP without SMP_ON_UP results in a kernel that does not boot on v6 CPUs without SMP extensions, so add this dependency to Kconfig as well. Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Nicolas Pitre <nico@fluxnic.net> Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Tested-by: Marc Zyngier <maz@kernel.org> Tested-by: Vladimir Murzin <vladimir.murzin@arm.com> # ARMv7M
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#
b9baf5c8 |
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10-Feb-2022 |
Russell King (Oracle) <rmk+kernel@armlinux.org.uk> |
ARM: Spectre-BHB workaround Workaround the Spectre BHB issues for Cortex-A15, Cortex-A57, Cortex-A72, Cortex-A73 and Cortex-A75. We also include Brahma B15 as well to be safe, which is affected by Spectre V2 in the same ways as Cortex-A15. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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#
9dd78194 |
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11-Feb-2022 |
Russell King (Oracle) <rmk+kernel@armlinux.org.uk> |
ARM: report Spectre v2 status through sysfs As per other architectures, add support for reporting the Spectre vulnerability status via sysfs CPU. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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#
8b5bd5ad |
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18-Oct-2021 |
Arnd Bergmann <arnd@arndb.de> |
ARM: 9137/1: disallow CONFIG_THUMB with ARMv4 We can currently build a multi-cpu enabled kernel that allows both ARMv4 and ARMv5 CPUs, and also supports THUMB mode in user space. However, returning to user space in this configuration with the usr_ret macro requires the use of the 'bx' instruction, which is refused by the assembler: arch/arm/kernel/entry-armv.S: Assembler messages: arch/arm/kernel/entry-armv.S:937: Error: selected processor does not support `bx lr' in ARM mode arch/arm/kernel/entry-armv.S:960: Error: selected processor does not support `bx lr' in ARM mode arch/arm/kernel/entry-armv.S:1003: Error: selected processor does not support `bx lr' in ARM mode <instantiation>:2:2: note: instruction requires: armv4t bx lr While it would be possible to handle this correctly in principle, doing so seems to not be worth it, if we can simply avoid the problem by enforcing that a kernel supporting both ARMv4 and a later CPU architecture cannot run THUMB binaries. This turned up while build-testing with clang; for some reason, gcc never triggered the problem. Reviewed-by: Nick Desaulniers <ndesaulniers@google.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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#
345dac33 |
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18-Oct-2021 |
Arnd Bergmann <arnd@arndb.de> |
ARM: 9136/1: ARMv7-M uses BE-8, not BE-32 When configuring the kernel for big-endian, we set either BE-8 or BE-32 based on the CPU architecture level. Until linux-4.4, we did not have any ARMv7-M platform allowing big-endian builds, but now i.MX/Vybrid is in that category, adn we get a build error because of this: arch/arm/kernel/module-plts.c: In function 'get_module_plt': arch/arm/kernel/module-plts.c:60:46: error: implicit declaration of function '__opcode_to_mem_thumb32' [-Werror=implicit-function-declaration] This comes down to picking the wrong default, ARMv7-M uses BE8 like ARMv7-A does. Changing the default gets the kernel to compile and presumably works. https://lore.kernel.org/all/1455804123-2526139-2-git-send-email-arnd@arndb.de/ Tested-by: Vladimir Murzin <vladimir.murzin@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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89a0b011 |
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03-Jun-2021 |
Wang Kefeng <wangkefeng.wang@huawei.com> |
ARM: 9091/1: Revert "mm: qsd8x50: Fix incorrect permission faults" This reverts commit e220ba60223a9d63e70217e5b112160df8c21cea. The VERIFY_PERMISSION_FAULT is introduced since 2009 but no one use it, just revert it and clean unused comment. Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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cc611137 |
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15-Jan-2021 |
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> |
ARM: drop efm32 platform I didn't touch this code since it served as a platform to introduce ARMv7-M support to Linux. The only known machine that runs Linux has only 4 MiB of RAM (that originally only exists to hold the display's framebuffer). There are no known users and no further use foreseeable, so drop the code. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20210115155130.185010-2-u.kleine-koenig@pengutronix.de' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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#
28187dc8 |
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16-Nov-2020 |
Nick Desaulniers <ndesaulniers@google.com> |
ARM: 9025/1: Kconfig: CPU_BIG_ENDIAN depends on !LD_IS_LLD LLD does not yet support any big endian architectures. Make this config non-selectable when using LLD until LLD is fixed. Link: https://github.com/ClangBuiltLinux/linux/issues/965 Signed-off-by: Nick Desaulniers <ndesaulniers@google.com> Tested-by: Nathan Chancellor <natechancellor@gmail.com> Reviewed-by: Nathan Chancellor <natechancellor@gmail.com> Reported-by: kbuild test robot <lkp@intel.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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#
f86fd32d |
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07-Feb-2020 |
Thomas Gleixner <tglx@linutronix.de> |
lib/vdso: Cleanup clock mode storage leftovers Now that all architectures are converted to use the generic storage the helpers and conditionals can be removed. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Reviewed-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Link: https://lkml.kernel.org/r/20200207124403.470699892@linutronix.de
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5e3c6a31 |
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07-Feb-2020 |
Thomas Gleixner <tglx@linutronix.de> |
ARM/arm64: vdso: Use common vdso clock mode storage Convert ARM/ARM64 to the generic VDSO clock mode storage. This needs to happen in one go as they share the clocksource driver. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Reviewed-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Link: https://lkml.kernel.org/r/20200207124403.363235229@linutronix.de
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20e2fc42 |
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04-Nov-2019 |
Vincenzo Frascino <vincenzo.frascino@arm.com> |
ARM: 8930/1: Add support for generic vDSO The arm vDSO library requires some adaptations to take advantage of the newly introduced generic vDSO library. Introduce the following changes: - Modification vdso.c to be compliant with the common vdso datapage - Use of lib/vdso for gettimeofday - Implementation of elf note Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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df8bf2d8 |
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07-Jun-2019 |
Lubomir Rintel <lkundrak@v3.sk> |
ARM: mmp: don't select CACHE_TAUROS2 on all ARCH_MMP MMP3 has a PJ4B with a Tauros 3 cache controller that uses CACHE_L2X0 instead, while CACHE_TAUROS2 is present on PJ4 and PJ1 (Mohawk) based platforms only. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
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#
936376f8 |
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19-Aug-2019 |
Christoph Hellwig <hch@lst.de> |
arm: select the dma-noncoherent symbols for all swiotlb builds We need to provide the arch hooks for non-coherent dma-direct and swiotlb for all swiotlb builds, not just when LPAS is enabled. Without that the Xen build that selects SWIOTLB indirectly through SWIOTLB_XEN fails to build. Fixes: ad3c7b18c5b3 ("arm: use swiotlb for bounce buffering on LPAE configs") Reported-by: Stefan Wahren <wahrenst@gmx.net> Signed-off-by: Christoph Hellwig <hch@lst.de> Tested-by: Stefan Wahren <wahrenst@gmx.net>
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#
c68b2669 |
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09-Aug-2019 |
Arnd Bergmann <arnd@arndb.de> |
ARM: remove ks8695 platform ks8695 is an older SoC originally made by Kendin, which was later acquired by Micrel, and subsequently by Microchip. The platform port was originally contributed by Andrew Victor and Ben Dooks, and later maintained by Greg Ungerer. When I recently submitted cleanups, but Greg noted that the platform no longer boots and nobody is using it any more, we decided to remove it. Link: https://lore.kernel.org/r/20190809202749.742267-2-arnd@arndb.de Cc: Andrew Victor <linux@maxim.org.za> Acked-by: Ben Dooks <ben-linux@fluff.org> Link: https://wikidevi.com/wiki/Micrel Link: https://lore.kernel.org/linux-arm-kernel/2bc41895-d4f9-896c-0726-0b2862fcbf25@kernel.org/ Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Greg Ungerer <gerg@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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#
ad3c7b18 |
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23-Jul-2019 |
Christoph Hellwig <hch@lst.de> |
arm: use swiotlb for bounce buffering on LPAE configs The DMA API requires that 32-bit DMA masks are always supported, but on arm LPAE configs they do not currently work when memory is present above 4GB. Wire up the swiotlb code like for all other architectures to provide the bounce buffering in that case. Fixes: 21e07dba9fb11 ("scsi: reduce use of block bounce buffers"). Reported-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Christoph Hellwig <hch@lst.de> Tested-by: Vignesh Raghavendra <vigneshr@ti.com>
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#
dc7a12bd |
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14-Apr-2019 |
Mauro Carvalho Chehab <mchehab+samsung@kernel.org> |
docs: arm: convert docs to ReST and rename to *.rst Converts ARM the text files to ReST, preparing them to be an architecture book. The conversion is actually: - add blank lines and identation in order to identify paragraphs; - fix tables markups; - add some lists markups; - mark literal blocks; - adjust title markups. At its new index.rst, let's add a :orphan: while this is not linked to the main index.rst file, in order to avoid build warnings. Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org> Reviewed-by Corentin Labbe <clabbe.montjoie@gmail.com> # For sun4i-ss
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#
5f41f919 |
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28-May-2019 |
Marek Szyprowski <m.szyprowski@samsung.com> |
ARM: 8864/1: Add workaround for I-Cache line size mismatch between CPU cores Some big.LITTLE systems have I-Cache line size mismatch between LITTLE and big cores. This patch adds a workaround for proper I-Cache support on such systems. Without it, some class of the userspace code (typically self-modifying) might suffer from random SIGILL failures. Similar workaround already exists for ARM64 architecture. I has been added by commit 116c81f427ff ("arm64: Work around systems with mismatched cache line sizes"). Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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#
cbfc5619 |
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23-Jul-2018 |
Vladimir Murzin <vladimir.murzin@arm.com> |
ARM: 8784/1: NOMMU: Allow enter in Hyp mode ARMv8R adds support for virtualisation extension (with some deviation from v8A). With this patch hyp-unaware boot code can offload to kernel setting up HYP stuff in a sane state. Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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#
06c23f5f |
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20-Apr-2018 |
Russell King <rmk+kernel@armlinux.org.uk> |
ARM: spectre-v2: harden branch predictor on context switches Harden the branch predictor against Spectre v2 attacks on context switches for ARMv7 and later CPUs. We do this by: Cortex A9, A12, A17, A73, A75: invalidating the BTB. Cortex A15, Brahma B15: invalidating the instruction cache. Cortex A57 and Cortex A72 are not addressed in this patch. Cortex R7 and Cortex R8 are also not addressed as we do not enforce memory protection on these cores. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Boot-tested-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Tony Lindgren <tony@atomide.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com>
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#
c58d237d |
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14-May-2018 |
Russell King <rmk+kernel@armlinux.org.uk> |
ARM: spectre: add Kconfig symbol for CPUs vulnerable to Spectre Add a Kconfig symbol for CPUs which are vulnerable to the Spectre attacks. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Boot-tested-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Tony Lindgren <tony@atomide.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com>
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#
4965a687 |
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03-Apr-2018 |
Christoph Hellwig <hch@lst.de> |
arch: define the ARCH_DMA_ADDR_T_64BIT config symbol in lib/Kconfig Define this symbol if the architecture either uses 64-bit pointers or the PHYS_ADDR_T_64BIT is set. This covers 95% of the old arch magic. We only need an additional select for Xen on ARM (why anyway?), and we now always set ARCH_DMA_ADDR_T_64BIT on mips boards with 64-bit physical addressing instead of only doing it when highmem is set. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: James Hogan <jhogan@kernel.org>
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d4a451d5 |
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03-Apr-2018 |
Christoph Hellwig <hch@lst.de> |
arch: remove the ARCH_PHYS_ADDR_T_64BIT config symbol Instead select the PHYS_ADDR_T_64BIT for 32-bit architectures that need a 64-bit phys_addr_t type directly. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: James Hogan <jhogan@kernel.org>
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f6f9be1c |
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30-Nov-2017 |
Florian Fainelli <f.fainelli@gmail.com> |
ARM: 8725/1: Add Broadcom Brahma-B15 readahead cache support This patch adds support for the Broadcom Brahma-B15 CPU readahead cache controller. This cache controller sits between the L2 and the memory bus and its purpose is to provide a friendler burst size towards the DDR interface than the native cache line size. The readahead cache is mostly transparent, except for flush_kern_cache_all, which is precisely what we are overriding here. The readahead cache only intercepts reads, and does invalidate on writes (IOW), as such, some data can remain stale in any of its buffers, such that we need to flush it, which is an operation that needs to happen in a particular order: - disable the readahead cache - flush it - call the appropriate cache-v7.S function - re-enable This patch tries to minimize the impact to the cache-v7.S file by only providing a stub in case CONFIG_CACHE_B15_RAC is enabled (default for ARCH_BRCMSTB since it is the current user). Signed-off-by: Alamy Liu <alamyliu@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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#
b2441318 |
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01-Nov-2017 |
Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
License cleanup: add SPDX GPL-2.0 license identifier to files with no license Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of the kernel, which is GPL version 2. Update the files which contain no license information with the 'GPL-2.0' SPDX license identifier. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne. How this work was done: Patches were generated and checked against linux-4.14-rc6 for a subset of the use cases: - file had no licensing information it it. - file was a */uapi/* one with no licensing information in it, - file was a */uapi/* one with existing licensing information, Further patches will be generated in subsequent months to fix up cases where non-standard license headers were used, and references to license had to be inferred by heuristics based on keywords. The analysis to determine which SPDX License Identifier to be applied to a file was done in a spreadsheet of side by side results from of the output of two independent scanners (ScanCode & Windriver) producing SPDX tag:value files created by Philippe Ombredanne. Philippe prepared the base worksheet, and did an initial spot review of a few 1000 files. The 4.13 kernel was the starting point of the analysis with 60,537 files assessed. Kate Stewart did a file by file comparison of the scanner results in the spreadsheet to determine which SPDX license identifier(s) to be applied to the file. She confirmed any determination that was not immediately clear with lawyers working with the Linux Foundation. Criteria used to select files for SPDX license identifier tagging was: - Files considered eligible had to be source code files. - Make and config files were included as candidates if they contained >5 lines of source - File already had some variant of a license header in it (even if <5 lines). All documentation files were explicitly excluded. The following heuristics were used to determine which SPDX license identifiers to apply. - when both scanners couldn't find any license traces, file was considered to have no license information in it, and the top level COPYING file license applied. For non */uapi/* files that summary was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 11139 and resulted in the first patch in this series. If that file was a */uapi/* path one, it was "GPL-2.0 WITH Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 WITH Linux-syscall-note 930 and resulted in the second patch in this series. - if a file had some form of licensing information in it, and was one of the */uapi/* ones, it was denoted with the Linux-syscall-note if any GPL family license was found in the file or had no licensing in it (per prior point). Results summary: SPDX license identifier # files ---------------------------------------------------|------ GPL-2.0 WITH Linux-syscall-note 270 GPL-2.0+ WITH Linux-syscall-note 169 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17 LGPL-2.1+ WITH Linux-syscall-note 15 GPL-1.0+ WITH Linux-syscall-note 14 ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5 LGPL-2.0+ WITH Linux-syscall-note 4 LGPL-2.1 WITH Linux-syscall-note 3 ((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3 ((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1 and that resulted in the third patch in this series. - when the two scanners agreed on the detected license(s), that became the concluded license(s). - when there was disagreement between the two scanners (one detected a license but the other didn't, or they both detected different licenses) a manual inspection of the file occurred. - In most cases a manual inspection of the information in the file resulted in a clear resolution of the license that should apply (and which scanner probably needed to revisit its heuristics). - When it was not immediately clear, the license identifier was confirmed with lawyers working with the Linux Foundation. - If there was any question as to the appropriate license identifier, the file was flagged for further research and to be revisited later in time. In total, over 70 hours of logged manual review was done on the spreadsheet to determine the SPDX license identifiers to apply to the source files by Kate, Philippe, Thomas and, in some cases, confirmation by lawyers working with the Linux Foundation. Kate also obtained a third independent scan of the 4.13 code base from FOSSology, and compared selected files where the other two scanners disagreed against that SPDX file, to see if there was new insights. The Windriver scanner is based on an older version of FOSSology in part, so they are related. Thomas did random spot checks in about 500 files from the spreadsheets for the uapi headers and agreed with SPDX license identifier in the files he inspected. For the non-uapi files Thomas did random spot checks in about 15000 files. In initial set of patches against 4.14-rc6, 3 files were found to have copy/paste license identifier errors, and have been fixed to reflect the correct identifier. Additionally Philippe spent 10 hours this week doing a detailed manual inspection and review of the 12,461 patched files from the initial patch version early this week with: - a full scancode scan run, collecting the matched texts, detected license ids and scores - reviewing anything where there was a license detected (about 500+ files) to ensure that the applied SPDX license was correct - reviewing anything where there was no detection but the patch license was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied SPDX license was correct This produced a worksheet with 20 files needing minor correction. This worksheet was then exported into 3 different .csv files for the different types of files to be modified. These .csv files were then reviewed by Greg. Thomas wrote a script to parse the csv files and add the proper SPDX tag to the file, in the format that the file expected. This script was further refined by Greg based on the output to detect more types of files automatically and to distinguish between header and source .c files (which need different comment types.) Finally Greg ran the script using the .csv files to generate the patches. Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
1b11d39e |
|
24-May-2017 |
Vladimir Murzin <vladimir.murzin@arm.com> |
ARM: NOMMU: Set ARM_DMA_MEM_BUFFERABLE for M-class cpus Now, we have dedicated non-cacheable region for consistent DMA operations. However, that region can still be marked as bufferable by MPU, so it'd be safer to have barriers by default. M-class machines that didn't need it until now also likely won't need it in the future, therefore, we offer this as an option. Tested-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Tested-by: Andras Szemzo <sza@esh.hu> Tested-by: Alexandre TORGUE <alexandre.torgue@st.com> Reviewed-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Acked-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Christoph Hellwig <hch@lst.de>
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#
1515b186 |
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19-May-2017 |
Russell King <rmk+kernel@armlinux.org.uk> |
ARM: make configuration of userspace Thumb support an expert option David Mosberger reports random segfaults and other problems when running his buildroot userspace. It turns out that his kernel did not have support for Thumb userspace, nor did his application, but glibc made use of Thumb instructions in glibc. The kernel Thumb support option already recommends being enabled, and is also so biased, but clearly this is not enough of a recommendation. So, hide this behind CONFIG_EXPERT as well, and include a note to indicate the potential issues if it's turned off and userspace Thumb mode is made use of. Reported-by: David Mosberger <davidm@egauge.net> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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#
c466bda6 |
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08-Feb-2017 |
Russell King <rmk+kernel@armlinux.org.uk> |
ARM: add CPU_THUMB_CAPABLE to indicate possible Thumb support Clean up arch/arm/mm/Kconfig a little to provide a symbol which indicates whether the CPU may support the Thumb instruction set. This gets rid of the growing dependencies on ARM_THUMB, and also gives us a useful Kconfig symbol for choosing the kuser code. Reviewed-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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#
0f5bf6d0 |
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06-Feb-2017 |
Laura Abbott <labbott@redhat.com> |
arch: Rename CONFIG_DEBUG_RODATA and CONFIG_DEBUG_MODULE_RONX Both of these options are poorly named. The features they provide are necessary for system security and should not be considered debug only. Change the names to CONFIG_STRICT_KERNEL_RWX and CONFIG_STRICT_MODULE_RWX to better describe what these options do. Signed-off-by: Laura Abbott <labbott@redhat.com> Acked-by: Jessica Yu <jeyu@redhat.com> Signed-off-by: Kees Cook <keescook@chromium.org>
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#
ad21fc4f |
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06-Feb-2017 |
Laura Abbott <labbott@redhat.com> |
arch: Move CONFIG_DEBUG_RODATA and CONFIG_SET_MODULE_RONX to be common There are multiple architectures that support CONFIG_DEBUG_RODATA and CONFIG_SET_MODULE_RONX. These options also now have the ability to be turned off at runtime. Move these to an architecture independent location and make these options def_bool y for almost all of those arches. Signed-off-by: Laura Abbott <labbott@redhat.com> Acked-by: Ingo Molnar <mingo@kernel.org> Acked-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Kees Cook <keescook@chromium.org>
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#
01bf9278 |
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31-Oct-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: 8623/1: mm: add ARM_L1_CACHE_SHIFT_7 for UniPhier outer cache The UniPhier outer cache (arch/arm/mm/cache-uniphier.c) has 128 byte line length and its tags are also managed per 128 byte line. This is very unfortunate, but the current 64 byte alignment for kmalloc() causes sharing problems on DMA if used with this outer cache. This commit adds ARM_L1_CACHE_SHIFT_7 to increase the DMA minimum alignment to 128 byte if CACHE_UNIPHIER is enabled. There are several drivers that assume aligning to L1_CACHE_BYTES will be DMA safe, so this commit also changes the L1_CACHE_BYTES for safety. Having said that, I hesitate to align all the other SoCs in Multi platform to the UniPhier's requirement. So, I am disabling the CONFIG_CACHE_UNIPHIER by default, so that multi_v7_defconfig will still stay with CONFIG_ARM_L1_CACHE_SHIFT=6. With this commit, UniPhier SoCs will become slower, but it is much better than system crash. If desired, the outer-cache can be enabled by merge_config or something. Note: The UniPhier PH1-Pro5 SoC is equipped also with L3 cache with 256 byte line size but its tags are managed per 128 byte sub-line. So, ARM_L1_CACHE_SHIFT_7 should be fine for all the UniPhier SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
b828f960 |
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02-Sep-2016 |
Mark Rutland <mark.rutland@arm.com> |
ARM: 8611/1: l2x0: add PMU support The L2C-220 (AKA L220) and L2C-310 (AKA PL310) cache controllers feature a Performance Monitoring Unit (PMU), which can be useful for tuning and/or debugging. This hardware is always present and the relevant registers are accessible to non-secure accesses. Thus, no special firmware interface is necessary. This patch adds support for the PMU, plugging into the usual perf infrastructure. The overflow interrupt is not always available (e.g. on RealView PBX A9 it is not wired up at all), and the hardware counters saturate, so the driver does not make use of this. Instead, the driver periodically polls and reset counters as required to avoid losing events due to saturation. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Pawel Moll <pawel.moll@arm.com> Tested-by: Kim Phillips <kim.phillips@arm.com> Cc: Russell King <linux@armlinux.org.uk> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
bc0ee9d2 |
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30-Aug-2016 |
Jonathan Austin <jonathan.austin@arm.com> |
ARM: 8607/1: V7M: Wire up caches for V7M processors with cache support. This patch does the plumbing required to invoke the V7M cache code added in earlier patches in this series, although there is no users for that yet. In order to honour the I/D cache disable config options, this patch changes the mechanism by which the CCR is set on boot, to be more like V7A/R. Signed-off-by: Jonathan Austin <jonathan.austin@arm.com> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Tested-by: Andras Szemzo <sza@esh.hu> Tested-by: Joachim Eastwood <manabian@gmail.com> Tested-by: Alexandre TORGUE <alexandre.torgue@st.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
520319de |
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20-Jun-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: 8582/1: remove unused CONFIG_ARCH_HAS_BARRIERS Since commit 2b749cb3a515 ("ARM: realview: remove private barrier implementation"), this config is not used by any platform. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
fff7fb0b |
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20-May-2016 |
Zhaoxiu Zeng <zhaoxiu.zeng@gmail.com> |
lib/GCD.c: use binary GCD algorithm instead of Euclidean The binary GCD algorithm is based on the following facts: 1. If a and b are all evens, then gcd(a,b) = 2 * gcd(a/2, b/2) 2. If a is even and b is odd, then gcd(a,b) = gcd(a/2, b) 3. If a and b are all odds, then gcd(a,b) = gcd((a-b)/2, b) = gcd((a+b)/2, b) Even on x86 machines with reasonable division hardware, the binary algorithm runs about 25% faster (80% the execution time) than the division-based Euclidian algorithm. On platforms like Alpha and ARMv6 where division is a function call to emulation code, it's even more significant. There are two variants of the code here, depending on whether a fast __ffs (find least significant set bit) instruction is available. This allows the unpredictable branches in the bit-at-a-time shifting loop to be eliminated. If fast __ffs is not available, the "even/odd" GCD variant is used. I use the following code to benchmark: #include <stdio.h> #include <stdlib.h> #include <stdint.h> #include <string.h> #include <time.h> #include <unistd.h> #define swap(a, b) \ do { \ a ^= b; \ b ^= a; \ a ^= b; \ } while (0) unsigned long gcd0(unsigned long a, unsigned long b) { unsigned long r; if (a < b) { swap(a, b); } if (b == 0) return a; while ((r = a % b) != 0) { a = b; b = r; } return b; } unsigned long gcd1(unsigned long a, unsigned long b) { unsigned long r = a | b; if (!a || !b) return r; b >>= __builtin_ctzl(b); for (;;) { a >>= __builtin_ctzl(a); if (a == b) return a << __builtin_ctzl(r); if (a < b) swap(a, b); a -= b; } } unsigned long gcd2(unsigned long a, unsigned long b) { unsigned long r = a | b; if (!a || !b) return r; r &= -r; while (!(b & r)) b >>= 1; for (;;) { while (!(a & r)) a >>= 1; if (a == b) return a; if (a < b) swap(a, b); a -= b; a >>= 1; if (a & r) a += b; a >>= 1; } } unsigned long gcd3(unsigned long a, unsigned long b) { unsigned long r = a | b; if (!a || !b) return r; b >>= __builtin_ctzl(b); if (b == 1) return r & -r; for (;;) { a >>= __builtin_ctzl(a); if (a == 1) return r & -r; if (a == b) return a << __builtin_ctzl(r); if (a < b) swap(a, b); a -= b; } } unsigned long gcd4(unsigned long a, unsigned long b) { unsigned long r = a | b; if (!a || !b) return r; r &= -r; while (!(b & r)) b >>= 1; if (b == r) return r; for (;;) { while (!(a & r)) a >>= 1; if (a == r) return r; if (a == b) return a; if (a < b) swap(a, b); a -= b; a >>= 1; if (a & r) a += b; a >>= 1; } } static unsigned long (*gcd_func[])(unsigned long a, unsigned long b) = { gcd0, gcd1, gcd2, gcd3, gcd4, }; #define TEST_ENTRIES (sizeof(gcd_func) / sizeof(gcd_func[0])) #if defined(__x86_64__) #define rdtscll(val) do { \ unsigned long __a,__d; \ __asm__ __volatile__("rdtsc" : "=a" (__a), "=d" (__d)); \ (val) = ((unsigned long long)__a) | (((unsigned long long)__d)<<32); \ } while(0) static unsigned long long benchmark_gcd_func(unsigned long (*gcd)(unsigned long, unsigned long), unsigned long a, unsigned long b, unsigned long *res) { unsigned long long start, end; unsigned long long ret; unsigned long gcd_res; rdtscll(start); gcd_res = gcd(a, b); rdtscll(end); if (end >= start) ret = end - start; else ret = ~0ULL - start + 1 + end; *res = gcd_res; return ret; } #else static inline struct timespec read_time(void) { struct timespec time; clock_gettime(CLOCK_PROCESS_CPUTIME_ID, &time); return time; } static inline unsigned long long diff_time(struct timespec start, struct timespec end) { struct timespec temp; if ((end.tv_nsec - start.tv_nsec) < 0) { temp.tv_sec = end.tv_sec - start.tv_sec - 1; temp.tv_nsec = 1000000000ULL + end.tv_nsec - start.tv_nsec; } else { temp.tv_sec = end.tv_sec - start.tv_sec; temp.tv_nsec = end.tv_nsec - start.tv_nsec; } return temp.tv_sec * 1000000000ULL + temp.tv_nsec; } static unsigned long long benchmark_gcd_func(unsigned long (*gcd)(unsigned long, unsigned long), unsigned long a, unsigned long b, unsigned long *res) { struct timespec start, end; unsigned long gcd_res; start = read_time(); gcd_res = gcd(a, b); end = read_time(); *res = gcd_res; return diff_time(start, end); } #endif static inline unsigned long get_rand() { if (sizeof(long) == 8) return (unsigned long)rand() << 32 | rand(); else return rand(); } int main(int argc, char **argv) { unsigned int seed = time(0); int loops = 100; int repeats = 1000; unsigned long (*res)[TEST_ENTRIES]; unsigned long long elapsed[TEST_ENTRIES]; int i, j, k; for (;;) { int opt = getopt(argc, argv, "n:r:s:"); /* End condition always first */ if (opt == -1) break; switch (opt) { case 'n': loops = atoi(optarg); break; case 'r': repeats = atoi(optarg); break; case 's': seed = strtoul(optarg, NULL, 10); break; default: /* You won't actually get here. */ break; } } res = malloc(sizeof(unsigned long) * TEST_ENTRIES * loops); memset(elapsed, 0, sizeof(elapsed)); srand(seed); for (j = 0; j < loops; j++) { unsigned long a = get_rand(); /* Do we have args? */ unsigned long b = argc > optind ? strtoul(argv[optind], NULL, 10) : get_rand(); unsigned long long min_elapsed[TEST_ENTRIES]; for (k = 0; k < repeats; k++) { for (i = 0; i < TEST_ENTRIES; i++) { unsigned long long tmp = benchmark_gcd_func(gcd_func[i], a, b, &res[j][i]); if (k == 0 || min_elapsed[i] > tmp) min_elapsed[i] = tmp; } } for (i = 0; i < TEST_ENTRIES; i++) elapsed[i] += min_elapsed[i]; } for (i = 0; i < TEST_ENTRIES; i++) printf("gcd%d: elapsed %llu\n", i, elapsed[i]); k = 0; srand(seed); for (j = 0; j < loops; j++) { unsigned long a = get_rand(); unsigned long b = argc > optind ? strtoul(argv[optind], NULL, 10) : get_rand(); for (i = 1; i < TEST_ENTRIES; i++) { if (res[j][i] != res[j][0]) break; } if (i < TEST_ENTRIES) { if (k == 0) { k = 1; fprintf(stderr, "Error:\n"); } fprintf(stderr, "gcd(%lu, %lu): ", a, b); for (i = 0; i < TEST_ENTRIES; i++) fprintf(stderr, "%ld%s", res[j][i], i < TEST_ENTRIES - 1 ? ", " : "\n"); } } if (k == 0) fprintf(stderr, "PASS\n"); free(res); return 0; } Compiled with "-O2", on "VirtualBox 4.4.0-22-generic #38-Ubuntu x86_64" got: zhaoxiuzeng@zhaoxiuzeng-VirtualBox:~/develop$ ./gcd -r 500000 -n 10 gcd0: elapsed 10174 gcd1: elapsed 2120 gcd2: elapsed 2902 gcd3: elapsed 2039 gcd4: elapsed 2812 PASS zhaoxiuzeng@zhaoxiuzeng-VirtualBox:~/develop$ ./gcd -r 500000 -n 10 gcd0: elapsed 9309 gcd1: elapsed 2280 gcd2: elapsed 2822 gcd3: elapsed 2217 gcd4: elapsed 2710 PASS zhaoxiuzeng@zhaoxiuzeng-VirtualBox:~/develop$ ./gcd -r 500000 -n 10 gcd0: elapsed 9589 gcd1: elapsed 2098 gcd2: elapsed 2815 gcd3: elapsed 2030 gcd4: elapsed 2718 PASS zhaoxiuzeng@zhaoxiuzeng-VirtualBox:~/develop$ ./gcd -r 500000 -n 10 gcd0: elapsed 9914 gcd1: elapsed 2309 gcd2: elapsed 2779 gcd3: elapsed 2228 gcd4: elapsed 2709 PASS [akpm@linux-foundation.org: avoid #defining a CONFIG_ variable] Signed-off-by: Zhaoxiu Zeng <zhaoxiu.zeng@gmail.com> Signed-off-by: George Spelvin <linux@horizon.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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#
ac96680d |
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19-Feb-2016 |
Arnd Bergmann <arnd@arndb.de> |
ARM: 8535/1: mm: DEBUG_RODATA makes no sense with XIP_KERNEL When CONFIG_DEBUG_ALIGN_RODATA is set, we get a link error: arch/arm/mm/built-in.o:(.data+0x4bc): undefined reference to `__start_rodata_section_aligned' However, this combination is useless, as XIP_KERNEL implies that all the RODATA is already marked readonly, so both CONFIG_DEBUG_RODATA and CONFIG_DEBUG_ALIGN_RODATA (which depends on the other) are not needed with XIP_KERNEL, and this patches enforces that using a Kconfig dependency. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Fixes: 25362dc496ed ("ARM: 8501/1: mm: flip priority of CONFIG_DEBUG_RODATA") Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
25362dc4 |
|
25-Jan-2016 |
Kees Cook <keescook@chromium.org> |
ARM: 8501/1: mm: flip priority of CONFIG_DEBUG_RODATA The use of CONFIG_DEBUG_RODATA is generally seen as an essential part of kernel self-protection: http://www.openwall.com/lists/kernel-hardening/2015/11/30/13 Additionally, its name has grown to mean things beyond just rodata. To get ARM closer to this, we ought to rearrange the names of the configs that control how the kernel protects its memory. What was called CONFIG_ARM_KERNMEM_PERMS is realy doing the work that other architectures call CONFIG_DEBUG_RODATA. This redefines CONFIG_DEBUG_RODATA to actually do the bulk of the ROing (and NXing). In the place of the old CONFIG_DEBUG_RODATA, use CONFIG_DEBUG_ALIGN_RODATA, since that's what the option does: adds section alignment for making rodata explicitly NX, as arm does not split the page tables like arm64 does without _ALIGN_RODATA. Also adds human readable names to the sections so I could more easily debug my typos, and makes CONFIG_DEBUG_RODATA default "y" for CPU_V7. Results in /sys/kernel/debug/kernel_page_tables for each config state: # CONFIG_DEBUG_RODATA is not set # CONFIG_DEBUG_ALIGN_RODATA is not set ---[ Kernel Mapping ]--- 0x80000000-0x80900000 9M RW x SHD 0x80900000-0xa0000000 503M RW NX SHD CONFIG_DEBUG_RODATA=y CONFIG_DEBUG_ALIGN_RODATA=y ---[ Kernel Mapping ]--- 0x80000000-0x80100000 1M RW NX SHD 0x80100000-0x80700000 6M ro x SHD 0x80700000-0x80a00000 3M ro NX SHD 0x80a00000-0xa0000000 502M RW NX SHD CONFIG_DEBUG_RODATA=y # CONFIG_DEBUG_ALIGN_RODATA is not set ---[ Kernel Mapping ]--- 0x80000000-0x80100000 1M RW NX SHD 0x80100000-0x80a00000 9M ro x SHD 0x80a00000-0xa0000000 502M RW NX SHD Signed-off-by: Kees Cook <keescook@chromium.org> Reviewed-by: Laura Abbott <labbott@fedoraproject.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
17d44d7d |
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25-Nov-2015 |
Arnd Bergmann <arnd@arndb.de> |
ARM: no longer make CPU targets visible separately Now that realview and integrator always select the correct CPU type themselves based on the core tiles, there is no need to still have them user-visible in arch/arm/mm/Kconfig. The ARM925T symbol has been selected by the only user for many years, so that can be removed along with the realview and integrator specific ones. This also solves randconfig build problems on realview. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Russell King <linux@arm.linux.org.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
38541bf4 |
|
25-Nov-2015 |
Arnd Bergmann <arnd@arndb.de> |
ARM: no longer force unbuffered DMA for realview Commit 42c4dafe803dca ("ARM: 6202/1: Do not ARM_DMA_MEM_BUFFERABLE on RealView boards with L210/L220") changed the generic setting for ARM_DMA_MEM_BUFFERABLE to be disabled on any Realview kernel that includes support for any of the ARM11 variations. Doing this was required to allow doing DMA without a lockup in the l2x0 cache controller on the Realview platform. Unfortunately, in a kernel that also contains support for any ARMv7 based machine, the same change makes it impossible to do DMA on ARMv7, which gets in the way of enabling multiplatform support on Realview. As confirmed by Catalin Marinas and Linus Walleij, the current code for Realview that we have in the kernel does not actually perform any DMA, and this is unlikely to change in the future. Therefore we can revert 42c4dafe803dca without introducing regressions, but we must never start using DMA on this platform in the future. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Russell King <linux@arm.linux.org.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
e7ecbc05 |
|
01-Oct-2015 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: uniphier: add outer cache support This commit adds support for UniPhier outer cache controller. All the UniPhier SoCs are equipped with the L2 cache, while the L3 cache is currently only integrated on PH1-Pro5 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Olof Johansson <olof@lixom.net>
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#
db695c05 |
|
21-Sep-2015 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: remove user cmpxchg syscall Mark Brand reports that a NEEDS_SYSCALL_FOR_CMPXCHG enabled kernel would open a security hole in the ghost syscall used to implement cmpxchg, as it fails to validate the user pointer. However, in order for this option to be enabled, you'd need to be building a pre-ARMv6 kernel with SMP support. There is only one system known which fits that, which is an early ARM SMP FPGA implementation based on the ARM926T. In any case, the Kconfig does not allow SMP to be enabled for pre-ARMv6 systems. Moreover, even if NEEDS_SYSCALL_FOR_CMPXCHG were to be enabled, the kernel would not build as __ARM_NR_cmpxchg64 is not defined. The simple answer is to remove the buggy code. Reported-by: Mark Brand <markbrand@google.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
f8130906 |
|
01-Jun-2015 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: move heavy barrier support out of line The existing memory barrier macro causes a significant amount of code to be inserted inline at every call site. For example, in gpio_set_irq_type(), we have this for mb(): c0344c08: f57ff04e dsb st c0344c0c: e59f8190 ldr r8, [pc, #400] ; c0344da4 <gpio_set_irq_type+0x230> c0344c10: e3590004 cmp r9, #4 c0344c14: e5983014 ldr r3, [r8, #20] c0344c18: 0a000054 beq c0344d70 <gpio_set_irq_type+0x1fc> c0344c1c: e3530000 cmp r3, #0 c0344c20: 0a000004 beq c0344c38 <gpio_set_irq_type+0xc4> c0344c24: e50b2030 str r2, [fp, #-48] ; 0xffffffd0 c0344c28: e50bc034 str ip, [fp, #-52] ; 0xffffffcc c0344c2c: e12fff33 blx r3 c0344c30: e51bc034 ldr ip, [fp, #-52] ; 0xffffffcc c0344c34: e51b2030 ldr r2, [fp, #-48] ; 0xffffffd0 c0344c38: e5963004 ldr r3, [r6, #4] Moving the outer_cache_sync() call out of line reduces the impact of the barrier: c0344968: f57ff04e dsb st c034496c: e35a0004 cmp sl, #4 c0344970: e50b2030 str r2, [fp, #-48] ; 0xffffffd0 c0344974: 0a000044 beq c0344a8c <gpio_set_irq_type+0x1b8> c0344978: ebf363dd bl c001d8f4 <arm_heavy_mb> c034497c: e5953004 ldr r3, [r5, #4] This should reduce the cache footprint of this code. Overall, this results in a reduction of around 20K in the kernel size: text data bss dec hex filename 10773970 667392 10369656 21811018 14ccf4a ../build/imx6/vmlinux-old 10754219 667392 10369656 21791267 14c8223 ../build/imx6/vmlinux-new Another advantage to this approach is that we can finally resolve the issue of SoCs which have their own memory barrier requirements within multiplatform kernels (such as OMAP.) Here, the bus interconnects need additional handling to ensure that writes become visible in the correct order (eg, between dma_map() operations, writes to DMA coherent memory, and MMIO accesses.) Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
45b0fa09 |
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19-May-2015 |
Stefan Agner <stefan@agner.ch> |
ARM: 8369/1: ARMv7M: define size of vector table for Vybrid Vybrids has 112 peripheral interrupts which can be routed to the Cortex-M4's NVIC interrupt controller. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
d8dc7fbd |
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04-Apr-2015 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: re-implement physical address space switching Re-implement the physical address space switching to be architecturally compliant. This involves flushing the caches, disabling the MMU, and only then updating the page tables. Once that is complete, the system can be brought back up again. Since we disable the MMU, we need to do the update in assembly code. Luckily, the entries which need updating are fairly trivial, and are all setup by the early assembly code. We can merely adjust each entry by the delta required. Not only does this fix the code to be architecturally compliant, but it fixes a couple of bugs too: 1. The original code would only ever update the first L2 entry covering a fraction of the kernel; the remainder were left untouched. 2. The L2 entries covering the DTB blob were likewise untouched. This solution fixes up all entries. Tested-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
c32b7655 |
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26-May-2015 |
Arnd Bergmann <arnd@arndb.de> |
ARM: 8374/1: no longer expose CPU_ARM7TDMI/CPU_ARM9TDMI Atmel at91x40 is gone, so we no longer have any platform using either of these two, and we get randconfig failures on NOMMU kernels if they accidentally get enabled on something that conflicts with ARMv4T. This stops short of removing the entire CPU support for now, but as nothing selects these, it is basically dead code. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
6b1814cd |
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10-Apr-2015 |
Maxime Coquelin stm32 <mcoquelin.stm32@gmail.com> |
ARM: 8340/1: ARMv7-M: Enlarge vector table up to 256 entries From Cortex-M reference manuals, the nvic supports up to 240 interrupts. So the number of entries in vectors table is up to 256. This patch adds a new config flag to specify the number of external interrupts. Some ifdeferies are added in order to respect the natural alignment without wasting too much space on smaller systems. Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Stefan Agner <stefan@agner.ch> Tested-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
5d38000b |
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17-Apr-2015 |
Nathan Lynch <nathan_lynch@mentor.com> |
ARM: 8342/1: VDSO: depend on CPU_V7 When targeting ARMv3 (e.g. rpc) and enabling CONFIG_VDSO we get: arch/arm/vdso/datapage.S:13: Error: selected processor does not support ARM mode `bx lr' One fix considered was to use 'ldr pc,lr' for such configurations, but since the VDSO is unlikely to be useful for pre-v7 hardware, just make it depend on CONFIG_CPU_V7. Reported-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Nathan Lynch <nathan_lynch@mentor.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
e1e2f6e4 |
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09-Jan-2015 |
Florian Fainelli <f.fainelli@gmail.com> |
ARM: 8276/1: Make CPU_DCACHE_DISABLE depend on !SMP Enabling CPU_DCACHE_DISABLE on a SMP capable system will prevent the kernel from booting because of the following ldrex instruction in arch_spin_lock: (gdb) x/10i $pc => 0xc053cfa8 <_raw_spin_lock+4>: ldrex r3, [r0] 0xc053cfac <_raw_spin_lock+8>: add r2, r3, #65536 ; 0x10000 which is taken by the very first printk call: at /home/fainelli/work/linux/arch/arm/include/asm/spinlock.h:65 fmt=0xc0637650 " 01 66Booting Linux on physical CPU 0x%xn", args=<incomplete type>) at kernel/printk/printk.c:1525 fmt=0xc05370f4 <printk+52> " 24320215342 04340235344 20320215342 36377/341 17") at kernel/printk/printk.c:1688 ldrex requires exclusive monitor(s) (local or global) which are no longer working when the Data cache is disabled in CP15 and will just hang the CPU there. Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
e5b61deb |
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25-Mar-2015 |
Nathan Lynch <nathan_lynch@mentor.com> |
ARM: 8332/1: add CONFIG_VDSO Kconfig and Makefile bits Allow users to enable the vdso in Kconfig; include the vdso in the build if CONFIG_VDSO is enabled. Add 'vdso_install' target. Signed-off-by: Nathan Lynch <nathan_lynch@mentor.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
d88d6cfc |
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10-Feb-2015 |
Paul Bolle <pebolle@tiscali.nl> |
ARM: mm: Remove Kconfig symbol CACHE_PL310 Commit 20e783e39e55 ("ARM: 8296/1: cache-l2x0: clean up aurora cache handling") removed the only user of the Kconfig symbol CACHE_PL310. Setting CACHE_PL310 is now pointless. Remove its Kconfig entry, and one select of this symbol. Signed-off-by: Paul Bolle <pebolle@tiscali.nl> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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#
fba28905 |
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28-Jan-2015 |
Arnd Bergmann <arnd@arndb.de> |
ARM: 8298/1: ARM_KERNMEM_PERMS only works with MMU enabled The recently added ARM_KERNMEM_PERMS feature works by manipulating the kernel page tables, which obviously requires an MMU. Trying to enable this feature when the MMU is disabled results in a lot of compile errors in mm/init.c, so let's add a Kconfig dependency to avoid that case. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
08b964ff |
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10-Nov-2014 |
Nathan Lynch <nathan_lynch@mentor.com> |
ARM: 8198/1: make kuser helpers depend on MMU The kuser helpers page is not set up on non-MMU systems, so it does not make sense to allow CONFIG_KUSER_HELPERS to be enabled when CONFIG_MMU=n. Allowing it to be set on !MMU results in an oops in set_tls (used in execve and the arm_syscall trap handler): Unhandled exception: IPSR = 00000005 LR = fffffff1 CPU: 0 PID: 1 Comm: swapper Not tainted 3.18.0-rc1-00041-ga30465a #216 task: 8b838000 ti: 8b82a000 task.ti: 8b82a000 PC is at flush_thread+0x32/0x40 LR is at flush_thread+0x21/0x40 pc : [<8f00157a>] lr : [<8f001569>] psr: 4100000b sp : 8b82be20 ip : 00000000 fp : 8b83c000 r10: 00000001 r9 : 88018c84 r8 : 8bb85000 r7 : 8b838000 r6 : 00000000 r5 : 8bb77400 r4 : 8b82a000 r3 : ffff0ff0 r2 : 8b82a000 r1 : 00000000 r0 : 88020354 xPSR: 4100000b CPU: 0 PID: 1 Comm: swapper Not tainted 3.18.0-rc1-00041-ga30465a #216 [<8f002bc1>] (unwind_backtrace) from [<8f002033>] (show_stack+0xb/0xc) [<8f002033>] (show_stack) from [<8f00265b>] (__invalid_entry+0x4b/0x4c) As best I can tell this issue existed for the set_tls ARM syscall before commit fbfb872f5f41 "ARM: 8148/1: flush TLS and thumbee register state during exec" consolidated the TLS manipulation code into the set_tls helper function, but now that we're using it to flush register state during execve, !MMU users encounter the oops at the first exec. Prevent CONFIG_MMU=n configurations from enabling CONFIG_KUSER_HELPERS. Fixes: fbfb872f5f41 (ARM: 8148/1: flush TLS and thumbee register state during exec) Signed-off-by: Nathan Lynch <nathan_lynch@mentor.com> Reported-by: Stefan Agner <stefan@agner.ch> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Cc: stable@vger.kernel.org Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
dc680b98 |
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10-Nov-2014 |
Linus Walleij <linus.walleij@linaro.org> |
ARM: fix multiplatform allmodcompile Commit 68f3b875f7848f5304472184a4634148c5330cbd "ARM: integrator: make the Integrator multiplatform" broke allmodconfig like this: >> arch/arm/include/asm/cmpxchg.h:114:2: error: #error "SMP is not supported on this platform" (etc) This is due to the fact that as we turned on multiplatform for the Integrator, this enabled a lot of non-applicable CPU's to be selected for its multiplatform images, due to a lot of "depends on ARCH_INTEGRATOR" restrictions in arch/arm/mm/Kconfig for the different ARM CPU types. Fix this by restricting the CPU selections to respective multiplatform config, which now becomes a subset of the possible Integrator configurations, or alternatively the non-multiplatform config plus ARCH_INTEGRATOR, i.e.: if (!ARCH_MULTIPLATFORM || ARCH_MULTI_Vx) && (ARCH_INTEGRATOR || ARCH_FOO ...) Since the Integrator has been converted to multiplatform, this will often take the short form: if (ARCH_MULTI_Vx && ARCH_INTEGRATOR) If no other non-multiplatform platforms are elegible. Reported-by: Build bot for Mark Brown <broonie@kernel.org> Reported-by: Kbuild test robot <fengguang.wu@intel.com> Suggested-by: Russell King <linux@arm.linux.org.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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#
80d6b0c2 |
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03-Apr-2014 |
Kees Cook <keescook@chromium.org> |
ARM: mm: allow text and rodata sections to be read-only This introduces CONFIG_DEBUG_RODATA, making kernel text and rodata read-only. Additionally, this splits rodata from text so that rodata can also be NX, which may lead to wasted memory when aligning to SECTION_SIZE. The read-only areas are made writable during ftrace updates and kexec. Signed-off-by: Kees Cook <keescook@chromium.org> Tested-by: Laura Abbott <lauraa@codeaurora.org> Acked-by: Nicolas Pitre <nico@linaro.org>
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#
1e6b4811 |
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03-Apr-2014 |
Kees Cook <keescook@chromium.org> |
ARM: mm: allow non-text sections to be non-executable Adds CONFIG_ARM_KERNMEM_PERMS to separate the kernel memory regions into section-sized areas that can have different permisions. Performs the NX permission changes during free_initmem, so that init memory can be reclaimed. This uses section size instead of PMD size to reduce memory lost to padding on non-LPAE systems. Based on work by Brad Spengler, Larry Bassel, and Laura Abbott. Signed-off-by: Kees Cook <keescook@chromium.org> Tested-by: Laura Abbott <lauraa@codeaurora.org> Acked-by: Nicolas Pitre <nico@linaro.org>
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#
a11dd731 |
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04-Jul-2014 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: SWP emulation: always enable when SMP is enabled SWP is deprecated in ARMv6 and ARMv7 CPUs, but more importantly, when running on a SMP system, SWP doesn't guarantee atomicity. This means it can't really be used (by userspace) for locking purposes in a SMP environment. Currently, many configurations leave the SWP emulation disabled, which means we never know if userspace executes this instruction on ARMv7 hardware. Rectify this by enabling SWP emulation for ARMv7 with SMP (where we can trap the instruction.) Tested-by: Tony Lindgren <tony@atomide.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
80d3cb91 |
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07-Jul-2014 |
Shawn Guo <shawn.guo@linaro.org> |
ARM: 8090/1: add revision info for PL310 errata 588369 and 727915 Add revision info for PL310_ERRATA_588369 and PL310_ERRATA_727915 to help people understand if they need to enable the errata for their hardware. Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
ba364fc7 |
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10-Jul-2014 |
Andrew Lunn <andrew@lunn.ch> |
ARM: Kirkwood: Remove mach-kirkwood Now that all boards have been converted to DT and all the support code lives in mach-mvebu, we can remove mach-kirkwood. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Link: https://lkml.kernel.org/r/1405028192-9623-2-git-send-email-andrew@lunn.ch Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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#
a641f3a6 |
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19-Jun-2014 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: l2c: fix dependencies on PL310 errata symbols A number of configurations spit out warnings similar to: warning: (SOC_IMX6 && SOC_VF610 && ARCH_OMAP4) selects PL310_ERRATA_588369 which has unmet direct dependencies (CACHE_L2X0) warning: (SOC_IMX6 && SOC_VF610 && ARCH_OMAP4) selects PL310_ERRATA_727915 which has unmet direct dependencies (CACHE_L2X0) Clean up the dependencies here: * PL310 symbols should only be selected when CACHE_L2X0 is enabled. * Since the cache-l2x0 code detects PL310 presence at runtime, and we will eventually get rid of CACHE_PL310, surround these errata options with an if CACHE_L2X0 conditional rather than repeating the dependency against each. Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
c0fe18ba |
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15-Mar-2014 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: l2c: move errata configuration options to arch/arm/mm/Kconfig Move the L2C-310 errata configuration options to arch/arm/mm/Kconfig along side the option which enables support for this device. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
51aaf81f |
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22-Apr-2014 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: keep arch/arm/Kconfig and arch/arm/mm/Kconfig select entries sorted Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
fa04e209 |
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26-Feb-2014 |
Arnd Bergmann <arnd@arndb.de> |
ARM: rpc: autoselect CPU_SA110 ARCH_RPC no longer supports other CPUs aside from StrongARM110, so we can make the option implicitly selected by the platform and no longer give the option of building a kernel without CPU support. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Russell King <linux@arm.linux.org.uk>
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#
adc00979 |
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22-Feb-2014 |
Andrew Lunn <andrew@lunn.ch> |
ARM: MM Enable building Feroceon L2 cache controller with ARCH_MVEBU Kirkwood, which uses the Feroceon L2 cache controller will soon be moving into mach-mvebu. Allow the cache controller to be built in this situation. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Arnd Bergmann <arnd@arndb.de> Tested-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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#
b6ccb980 |
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07-Feb-2014 |
Will Deacon <will@kernel.org> |
ARM: 7954/1: mm: remove remaining domain support from ARMv6 CPU_32v6 currently selects CPU_USE_DOMAINS if CPU_V6 and MMU. This is because ARM 1136 r0pX CPUs lack the v6k extensions, and therefore do not have hardware thread registers. The lack of these registers requires the kernel to update the vectors page at each context switch in order to write a new TLS pointer. This write must be done via the userspace mapping, since aliasing caches can lead to expensive flushing when using kmap. Finally, this requires the vectors page to be mapped r/w for kernel and r/o for user, which has implications for things like put_user which must trigger CoW appropriately when targetting user pages. The upshot of all this is that a v6/v7 kernel makes use of domains to segregate kernel and user memory accesses. This has the nasty side-effect of making device mappings executable, which has been observed to cause subtle bugs on recent cores (e.g. Cortex-A15 performing a speculative instruction fetch from the GIC and acking an interrupt in the process). This patch solves this problem by removing the remaining domain support from ARMv6. A new memory type is added specifically for the vectors page which allows that page (and only that page) to be mapped as user r/o, kernel r/w. All other user r/o pages are mapped also as kernel r/o. Patch co-developed with Russell King. Cc: <stable@vger.kernel.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
d10d2d48 |
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01-Feb-2013 |
Ben Dooks <ben.dooks@codethink.co.uk> |
ARM: fix ARCH_IXP4xx usage of ARCH_SUPPORTS_BIG_ENDIAN The Kconfig for arch/arm/mach-ixp4xx has a local definition of ARCH_SUPPORTS_BIG_ENDIAN which could be used elsewhere. This means that if IXP4xx is selected and this symbol is selected eleswhere then an warning is produced. Clean the following error up by making the symbol be selected by the main ARCH_IXP4XX definition and have a common definition in arch/arm/mm/Kconfig warning: (ARCH_xxx) selects ARCH_SUPPORTS_BIG_ENDIAN which has unmet direct dependencies (ARCH_IXP4XX) warning: (ARCH_xxx) selects ARCH_SUPPORTS_BIG_ENDIAN which has unmet direct dependencies (ARCH_IXP4XX) Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
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#
ac124504 |
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14-Aug-2013 |
Nicolas Pitre <nico@fluxnic.net> |
ARM: 7816/1: CONFIG_KUSER_HELPERS: fix help text Commit f6f91b0d9fd9 ("ARM: allow kuser helpers to be removed from the vector page") introduced some help text for the CONFIG_KUSER_HELPERS option which is rather contradictory. Let's fix that, and improve it a little. Cc: <stable@vger.kernel.org> Signed-off-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
f6f91b0d |
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23-Jul-2013 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: allow kuser helpers to be removed from the vector page Provide a kernel configuration option to allow the kernel user helpers to be removed from the vector page, thereby preventing their use with ROP (return orientated programming) attacks. This option is only visible for CPU architectures which natively support all the operations which kernel user helpers would normally provide, and must be enabled with caution. Cc: <stable@vger.kernel.org> Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
66567618 |
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12-Jul-2012 |
Jonathan Austin <jonathan.austin@arm.com> |
ARM: select CPU_CPU15_MMU/MPU appropriately Currently CPU_V7 selects CPU_CP15_MMU, however in the case of a V7 CPU implementing the PMSA, such as the Cortex-R7, the CP15_MMU operations are not available. Selecting CPU_CP15_MPU is appropriate in this case. This patch makes CPU_CP15_MMU dependent on the use of the MMU, selecting CPU_CP15_MPU for v7 processors when !MMU is chosen. Signed-off-by: Jonathan Austin <jonathan.austin@arm.com>
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#
4477ca45 |
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21-Mar-2013 |
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> |
ARM: ARMv7-M: Allow the building of new kernel port This patch modifies the required Kconfig and Makefile files to allow the building of kernel for Cortex-M3. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: Jonathan Austin <jonathan.austin@arm.com> Tested-by: Jonathan Austin <jonathan.austin@arm.com> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
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#
82d9b0d0 |
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14-Jan-2013 |
Will Deacon <will@kernel.org> |
ARM: cache: remove ARMv3 support code This is only used by 740t, which is a v4 core and (by my reading of the datasheet for the CPU) ignores CRm for the cp15 cache flush operation, making the v4 cache implementation in cache-v4.S sufficient for this CPU. Tested with 740T core-tile on Integrator/AP baseboard. Acked-by: Hyok S. Choi <hyok.choi@samsung.com> Acked-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
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#
bc7dea00 |
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09-Dec-2011 |
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> |
ARM: let CPUs not being able to run in ARM mode enter in THUMB mode Some ARM cores are not capable to run in ARM mode (e.g. Cortex-M3). So obviously these cannot enter the kernel in ARM mode. Make an exception for them and let them enter in THUMB mode. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Message-Id: 1358162123-30113-1-git-send-email-u.kleine-koenig@pengutronix.de Acked-by: Nicolas Pitre <nico@linaro.org>
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#
651134b0 |
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09-Jan-2013 |
Will Deacon <will@kernel.org> |
ARM: virt: hide CONFIG_ARM_VIRT_EXT from user ARM_VIRT_EXT is a property of CPU_V7, but does not adversely affect other CPUs that can be built into the same kernel image (i.e. ARMv6+). This patch defaults ARM_VIRT_EXT to y if CPU_V7, allowing hypervisors such as KVM to make better use of the option and being able to rely on hyp-mode boot support. Signed-off-by: Will Deacon <will.deacon@arm.com>
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#
de490193 |
|
03-Oct-2012 |
Gregory CLEMENT <gregory.clement@bootlin.com> |
arm: mm: Add support for PJ4B cpu and init routines PJ4B is an implementation of the ARMv7 (such as the Cortex A9 for example) released by Marvell. This CPU is currently found in Armada 370 and Armada XP SoCs. This patch provides a support for the specific initialization of this CPU. Signed-off-by: Yehuda Yitschak <yehuday@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
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#
b1b3f49c |
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06-Oct-2012 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: config: sort select statements alphanumerically As suggested by Andrew Morton: This is a pet peeve of mine. Any time there's a long list of items (header file inclusions, kconfig entries, array initalisers, etc) and someone wants to add a new item, they *always* go and stick it at the end of the list. Guys, don't do this. Either put the new item into a randomly-chosen position or, probably better, alphanumerically sort the list. lets sort all our select statements alphanumerically. This commit was created by the following perl: while (<>) { while (/\\\s*$/) { $_ .= <>; } undef %selects if /^\s*config\s+/; if (/^\s+select\s+(\w+).*/) { if (defined($selects{$1})) { if ($selects{$1} eq $_) { print STDERR "Warning: removing duplicated $1 entry\n"; } else { print STDERR "Error: $1 differently selected\n". "\tOld: $selects{$1}\n". "\tNew: $_\n"; exit 1; } } $selects{$1} = $_; next; } if (%selects and (/^\s*$/ or /^\s+help/ or /^\s+---help---/ or /^endif/ or /^endchoice/)) { foreach $k (sort (keys %selects)) { print "$selects{$k}"; } undef %selects; } print; } if (%selects) { foreach $k (sort (keys %selects)) { print "$selects{$k}"; } } It found two duplicates: Warning: removing duplicated S5P_SETUP_MIPIPHY entry Warning: removing duplicated HARDIRQS_SW_RESEND entry and they are identical duplicates, hence the shrinkage in the diffstat of two lines. We have four testers reporting success of this change (Tony, Stephen, Linus and Sekhar.) Acked-by: Jason Cooper <jason@lakedaemon.net> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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5b6728d4 |
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17-Feb-2012 |
Dave Martin <dave.martin@linaro.org> |
ARM: virt: Add CONFIG_ARM_VIRT_EXT option It is now possible to enable the virtualization extention support. Signed-off-by: Dave Martin <dave.martin@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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357c9c1f |
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03-May-2012 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: Remove support for ARMv3 ARM610 and ARM710 CPUs This patch removes support for ARMv3 CPUs, which haven't worked properly for quite some time (see the FIXME comment in arch/arm/mm/fault.c). The only V3 parts left is the cache model for ARMv3, which is needed for some odd reason by ARM740T CPUs, and being able to build with -march=armv3, which is required for the RiscPC platform due to its bus structure. Acked-by: Will Deacon <will.deacon@arm.com> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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9b7333a9 |
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12-Apr-2012 |
Will Deacon <will@kernel.org> |
ARM: 7381/1: nommu: fix typo in mm/Kconfig The description for the CPU_HIGH_VECTOR Kconfig option for nommu builds doesn't make any sense. This patch fixes up the trivial grammatical error. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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08a183f0 |
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14-Feb-2012 |
Catalin Marinas <catalin.marinas@arm.com> |
ARM: 7323/1: Do not allow ARM_LPAE on pre-ARMv7 architectures This patch expands the Kconfig dependencies for ARM_LPAE to not allow enabling when architectures other than ARMv7 are built into the kernel. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Reported-by: Russell King <linux@arm.linux.org.uk> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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a092f2b1 |
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19-Jan-2012 |
Will Deacon <will@kernel.org> |
ARM: 7291/1: cache: assume 64-byte L1 cachelines for ARMv7 CPUs To ensure correct alignment of cacheline-aligned data, the maximum cacheline size needs to be known at compile time. Since Cortex-A8 and Cortex-A15 have 64-byte cachelines (and it is likely that there will be future ARMv7 implementations with the same line size) then it makes sense to assume that CPU_V7 implies a 64-byte L1 cacheline size. For CPUs with smaller caches, this will result in some harmless padding but will help with single zImage work and avoid hitting subtle bugs with misaligned data structures. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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ce5ea9f3 |
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29-Nov-2011 |
Dave Martin <dave.martin@linaro.org> |
ARM: l2x0/pl310: Refactor Kconfig to be more maintainable Making CACHE_L2X0 depend on (huge list of MACH_ and ARCH_ configs) is bothersome to maintain and likely to lead to merge conflicts. This patch moves the knowledge of which platforms have a L2x0 or PL310 cache controller to the individual machines. To enable this, a new MIGHT_HAVE_CACHE_L2X0 config option is introduced to allow machines to indicate that they may have such a cache controller independently of each other. Boards/SoCs which cannot reliably operate without the L2 cache controller support will need to select CACHE_L2X0 directly from their own Kconfigs instead. This applies to some TrustZone-enabled boards where Linux runs in the Normal World, for example. Signed-off-by: Dave Martin <dave.martin@linaro.org> Acked-by: Anton Vorontsov <cbouatmailru@gmail.com> (for cns3xxx) Acked-by: Tony Lindgren <tony@atomide.com> (for omap) Acked-by: Shawn Guo <shawn.guo@linaro.org> (for imx) Acked-by: Kukjin Kim <kgene.kim@samsung.com> (for exynos) Acked-by: Sascha Hauer <s.hauer@pengutronix.de> (for imx) Acked-by: Olof Johansson <olof@lixom.net> (for tegra)
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497b7e94 |
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22-Nov-2011 |
Catalin Marinas <catalin.marinas@arm.com> |
ARM: LPAE: Add the Kconfig entries This patch adds the ARM_LPAE and ARCH_PHYS_ADDR_T_64BIT Kconfig entries allowing LPAE support to be compiled into the kernel. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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a89cf59b |
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26-Sep-2011 |
Sascha Hauer <s.hauer@pengutronix.de> |
arm/imx: merge i.MX3 and i.MX6 The patch merges the build of imx3 and imx6. The Kconfig symbol ARCH_IMX_V6_V7 is introduced to replace ARCH_MX3 and ARCH_MX6. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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13eed989 |
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06-Sep-2011 |
Shawn Guo <shawn.guo@linaro.org> |
arm/imx6q: add device tree machine support It adds generic device tree based machine support for imx6q. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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220e6cf7 |
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07-Jun-2011 |
Rob Herring <rob.herring@calxeda.com> |
ARM: add Highbank core platform support This adds basic support for the Calxeda Highbank platform. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Reviewed-by: Jamie Iles <jamie@jamieiles.com> Reviewed-by: Shawn Guo <shawn.guo@linaro.org>
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02c981c0 |
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08-Jul-2011 |
Binghua Duan <binghua.duan@csr.com> |
ARM: CSR: Adding CSR SiRFprimaII board support SiRFprimaII is the latest generation application processor from CSR’s Multifunction SoC product family. Designed around an ARM cortex A9 core, high-speed memory bus, advanced 3D accelerator and full-HD multi-format video decoder, SiRFprimaII is able to meet the needs of complicated applications for modern multifunction devices that require heavy concurrent applications and fluid user experience. Integrated with GPS baseband, analog and PMU, this new platform is designed to provide a cost effective solution for Automotive and Consumer markets. This patch adds the basic support for this SoC and EVB board based on device tree. It is following the ZYNQ of Xilinx in some degree. Signed-off-by: Binghua Duan <Binghua.Duan@csr.com> Signed-off-by: Rongjun Ying <Rongjun.Ying@csr.com> Signed-off-by: Zhiwu Song <Zhiwu.Song@csr.com> Signed-off-by: Yuping Luo <Yuping.Luo@csr.com> Signed-off-by: Bin Shi <Bin.Shi@csr.com> Signed-off-by: Huayi Li <Huayi.Li@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
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93e85d8e |
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06-Jul-2011 |
Anton Vorontsov <avorontsov@mvista.com> |
ARM: cns3xxx: Add support for L2 Cache Controller CNS3xxx SOCs have L310-compatible cache controller, so let's use it. With this patch benchmarking with 'gzip' shows that performance is doubled, and I'm still able to boot full-fledged userland over NFS (using PCIe NIC), so the support should be pretty robust. p.s. While CNS3xxx reports that it has PL310, it still needs to wait on cache line operations, so we should not select 'CACHE_PL310', which is a micro-optimization that removes these waits for v7 CPUs. Someday we'd better rename CACHE_PL310 Kconfig option into NO_CACHE_WAIT or something less ambiguous. Signed-off-by: Anton Vorontsov <avorontsov@mvista.com>
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b85a3ef4 |
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20-Jun-2011 |
John Linn <john.linn@xilinx.com> |
ARM: Xilinx: Adding Xilinx board support The 1st board support is minimal to get a system up and running on the Xilinx platform. This platform reuses the clock implementation from plat-versatile, and it depends entirely on CONFIG_OF support. There is only one board support file which obtains all device information from a device tree dtb file which is passed to the kernel at boot time. Signed-off-by: John Linn <john.linn@xilinx.com>
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c23eb89e |
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03-Mar-2011 |
Richard Zhao <richard.zhao@freescale.com> |
ARM: imx3x: clean up ARCH_MX3X Move to SOC_SOC_IMX3X. Leave ARCH_MX31/35 definitions there, in case some place prevent multi-soc single image. Signed-off-by: Richard Zhao <richard.zhao@freescale.com> Acked-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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5637a126 |
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14-Feb-2011 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: move L1_CACHE_SHIFT_6 to mm/Kconfig Move L1_CACHE_SHIFT related options together, rather than spreading them across two separate Kconfig files. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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10606aad |
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13-Feb-2011 |
Kukjin Kim <kgene.kim@samsung.com> |
ARM: EXYNOS4: Update Kconfig and Makefile for the new ARCH_EXYNOS4 This patch changes the Kconfig and Makefile for the new ARCH_EXYNOS4. It also updates arch/arm/Kconfig, Makeifile and arch/arm/mm/Kconfig to include support for the new ARCH_EXYNOS4. Cc: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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0193c00e |
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10-Feb-2011 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: make SWP emulation explicit on !CPU_USE_DOMAINS SWP emulation requires that CPU domain support is disabled in order to work safely. Make that explicit in the kernel configuration to prevent illegal configurations being generated. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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15490ef8 |
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09-Feb-2011 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: Avoid building unsafe kernels on OMAP2 and MX3 OMAP2 (armv6) and MX3 turn off support for the V6K instructions, which when they include support for SMP kernels means that the resulting kernel is unsafe on SMP and can result in corrupted filesystems as we end up using unsafe bitops. Re-enable the use of V6K instructions on such kernels, and let such kernels running on V6 CPUs eat undefined instruction faults which will be much safer than filesystem corruption. Next merge window we can fix this properly (as it requires a much bigger set of changes.) Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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3bc28c8e |
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18-Jan-2011 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: v6k: DMA_CACHE_RWFO isn't appropriate for non-v6k CPUs Limit DMA_CACHE_RWFO to only v6k SMP CPUs - V6 CPUs aren't SMP capable, so the read/write for ownership work-around doesn't apply to them. Acked-by: Will Deacon <will.deacon@arm.com> Tested-by: Sourav Poddar <sourav.poddar@ti.com> Tested-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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581388c1 |
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17-Jan-2011 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: v6k: allow swp emulation again when ARMv7 is enabled Now that we build a v6+v6k+v7 kernel with -march=armv6k for everything, we don't need to disable swp emulation to work around the build problem with OMAP. Tested-by: Tony Lindgren <tony@atomide.com> Tested-by: Sourav Poddar <sourav.poddar@ti.com> Tested-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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60799c6d |
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15-Jan-2011 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: v6k: do not disable CPU_32v6K based on platform selection CPU_32v6K controls whether we use the ARMv6K extension instructions in the kernel, and in some places whether we use SMP-safe code sequences (eg, bitops.) MX3 prevents the selection of this option to ensure that it is not enabled for their CPU, which is ARMv6 only. Now that we've split the CPU_V6 option, V6K support won't be offered for MX3 anymore. OMAP prevents the selection of this option in an attempt to produce a kernel which runs on architectures from ARMv6 to ARMv7 MPCore. We now achieve this in a different way (see the previous patches). As such, we no longer need to offer this as a configuration option to the user. Tested-by: Tony Lindgren <tony@atomide.com> Tested-by: Sourav Poddar <sourav.poddar@ti.com> Tested-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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8762df4d |
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17-Jan-2011 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: v6k: use CPU domain feature if we include support for arch < ARMv6K Rather than turning off CPU domain switching when the build architecture includes ARMv6K, thereby causing problems for ARMv6-supporting kernels, turn it on when it's required to support a CPU architecture. Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Acked-by: Tony Lindgren <tony@atomide.com> Tested-by: Sourav Poddar <sourav.poddar@ti.com> Tested-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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c786282e |
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17-Jan-2011 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: v6k: Dove platforms use V6K architecture CPUs Make Dove platforms select the new V6K CPU option. Tested-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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e399b1a4 |
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17-Jan-2011 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: v6k: introduce CPU_V6K option Introduce a CPU_V6K configuration option for platforms to select if they have a V6K CPU core. This allows us to identify whether we need to support ARMv6 CPUs without the V6K SMP extensions at build time. Currently CPU_V6K is just an alias for CPU_V6, and all places which reference CPU_V6 are replaced by (CPU_V6 || CPU_V6K). Select CPU_V6K from platforms which are known to be V6K-only. Acked-by: Tony Lindgren <tony@atomide.com> Tested-by: Sourav Poddar <sourav.poddar@ti.com> Tested-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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e118a1df |
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06-Jan-2011 |
Catalin Marinas <catalin.marinas@arm.com> |
ARM: Do not enable SWP emulation if CPU_V6 && CPU_V7 This option uses LDREXB/STREXB to emulate SWPB but these instructions are not supported on all the ARMv6 processors. Reported-by: Anand Gadiyar <gadiyar@ti.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Leif Lindholm <Leif.Lindholm@arm.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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3f408fa0 |
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23-Nov-2010 |
Haojian Zhuang <haojian.zhuang@marvell.com> |
ARM: mmp: select CPU_PJ4 Since CPU_PJ4 is shared between PXA95x and MMP2, select CPU_PJ4 in MMP2 configuration. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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a4553358 |
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23-Nov-2010 |
Haojian Zhuang <haojian.zhuang@marvell.com> |
ARM: pxa: support pxa95x The core of PXA955 is PJ4. Add new PJ4 support. And add new macro CONFIG_PXA95x. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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6d9598e2 |
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17-Nov-2010 |
Magnus Damm <damm@opensource.se> |
ARM: mach-shmobile: Initial AG5 and AG5EVM support This patch adds initial support for Renesas SH-Mobile AG5. At this point the AG5 CPU support is limited to the ARM core, SCIF serial and a CMT timer together with L2 cache and the GIC. The AG5EVM board also supports Ethernet. Future patches will add support for GPIO, INTCS, CPGA and platform data / driver updates for devices such as IIC, LCDC, FSI, KEYSC, CEU and SDHI among others. The code in entry-macro.S will be cleaned up when the ARM IRQ demux code improvements have been merged. Depends on the AG5EVM mach-type recently registered but not yet present in arch/arm/tools/mach-types. As the AG5EVM board comes with 512MiB memory it is recommended to turn on HIGHMEM. Many thanks to Yoshii-san for initial bring up. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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64d2dc38 |
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16-Sep-2010 |
Leif Lindholm <leif.lindholm@arm.com> |
ARM: 6396/1: Add SWP/SWPB emulation for ARMv7 processors The SWP instruction was deprecated in the ARMv6 architecture, superseded by the LDREX/STREX family of instructions for load-linked/store-conditional operations. The ARMv7 multiprocessing extensions mandate that SWP/SWPB instructions are treated as undefined from reset, with the ability to enable them through the System Control Register SW bit. This patch adds the alternative solution to emulate the SWP and SWPB instructions using LDREX/STREX sequences, and log statistics to /proc/cpu/swp_emulation. To correctly deal with copy-on-write, it also modifies cpu_v7_set_pte_ext to change the mappings to priviliged RO when user RO. Signed-off-by: Leif Lindholm <leif.lindholm@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Kirill A. Shutemov <kirill@shutemov.name> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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247055aa |
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13-Sep-2010 |
Catalin Marinas <catalin.marinas@arm.com> |
ARM: 6384/1: Remove the domain switching on ARMv6k/v7 CPUs This patch removes the domain switching functionality via the set_fs and __switch_to functions on cores that have a TLS register. Currently, the ioremap and vmalloc areas share the same level 1 page tables and therefore have the same domain (DOMAIN_KERNEL). When the kernel domain is modified from Client to Manager (via the __set_fs or in the __switch_to function), the XN (eXecute Never) bit is overridden and newer CPUs can speculatively prefetch the ioremap'ed memory. Linux performs the kernel domain switching to allow user-specific functions (copy_to/from_user, get/put_user etc.) to access kernel memory. In order for these functions to work with the kernel domain set to Client, the patch modifies the LDRT/STRT and related instructions to the LDR/STR ones. The user pages access rights are also modified for kernel read-only access rather than read/write so that the copy-on-write mechanism still works. CPU_USE_DOMAINS gets disabled only if the hardware has a TLS register (CPU_32v6K is defined) since writing the TLS value to the high vectors page isn't possible. The user addresses passed to the kernel are checked by the access_ok() function so that they do not point to the kernel space. Tested-by: Anton Vorontsov <cbouatmailru@gmail.com> Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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9a6655e4 |
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31-Aug-2010 |
Catalin Marinas <catalin.marinas@arm.com> |
ARM: Improve the L2 cache performance when PL310 is used With this L2 cache controller, the cache maintenance by PA and sync operations are atomic and do not require a "wait" loop. This patch conditionally defines the cache_wait() function. Since L2x0 cache controllers do not work with ARMv7 CPUs, the patch automatically enables CACHE_PL310 when only CPU_V7 is defined. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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026b5ca3 |
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01-Sep-2010 |
Catalin Marinas <catalin.marinas@arm.com> |
ARM: 6344/1: Mark CPU_32v6K as depended on CPU_V7 CPU_32v6K is selected by CPU_V7 but it only depends on CPU_V6. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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c5f80065 |
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21-Jan-2010 |
Erik Gilling <konkers@android.com> |
[ARM] tegra: initial tegra support v2: Fixes from Mike Rapoport - remove unused header files (mach/dma.h and mach/nand.h) - remove tegra 1 references from Makefile.boot v2: fixes from Russell King - remove mach/io.h include from mach/iomap.h - fix whitespace in Kconfig v2: from Colin Cross - fix invalid immediate in debug-macro.S v3: - allow selection of multiple boards Signed-off-by: Colin Cross <ccross@android.com> Signed-off-by: Erik Gilling <konkers@android.com>
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cc0e72b8 |
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15-Jul-2010 |
Changhwan Youn <chaos.youn@samsung.com> |
ARM: S5PV310: Add new Kconfig and Makefiles This patch adds the Kconfig and Makefile for the new S5PV310 SoC. It also updates arch/arm Kconfig, Makefile and arch/arm/mm/Kconfig to include support for the new S5PV310. Signed-off-by: Changhwan Youn <chaos.youn@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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f159f4ed |
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05-Jul-2010 |
Tony Lindgren <tony@atomide.com> |
ARM: 6207/1: Replace CONFIG_HAS_TLS_REG with HWCAP_TLS and check for it on V6 The TLS register is only available on ARM1136 r1p0 and later. Set HWCAP_TLS flags if hardware TLS is available and test for it if CONFIG_CPU_32v6K is not set for V6. Note that we set the TLS instruction in __kuser_get_tls dynamically as suggested by Jamie Lokier <jamie@shareable.org>. Also the __switch_to code is optimized out in most cases as suggested by Nicolas Pitre <nico@fluxnic.net>. Reviewed-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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42c4dafe |
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01-Jul-2010 |
Catalin Marinas <catalin.marinas@arm.com> |
ARM: 6202/1: Do not ARM_DMA_MEM_BUFFERABLE on RealView boards with L210/L220 RealView boards with certain revisions of the L210/L220 cache controller may have issues (hardware deadlock) with the mandatory barriers (DSB followed by an L2 cache sync) when ARM_DMA_MEM_BUFFERABLE is enabled. The patch disables ARM_DMA_MEM_BUFFERABLE for these boards. Tested-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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ad642d9f |
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21-Jun-2010 |
Catalin Marinas <catalin.marinas@arm.com> |
ARM: 6188/1: Add a config option for the ARM11MPCore DMA cache maintenance workaround Commit f4d6477f introduced a workaround for the lack of hardware broadcasting of the cache maintenance operations on ARM11MPCore. However, the workaround is only valid on CPUs that do not do speculative loads into the D-cache. This patch adds a Kconfig option with the corresponding help to make the above clear. When the DMA_CACHE_RWFO option is disabled, the kernel behaviour is that prior to the f4d6477f commit. This also allows ARMv6 UP processors with speculative loads to work correctly. For other processors, a different workaround may be needed. Cc: Ronen Shitrit <rshitrit@marvell.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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47ab0dee |
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15-May-2010 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: Optionally allow ARMv6 to use 'normal, bufferable' memory for DMA Provide a configuration option to allow the ARMv6 to use normal bufferable memory for coherent DMA. This option is forced to 'y' for ARMv7, and offered as a configuration option on ARMv6. Enabling this option requires drivers to have the necessary barriers to ensure that data in DMA coherent memory is visible prior to the DMA operation commencing. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
66b19647 |
|
28-Apr-2010 |
Haojian Zhuang <haojian.zhuang@marvell.com> |
[ARM] mmp: enable L2 in mmp2 Enable Tauros2 L2 in mmp2. Tauros2 L2 is shared in Marvell ARM cores. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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#
e220ba60 |
|
11-Aug-2009 |
Dave Estes <cestes@quicinc.com> |
arm: mm: qsd8x50: Fix incorrect permission faults Handle incorrectly reported permission faults for qsd8650. On permission faults, retry MVA to PA conversion. If retry detects translation fault. Report as translation fault. Cc: Jamie Lokier <jamie@shareable.org> Signed-off-by: Dave Estes <cestes@quicinc.com>
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#
fef88f10 |
|
28-Feb-2010 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: Add Versatile Express CA9x4 processor support Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
#
8e797a7e |
|
03-Apr-2010 |
Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> |
ARM: 6027/1: ux500: enable l2x0 support This enables the l2x0 support and ensures that the secondary CPU can see the page table and secondary data at this point. Signed-off-by: srinidhi kasagar <srinidhi.kasagar@stericsson.com> Acked-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
e7c5650f |
|
24-Mar-2010 |
Catalin Marinas <catalin.marinas@arm.com> |
ARM: 5996/1: ARM: Change the mandatory barriers implementation (4/4) The mandatory barriers (mb, rmb, wmb) are used even on uniprocessor systems for things like ordering Normal Non-cacheable memory accesses with DMA transfer (via Device memory writes). The current implementation uses dmb() for mb() and friends but this is not sufficient. The DMB only ensures the relative ordering of the observability of accesses by other processors or devices acting as masters. In case of DMA transfers started by writes to device memory, the relative ordering is not ensured because accesses to slave ports of a device are not considered observable by the DMB definition. A DSB is required for the data to reach the main memory (even if mapped as Normal Non-cacheable) before the device receives the notification to begin the transfer. Furthermore, some L2 cache controllers (like L2x0 or PL310) buffer stores to Normal Non-cacheable memory and this would need to be drained with the outer_sync() function call. The patch also allows platforms to define their own mandatory barriers implementation by selecting CONFIG_ARCH_HAS_BARRIERS and providing a mach/barriers.h file. Note that the SMP barriers are unchanged (being DMBs as before) since they are only guaranteed to work with Normal Cacheable memory. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
23107c54 |
|
24-Mar-2010 |
Catalin Marinas <catalin.marinas@arm.com> |
ARM: 5995/1: ARM: Add L2x0 outer_sync() support (3/4) The L2x0 cache controllers need to explicitly drain their write buffer even for Normal Noncacheable memory accesses. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
319f551a |
|
24-Mar-2010 |
Catalin Marinas <catalin.marinas@arm.com> |
ARM: 5994/1: ARM: Add outer_cache_fns.sync function pointer (2/4) This patch introduces the outer_cache_fns.sync function pointer together with the OUTER_CACHE_SYNC config option that can be used to drain the write buffer of the outer cache. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
d6d502fa |
|
21-Feb-2010 |
Kukjin Kim <kgene.kim@samsung.com> |
ARM: 5952/1: ARM: MM: Add ARM_L1_CACHE_SHIFT_6 for handle inside each ARCH Kconfig Add ARM_L1_CACHE_SHIFT_6 to arch/arm/Kconfig to allow CPUs with L1 cache lines which are 64bytes to indicate this without having to alter the arch/arm/mm/Kconfig entry each time. Update the mm Kconfig so that ARM_L1_CACHE_SHIFT default value uses this and change OMAP3 and S5PC1XX to select ARM_L1_CACHE_SHIFT_6. Acked-by: Ben Dooks <ben-linux@fluff.org> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
d309427e |
|
04-Feb-2010 |
Santosh Shilimkar <santosh.shilimkar@ti.com> |
ARM: 5917/1: OMAP4: Add L2 Cache support This patch adds L2 Cache support for OMAP4. External L2 cache is used in OMAP4 CC: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
1a28e3d9 |
|
01-Feb-2010 |
Tony Lindgren <tony@atomide.com> |
ARM: 5911/1: ARM: Select CPU_32v6K for CPU_V7 only if ARCH_OMAP2 is not selected Otherwise the kernel built with both CPU_V6 and CPU_V7 will not boot on omap2. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
#
4da8b820 |
|
18-Dec-2009 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: Kill CONFIG_CPU_32 26-bit ARM support was removed a long time ago, and this symbol has been defined to be 'y' ever since. As it's never disabled anymore, we can kill it without any side effects. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
#
573a652f |
|
24-Nov-2009 |
Lennert Buytenhek <buytenh@marvell.com> |
ARM: Add Tauros2 L2 cache controller support Support for the Tauros2 L2 cache controller as used with the PJ1 and PJ4 CPUs. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
|
#
edabd38e |
|
06-Aug-2009 |
Saeed Bishara <saeed@marvell.com> |
ARM: add base support for Marvell Dove SoC The Marvell Dove (88AP510) is a high-performance, highly integrated, low power SoC with high-end ARM-compatible processor (known as PJ4), graphics processing unit, high-definition video decoding acceleration hardware, and a broad range of peripherals. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
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#
39416838 |
|
19-Nov-2009 |
Marek Szyprowski <m.szyprowski@samsung.com> |
ARM: 5791/1: ARM: MM: use 64bytes of L1 cache on plat S5PC1xx Samsung S5PC1xx SoCs are based on ARM Coretex8, which has 64 bytes of L1 cache line size. Enable proper handling of L1 cache on these SoCs. Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
c768e676 |
|
20-Oct-2009 |
Hartley Sweeten <hartleys@visionengravers.com> |
ARM: 5769/1: CPU_ARM920T: remove dead Maverick EP9312 URL Remove the URL listed for Maverick EP9312 since it is not available and modify the help text appropriately. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Acked-by: Ryan Mallon <ryan@bluewatersys.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
4fb28474 |
|
25-Sep-2009 |
Kirill A. Shutemov <kirill@shutemov.name> |
ARM: 5727/1: Pass IFSR register to do_PrefetchAbort() Instruction fault status register, IFSR, was introduced on ARMv6 to provide status information about the last insturction fault. It needed for proper prefetch abort handling. Now we have three prefetch abort model: * legacy - for CPUs before ARMv6. They doesn't provide neither IFSR nor IFAR. We simulate IFSR with section translation fault status for them to generalize code; * ARMv6 - provides IFSR, but not IFAR; * ARMv7 - provides both IFSR and IFAR. Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
#
910a17e5 |
|
15-Sep-2009 |
Kirill A. Shutemov <kirill@shutemov.name> |
ARM: 5700/1: ARM: Introduce ARM_L1_CACHE_SHIFT to define cache line size Currently kernel believes that all ARM CPUs have L1_CACHE_SHIFT == 5. It's not true at least for CPUs based on Cortex-A8. List of CPUs with cache line size != 32 should be expanded later. Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
#
0b260fd4 |
|
02-Jul-2009 |
Alessandro Rubini <rubini@gnudd.com> |
[ARM] 5587/1: nomadik: add l2cc Signed-off-by: Alessandro Rubini <rubini@unipv.it> Acked-by: Andrea Gallo <andrea.gallo@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
a22f277b |
|
31-May-2009 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] Kconfig: remove 'default n' Kconfig entries default to n, so there's no need for this to be explicitly specified. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
#
26584853 |
|
30-May-2009 |
Catalin Marinas <catalin.marinas@arm.com> |
Add core support for ARMv6/v7 big-endian Starting with ARMv6, the CPUs support the BE-8 variant of big-endian (byte-invariant). This patch adds the core support: - setting of the BE-8 mode via the CPSR.E register for both kernel and user threads - big-endian page table walking - REV used to rotate instructions read from memory during fault processing as they are still little-endian format - Kconfig and Makefile support for BE-8. The --be8 option must be passed to the final linking stage to convert the instructions to little-endian Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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#
1b504bbe |
|
30-May-2009 |
Colin Tuckley <colin.tuckley@arm.com> |
RealView: Add support for the RealView/PBX platform This is a RealView platform supporting core tiles with ARM11MPCore, Cortex-A8 or Cortex-A9 (multicore) processors. It has support for MMC, CompactFlash, PCI-E. Signed-off-by: Colin Tuckley <colin.tuckley@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
|
#
28853ac8 |
|
25-Mar-2009 |
Paulius Zaleckas <paulius.zaleckas@teltonika.lt> |
ARM: Add support for FA526 v2 Adds support for Faraday FA526 core. This core is used at least by: Cortina Systems Gemini and Centroid family Cavium Networks ECONA family Grain Media GM8120 Pixelplus ImageARM Prolific PL-1029 Faraday IP evaluation boards v2: - move TLB_BTB to separate patch - update copyrights Signed-off-by: Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
|
#
49cbe786 |
|
19-Jan-2009 |
Eric Miao <eric.miao@marvell.com> |
[ARM] pxa: add base support for Marvell's PXA168 processor line """The Marvell® PXA168 processor is the first in a family of application processors targeted at mass market opportunities in computing and consumer devices. It balances high computing and multimedia performance with low power consumption to support extended battery life, and includes a wealth of integrated peripherals to reduce overall BOM cost .... """ See http://www.marvell.com/featured/pxa168.jsp for more information. 1. Marvell Mohawk core is a hybrid of xscale3 and its own ARM core, there are many enhancements like instructions for flushing the whole D-cache, and so on 2. Clock reuses Russell's common clkdev, and added the basic support for UART1/2. 3. Devices are a bit different from the 'mach-pxa' way, the platform devices are now dynamically allocated only when necessary (i.e. when pxa_register_device() is called). Description for each device are stored in an array of 'struct pxa_device_desc'. Now that: a. this array of device description is marked with __initdata and can be freed up system is fully up b. which means board code has to add all needed devices early in his initializing function c. platform specific data can now be marked as __initdata since they are allocated and copied by platform_device_add_data() 4. only the basic UART1/2/3 are added, more devices will come later. Signed-off-by: Jason Chagas <chagas@marvell.com> Signed-off-by: Eric Miao <eric.miao@marvell.com>
|
#
cb88214d |
|
07-Feb-2009 |
Sascha Hauer <s.hauer@pengutronix.de> |
[ARM] MX31/MX35: Add l2x0 cache support Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
#
4c3ea371 |
|
01-Dec-2008 |
Jon Callan <Jon.Callan@arm.com> |
RealView: Add Cortex-A9 support to the EB board This patch adds the necessary definitions and Kconfig entries to enable Cortex-A9 (ARMv7 SMP) tiles on the RealView/EB board. Signed-off-by: Jon Callan <Jon.Callan@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
|
#
c750815e |
|
26-Oct-2008 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] Arrange for platforms to select appropriate CPU support Rather than: config CPU_BLAH bool depends on ARCH_FOO || MACH_BAR default y if ARCH_FOO || MACH_BAR arrange for ARCH_FOO and MACH_BAR to select CPU_BLAH directly. Acked-by: Nicolas Pitre <nico@marvell.com> Acked-by: Andrew Victor <linux@maxim.org.za> Acked-by: Brian Swetland <swetland@google.com> Acked-by: Eric Miao <eric.miao@marvell.com> Acked-by: Nicolas Bellido <ml@acolin.be> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
#
1637de0c |
|
09-Sep-2008 |
Brian Swetland <swetland@google.com> |
[ARM] msm: rename ARCH_MSM7X00A to ARCH_MSM The MSM architecture covers a wider family of chips than just the MSM7X00A. Move to a more generic name, in perparation for supporting the specific SoC variants as sub-architectures (ARCH_MSM7X01A, ARCH_MSM722X, etc). This gives us ARCH_MSM for the (many) common peripherals. This also removes the unused/obsolete config item MSM7X00A_IDLE. Signed-off-by: Brian Swetland <swetland@google.com>
|
#
2885f000 |
|
09-Oct-2008 |
Syed Mohammed, Khasim <khasim@ti.com> |
ARM: OMAP3: Add minimal Beagle board support Add minimal Beagle board support. Based on earlier patches by Syed Mohammed Khasim with some fixes from linux-omap tree. Signed-off-by: Syed Mohammed Khasim <khasim@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
|
#
4360bb41 |
|
23-Sep-2008 |
Ronen Shitrit <rshitrit@marvell.com> |
[ARM] Kirkwood: add support for L2 cache WB/WT selection Feroceon L2 cache can work in eighther write through or write back mode on Kirkwood. Add the option to configure this mode according to Kconfig. Signed-off-by: Ronen Shitrit <rshitrit@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
|
#
905a09d5 |
|
06-Jun-2008 |
Eric Miao <eric.miao@marvell.com> |
[ARM] pxa: add support for L2 outer cache on XScale3 (attempt 2) (20072fd0c93349e19527dd2fa9588b4335960e62 lost most of its changes somehow, came from a mbox archive applied with git-am. No idea what happened. This puts back the missing bits. --rmk) The initial patch from Lothar, and Lennert make it into a cleaner one, modified and tested on PXA320 by Eric Miao. This patch moves the L2 cache operations out of proc-xsc3.S into dedicated outer cache support code. CACHE_XSC3L2 can be deselected so no L2 cache specific code will be linked in, and that L2 enable bit will not be set, this applies to the following cases: a. _only_ PXA300/PXA310 support included and no L2 cache wanted b. PXA320 support included, but want L2 be disabled So the enabling of L2 depends on two things: - CACHE_XSC3L2 is selected - and L2 cache is present Where the latter is only a safeguard (previous testing shows it works OK even when this bit is turned on). IXP series of processors with XScale3 cannot disable L2 cache for the moment since they depend on the L2 cache for its coherent memory, so IXP may always select CACHE_XSC3L2. Other L2 relevant bits are always turned on (i.e. the original code enclosed by #if L2_CACHE_ENABLED .. #endif), as they showed no side effects. Specifically, these bits are: - OC bits in TTBASE register (table walk outer cache attributes) - LLR Outer Cache Attributes (OC) in Auxiliary Control Register Signed-off-by: Lothar WaÃ<9f>mann <LW@KARO-electronics.de> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Eric Miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
#
221d62c1 |
|
16-Jul-2008 |
Sascha Hauer <s.hauer@pengutronix.de> |
[ARM] mx2: add missing Kconfig dependency It seems this small label was lost in the last merge. Without it no CPU type is selected for the MX2 family of processors. And a build will fail badly... Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
#
61352667 |
|
10-Jul-2008 |
sedji gaouaou <sedji.gaouaou@atmel.com> |
[ARM] 5130/4: Support for the at91sam9g20 Support for the at91sam9g20 : Atmel 400Mhz ARM 926ej-s SOC. AT91sam9g20 is an evolution of the at91sam9260 with a faster clock speed. We created a new board for this device but based the chip support directly on 9260 files with little updates. Here is the chip page on Atmel wabsite: http://atmel.com/dyn/products/product_card.asp?part_id=4337 Signed-off-by: Sedji Gaouaou <sedji.gaouaou@atmel.com> Signed-off-by: Justin Waters <justin.waters@timesys.com> Acked-by: Andrew Victor <linux@maxim.org.za> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
#
1bd55a43 |
|
05-Jul-2008 |
Juergen Beisert <j.beisert@pengutronix.de> |
i.MX2 family: Add basic mach support This patch adds basic mach support for the mx2 processor family, based on the original freescale code and adapted to mainline kernel coding style. This part adds the global build only. Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de>
|
#
794d15b2 |
|
22-Jun-2008 |
Stanislav Samsonov <samsonov@marvell.com> |
[ARM] add Marvell 78xx0 ARM SoC support The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring (depending on the model) one or two Feroceon CPU cores with 512K of L2 cache and VFP coprocessors running at (depending on the model) between 800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe interfaces that can each run either in x4 or quad x1 mode, three USB 2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI interface, four UARTs, and depending on the model, two or four gigabit ethernet interfaces. This patch adds basic support for the platform, and allows booting on the MV78x00 development board, with functional UARTs, SATA, PCIe, GigE and USB ports. Signed-off-by: Stanislav Samsonov <samsonov@marvell.com> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
|
#
651c74c7 |
|
22-Jun-2008 |
Saeed Bishara <saeed@marvell.com> |
[ARM] add Marvell Kirkwood (88F6000) SoC support The Marvell Kirkwood (88F6000) is a family of ARM SoCs based on a Shiva CPU core, and features a DDR2 controller, a x1 PCIe interface, a USB 2.0 interface, a SPI controller, a crypto accelerator, a TS interface, and IDMA/XOR engines, and depending on the model, also features one or two Gigabit Ethernet interfaces, two SATA II interfaces, one or two TWSI interfaces, one or two UARTs, a TDM/SLIC interface, a NAND controller, an I2S/SPDIF interface, and an SDIO interface. This patch adds supports for the Marvell DB-88F6281-BP Development Board and the RD-88F6192-NAS and the RD-88F6281 Reference Designs, enabling support for the PCIe interface, the USB interface, the ethernet interfaces, the SATA interfaces, the TWSI interfaces, the UARTs, and the NAND controller. Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
|
#
99c6dc11 |
|
22-Jun-2008 |
Lennert Buytenhek <buytenh@wantstofly.org> |
[ARM] Feroceon: L2 cache support This patch adds support for the unified Feroceon L2 cache controller as found in e.g. the Marvell Kirkwood and Marvell Discovery Duo families of ARM SoCs. Note that: - Page table walks are outer uncacheable on Kirkwood and Discovery Duo, since the ARMv5 spec provides no way to indicate outer cacheability of page table walks (specifying it in TTBR[4:3] is an ARMv6+ feature). This requires adding L2 cache clean instructions to proc-feroceon.S (dcache_clean_area(), set_pte()) as well as to tlbflush.h ({flush,clean}_pmd_entry()). The latter case is handled by defining a new TLB type (TLB_FEROCEON) which is almost identical to the v4wbi one but provides a TLB_L2CLEAN_FR flag. - The Feroceon L2 cache controller supports L2 range (i.e. 'clean L2 range by MVA' and 'invalidate L2 range by MVA') operations, and this patch uses those range operations for all Linux outer cache operations, as they are faster than the regular per-line operations. L2 range operations are not interruptible on this hardware, which avoids potential livelock issues, but can be bad for interrupt latency, so there is a compile-time tunable (MAX_RANGE_SIZE) which allows you to select the maximum range size to operate on at once. (Valid range is between one cache line and one 4KiB page, and must be a multiple of the line size.) Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
|
#
777f9beb |
|
22-Jun-2008 |
Lennert Buytenhek <buytenh@marvell.com> |
[ARM] add Marvell Loki (88RC8480) SoC support The Marvell Loki (88RC8480) is an ARM SoC based on a Feroceon CPU core running at between 400 MHz and 1.0 GHz, and features a 64 bit DDR controller, 512K of internal SRAM, two x4 PCI-Express ports, two Gigabit Ethernet ports, two 4x SAS/SATA controllers, two UARTs, two TWSI controllers, and IDMA/XOR engines. This patch adds support for the Marvell LB88RC8480 Development Board, enabling the use of the PCIe interfaces, the ethernet interfaces, the TWSI interfaces and the UARTs. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
|
#
0ed15071 |
|
23-Apr-2008 |
Lennert Buytenhek <buytenh@wantstofly.org> |
[ARM] Feroceon: Feroceon-specific WA-cache compatible {copy,clear}_user_page() This patch implements a set of Feroceon-specific {copy,clear}_user_page() routines that perform more optimally than the generic implementations. This also deals with write-allocate caches (Feroceon can run L1 D in WA mode) which otherwise prevents Linux from booting. [nico: optimized the code even further] Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Tested-by: Sylver Bruneau <sylver.bruneau@googlemail.com> Tested-by: Martin Michlmayr <tbm@cyrius.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
|
#
a7039bd6 |
|
23-Apr-2008 |
Lennert Buytenhek <buytenh@wantstofly.org> |
[ARM] feroceon: remove CONFIG_CPU_DCACHE_WRITETHROUGH check Since the Feroceon doesn't have a global WT override bit like ARM926 does, remove all code relating to this mode of operation from proc-feroceon.S. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
|
#
4a1fd556 |
|
21-Apr-2008 |
Catalin Marinas <catalin.marinas@arm.com> |
[ARM] fix 48d7927bdf071d05cf5d15b816cf06b0937cb84f The proc-*.S files have the _prefetch_abort pointer placed at the end of the processor structure but the cpu-multi32.h defines it in the second position. The patch also fixes the support for XSC3 and the MMU-less CPUs (740, 7tdmi, 940, 946 and 9tdmi). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
#
ba927951 |
|
18-Apr-2008 |
Catalin Marinas <catalin.marinas@arm.com> |
Allow the L2X0 outer cache support to be configurable By default, this option was selected by the platform Kconfig. This patch adds "depends on" to L2X0 so that it can be enabled/disabled manually. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
|
#
bc02c58b |
|
18-Apr-2008 |
Bahadir Balban <bahadir.balban@arm.com> |
RealView: Add the configuration and build changes for PB1176 This patch enables the building of Linux for the PB1176 platform. Signed-off-by: Bahadir Balban <bahadir.balban@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
|
#
78fdcb42 |
|
18-Apr-2008 |
Bahadir Balban <bahadir.balban@arm.com> |
RealView: Enable the configuration options for PB11MPCore This patch adds the PB11MPCore support to the corresponding Kconfig and Makefile to enable building. Signed-off-by: Bahadir Balban <bahadir.balban@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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#
41267e20 |
|
18-Apr-2008 |
Catalin Marinas <catalin.marinas@arm.com> |
RealView: Allow ARMv7 support for RealView/EB This patch changes the CPU_V7 configuration dependency to allow MACH_REALVIEW_EB. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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#
48d7927b |
|
18-Apr-2008 |
Paul Brook <paul@codesourcery.com> |
Add a prefetch abort handler This patch adds a prefetch abort handler similar to the data abort one and renames the latter for consistency. Initial implementation by Paul Brook with some renaming by Catalin Marinas. Signed-off-by: Paul Brook <paul@codesourcery.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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#
d7f864be |
|
18-Apr-2008 |
Catalin Marinas <catalin.marinas@arm.com> |
ARMv7: Add support for the ThumbEE state saving/restoring This patch adds the detection and handling of the ThumbEE extension on ARMv7 CPUs. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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#
9dd0b194 |
|
27-Mar-2008 |
Lennert Buytenhek <buytenh@wantstofly.org> |
Orion: orion -> orion5x rename Do a global s/orion/orion5x/ of the Orion 5x-specific bits (i.e. not the plat-orion bits.) Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Reviewed-by: Tzachi Perelstein <tzachi@marvell.com> Acked-by: Saeed Bishara <saeed@marvell.com> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Nicolas Pitre <nico@marvell.com>
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#
d910a0aa |
|
06-Nov-2007 |
Tzachi Perelstein <tzachi@marvell.com> |
[ARM] Feroceon: support old cores with ARM926 ID This enables the usage of some old Feroceon cores for which the CPU ID is equal to the ARM926 ID. Relevant for Feroceon-1850 and old Feroceon-2850. Signed-off-by: Tzachi Perelstein <tzachi@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
e50d6409 |
|
23-Oct-2007 |
Assaf Hoffman <hoffman@marvell.com> |
[ARM] Marvell Feroceon CPU core support The Feroceon is a family of independent ARMv5TE compliant CPU core implementations, supporting a variable depth pipeline and out-of-order execution. The Feroceon is configurable with VFP support, and the later models in the series are superscalar with up to two instructions per clock cycle. This patch adds the initial low-level cache/TLB handling for this core. Signed-off-by: Assaf Hoffman <hoffman@marvell.com> Reviewed-by: Tzachi Perelstein <tzachi@marvell.com> Reviewed-by: Nicolas Pitre <nico@marvell.com> Reviewed-by: Lennert Buytenhek <buytenh@marvell.com> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
2b3b3516 |
|
24-Jan-2008 |
Andrew Victor <linux@maxim.org.za> |
[ARM] 4764/1: [AT91] AT91CAP9 core support Add support for Atmel's AT91CAP9 Customizable Microcontroller family. <http://www.atmel.com/products/AT91CAP/Default.asp> Signed-off-by: Stelian Pop <stelian@popies.net> Signed-off-by: Andrew Victor <linux@maxim.org.za> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
3042102a |
|
26-Nov-2007 |
Brian Swetland <swetland@google.com> |
[ARM] msm: core platform support for ARCH_MSM7X00A - core header files for arch-msm - Kconfig and Makefiles to enable ARCH_MSM7X00A builds - MSM7X00A specific arch_idle - peripheral iomap and irq number definitions Signed-off-by: Brian Swetland <swetland@google.com>
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#
2c8086a5 |
|
11-Sep-2007 |
eric miao <eric.y.miao@gmail.com> |
[ARM] pxa: PXA3xx base support Signed-off-by: eric miao <eric.y.miao@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
fa0b6251 |
|
19-Sep-2007 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] pxa: Make CPU_XSCALE depend on PXA25x or PXA27x PXA3 SoCs are supported by the Xscale3 CPU code rather than the Xscale CPU code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
52c543f9 |
|
09-Jul-2007 |
Quinn Jensen <qcjensen@gmail.com> |
[ARM] 4461/1: MXC platform and i.MX31ADS core support This patch adds the foundation pieces for the Freescale MXC platforms, including i.MX2 and i.MX3 based systems. The bare-bones MX31 support in this patch boots to the rootdev panic with 8250 serial console configured "console=ttyS0,115200". It assumes that Redboot is the boot loader. Signed-off-by: Quinn Jensen <quinn.jensen@freescale.com> Acked-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
11179d8c |
|
20-Jul-2007 |
Catalin Marinas <catalin.marinas@arm.com> |
[ARM] 4497/1: Only allow safe cache configurations on ARMv6 and later Currently, Linux doesn't generate correct page tables for ARMv6 and later cores if the cache policy is different from the default one (it may lead to strongly ordered or shared device mappings). This patch disallows cache policies other than writeback and the CPU_[ID]CACHE_DISABLE options only affect the CP15 system control register rather than the page tables. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
2eb8c82b |
|
20-Jul-2007 |
Catalin Marinas <catalin.marinas@arm.com> |
[ARM] 4503/1: nommu: Add noMMU support for ARMv7 This patch adds the necessary ifdef's to the proc-v7.S code and defines the v7wbi_tlb_fns macro in pgtable-nommu.h Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
7092fc38 |
|
20-Jul-2007 |
Catalin Marinas <catalin.marinas@arm.com> |
[ARM] 4498/1: ARMv7: Remove the L2 cache configuration via the aux ctrl register The auxiliary control and the L2 auxiliary control registers are Cortex-A8 specific. They need to be removed from the generic ARMv7 support code. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
7b4c965a |
|
20-Jul-2007 |
Catalin Marinas <catalin.marinas@arm.com> |
[ARM] 4504/1: nommu: Fix the ARMv6 support for MMU-less platforms With this patch, Kconfig only selects CPU_HAS_ASID for the MMU case. It also corrects the typo in the v6wbi_tlb_fns definition in pgtable-nommu.h. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
367afaf8 |
|
20-Jul-2007 |
Catalin Marinas <catalin.marinas@arm.com> |
[ARM] 4501/1: nommu: Select TLS register emulation if ARMv6 and not v6K If not MMU and not v6K, access to the TLS register has to be emulated. MMU-less systems do not provide a high page for kuser helpers. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
2ccdd1e7 |
|
18-May-2007 |
Catalin Marinas <catalin.marinas@arm.com> |
[ARM] 4394/1: ARMv7: Add the TLB range operations We are currently using the ARMv6 operations but need to duplicate some of the code because of the introduction of the new CPU barrier instructions in ARMv7. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
516793c6 |
|
17-May-2007 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] ARMv6: add CPU_HAS_ASID configuration Presently, we check for the minimum ARM architecture that we're building for to determine whether we need ASID support. This is wrong - if we're going to support a range of CPUs which include ARMv6 or higher, we need the ASID. Convert the checks to use a new configuration symbol, and arrange for ARMv6 and higher CPU entries to select it. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
c53c9cf6 |
|
11-May-2007 |
Andrew Victor <andrew@sanpeople.com> |
[ARM] 4331/3: Support for Micrel/Kendin KS8695 processor Add core support for the Kendin/Micrel KS8695 processor family. It is an ARM922-T based SoC with integrated USART, 4-port Ethernet Switch, WAN Ethernet port, and optional PCI Host bridge, etc. http://www.micrel.com/page.do?page=product-info/sys_on_chip.jsp This patch is based on earlier patches from Lennert Buytenhek, Ben Dooks and Greg Ungerer posted to the arm-linux-kernel mailing list in March 2006; and Micrel's 2.6.9 port. Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
877d7720 |
|
11-May-2007 |
Andrew Victor <andrew@sanpeople.com> |
[ARM] 4370/3: AT91: Support for Atmel AT91SAM9RL processors. Add support for Atmel's new AT91SAM9RL range of processors. Includes similar peripherals as other AT91SAM9 processors, but with a High-speed USB controller and various sizes of internal SRAM. Signed-off-by: Nicolas Ferre <nicolas.ferre@rfo.atmel.com> Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
7c6337e2 |
|
30-Apr-2007 |
Kevin Hilman <khilman@mvista.com> |
[ARM] 4303/3: base kernel support for TI DaVinci Add base kernel support for the TI DaVinci platform. This patch only includes interrupts, timers, CPU identification, serial support and basic power and sleep controller init. More drivers to come. Signed-off-by: Kevin Hilman <khilman@mvista.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
23688e99 |
|
08-May-2007 |
Catalin Marinas <catalin.marinas@arm.com> |
[ARM] armv7: add Makefile and Kconfig entries This patch adds the necessary lines to the Makefile and Kconfig files for enabling the compilation of the ARMv7 CPU support. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
9918cda5 |
|
16-Feb-2007 |
Uwe Kleine-König <ukleinek@informatik.uni-freiburg.de> |
[ARM] 4210/1: base for new machine type "NetSilicon NS9360" Signed-off-by: Uwe Kleine-König <ukleinek@informatik.uni-freiburg.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
6340aa61 |
|
17-Feb-2007 |
Robert P. J. Day <rpjday@mindspring.com> |
kbuild: Replace remaining "depends" with "depends on" Replace the very few remaining "depends" Kconfig directives with "depends on". Signed-off-by: Robert P. J. Day <rpjday@mindspring.com> Signed-off-by: Adrian Bunk <bunk@stusta.de>
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#
382266ad |
|
05-Feb-2007 |
Catalin Marinas <catalin.marinas@arm.com> |
[ARM] 4135/1: Add support for the L210/L220 cache controllers This patch adds the support for the L210/L220 (outer) cache controller. The cache range operations are done by index/way since L2 cache controller only accepts physical addresses. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
b2c65616 |
|
08-Feb-2007 |
Andrew Victor <andrew@sanpeople.com> |
[ARM] 4145/2: AT91: Add support for AT91SAM9263 processor Add support for the Atmel AT91SAM9263 processor. It is similar to the AT91SAM9260 but with more integrated peripherals, 5 GPIO banks, etc. Original patch from Nicolas Ferre. Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
953233dc |
|
05-Feb-2007 |
Catalin Marinas <catalin.marinas@arm.com> |
[ARM] 4134/1: Add generic support for outer caches The outer cache can be L2 as on RealView/EB MPCore platform or even L3 or further on ARMv7 cores. This patch adds the generic support for flushing the outer cache in the DMA operations. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
285f5fa7 |
|
06-Dec-2006 |
Dan Williams <dan.j.williams@intel.com> |
[ARM] 3995/1: iop13xx: add iop13xx support The iop348 processor integrates an Xscale (XSC3 512KB L2 Cache) core with a Serial Attached SCSI (SAS) controller, multi-ported DDR2 memory controller, 3 Application Direct Memory Access (DMA) controllers, a 133Mhz PCI-X interface, a x8 PCI-Express interface, and other peripherals to form a system-on-a-chip RAID subsystem engine. The iop342 processor replaces the SAS controller with a second Xscale core for dual core embedded applications. The iop341 processor is the single core version of iop342. This patch supports the two Intel customer reference platforms iq81340mc for external storage and iq81340sc for direct attach (HBA) development. The developer's manual is available here: ftp://download.intel.com/design/iio/docs/31503701.pdf Changelog: * removed virtual addresses from resource definitions * cleaned up some unnecessary #include's Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
f5236225 |
|
01-Dec-2006 |
Dan Williams <dan.j.williams@intel.com> |
[ARM] 3967/1: xsc3: make branch predication configurable on xsc3 Remove BTB_ENABLE from proc-xsc3.S On some early revisions of xsc3 enabling the branch target buffer can cause crashes, see erratum #42. Cc: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
3cb2fccc |
|
29-Nov-2006 |
Matt LaPlante <kernel1@cyberdogtech.com> |
Fix misc Kconfig typos Fix various Kconfig typos. Signed-off-by: Matt LaPlante <kernel1@cyberdogtech.com> Acked-by: Randy Dunlap <randy.dunlap@oracle.com> Signed-off-by: Adrian Bunk <bunk@stusta.de>
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#
6afd6fae |
|
28-Sep-2006 |
Hyok S. Choi <hyok.choi@samsung.com> |
[ARM] nommu: confirms the CR_V bit in nommu mode In nommu mode, the exception vector location depends on the platforms. Some of the implementations may have some special exception control forwarding method in their ROM/flash and for some of them has its own re-mapping mechanism by the h/w. This patch introduces a special configuration CONFIG_CPU_HIGH_VECTOR which turns on the CR_V bit in nommu mode. The CR_V bit is turned off by default. This feature depends on CP15 and does not supported by ARM740. Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
#
0f45d7f3 |
|
28-Sep-2006 |
Hyok S. Choi <hyok.choi@samsung.com> |
[ARM] nommu: abort handler fixup for !CPU_CP15_MMU cores. There is no FSR/FAR register on no-CP15 or MPU cores. This patch adds a dummy abort handler which returns zero for the base restored Data Abort model !CPU_CP15_MMU cores. The abort-lv4t.S is still used with the fix-up for the base updated Data Abort model cores. Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
#
6b237a35 |
|
27-Sep-2006 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] Make !MMU CPUs depend on !MMU Don't offer non-MMU based CPUs for selection when CONFIG_MMU is set. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
f37f46eb |
|
26-Sep-2006 |
Hyok S. Choi <hyok.choi@samsung.com> |
[ARM] nommu: add ARM946E-S core support This patch adds ARM946E-S core support which has typically 8KB I&D cache. It has a MPU and supports ARMv5TE instruction set. Because the ARM946E-S core can be synthesizable with various cache size, CONFIG_CPU_DCACHE_SIZE is defined for vendor specific configurations. Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
d60674eb |
|
26-Sep-2006 |
Hyok S. Choi <hyok.choi@samsung.com> |
[ARM] nommu: add ARM940T core support This patch adds ARM940T core support which has 4KB D-cache, 4KB I-cache and a MPU. Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
#
43f5f014 |
|
26-Sep-2006 |
Hyok S. Choi <hyok.choi@samsung.com> |
[ARM] nommu: add ARM9TDMI core support This patch adds ARM9TDMI core support which has no cache and no CP15 register(no memory control unit). Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
#
b731c311 |
|
26-Sep-2006 |
Hyok S. Choi <hyok.choi@samsung.com> |
[ARM] nommu: add ARM740T core support This patch adds ARM740T core support which has a MPU and 4KB or 8KB cache. Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
#
07e0da78 |
|
26-Sep-2006 |
Hyok S. Choi <hyok.choi@samsung.com> |
[ARM] nommu: add ARM7TDMI core support This patch adds ARM7TDMI core support which has no cache and no CP15 register(no memory control unit). Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
#
f12d0d7c |
|
26-Sep-2006 |
Hyok S. Choi <hyok.choi@samsung.com> |
[ARM] nommu: manage the CP15 things All the current CP15 access codes in ARM arch can be categorized and conditioned by the defines as follows: Related operation Safe condition a. any CP15 access !CPU_CP15 b. alignment trap CPU_CP15_MMU c. D-cache(C-bit) CPU_CP15 d. I-cache CPU_CP15 && !( CPU_ARM610 || CPU_ARM710 || CPU_ARM720 || CPU_ARM740 || CPU_XSCALE || CPU_XSC3 ) e. alternate vector CPU_CP15 && !CPU_ARM740 f. TTB CPU_CP15_MMU g. Domain CPU_CP15_MMU h. FSR/FAR CPU_CP15_MMU For example, alternate vector is supported if and only if "CPU_CP15 && !CPU_ARM740" is satisfied. Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
#
fefdaa06 |
|
26-Sep-2006 |
Hyok S. Choi <hyok.choi@samsung.com> |
[ARM] nommu: defines CPU_CP15, CPU_CP15_MMU and CPU_CP15_MPU By merging of uClinux/ARM, we need to treat various CPU cores which have MMU, MPU or even none for memory management. The memory management coprocessors are controlled by CP15 register set and the ARM core family can be categorized by 5 groups by the register ; G-a. CP15 is MMU : 610, 710, 720, 920, 922, 925, 926, 1020, 1020e, 1022, v6 and the derivations sa1100, sa110, xscale, xsc3. G-b. CP15 is MPU : 740, 940, 946, 996, 1156. G-c. CP15 is MPU or MMU : 1026 (selectable by schematic design) G-d. CP15 is exist, but nothing for memory managemnt : 966, 968. G-e. no-CP15 : 7tdmi, 9tdmi, 9e, 9ej This patch defines CPU_CP15, CPU_CP15_MMU and CPU_CP15_MPU. Thus the family can be defined as : - CPU_CP15 only : G-d - CPU_CP15_MMU(implies CPU_CP15) : G-a, G-c(selectable) - CPU_CP15_MPU(implies CPU_CP15) : G-b, G-c(selectable) - !CPU_CP15 : G-e Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
#
3f7e5815 |
|
18-Sep-2006 |
Lennert Buytenhek <buytenh@wantstofly.org> |
[ARM] 3817/1: iop3xx: split the iop3xx mach into iop32x and iop33x Split the iop3xx mach type into iop32x and iop33x -- split the config symbols, and move the code in the mach-iop3xx directory to the mach-iop32x and mach-iop33x directories. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
#
260e98ed |
|
27-Aug-2006 |
Lennert Buytenhek <buytenh@wantstofly.org> |
[ARM] 3761/1: fix armv4t breakage after adding thumb interworking to userspace helpers Patch from Lennert Buytenhek On armv4t systems, we have always compiled the kernel with -march=armv4 instead of -march=armv4t, which means that any use of bx will bomb out. Commit ba9b5d76372dc290b6ca04dad93927a22c2ac49a introduced the use of bx in the kernel, which means we need to compile with -march=armv4t on armv4t systems now. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
#
8fc5ffa0 |
|
29-Jun-2006 |
Andrew Victor <andrew@sanpeople.com> |
[ARM] 3675/2: Preparing for AT91SAM926 support Patch from Andrew Victor This prepares the way for adding support for the new Atmel AT91SAM926x processors. Major changes: - Rename time.c to at91rm9200_time.c - Rename common.c to at91rm9200.c - Introduce ARCH_AT91, of which ARCH_AT91RM9200, ARCH_AT91SAM9260 and ARCH_AT91SAM9261 are dependent. Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
#
f9c21a6e |
|
21-Jun-2006 |
Hyok S. Choi <hyok.choi@samsung.com> |
[ARM] nommu: avoid selecting TLB and CPU specific copy code Since uclinux doesn't make use of the TLB, including the TLB maintainence and CPU-optimised copypage functions does not make sense. Remove them. (This is part of one of Hyok's patches.) Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
#
60b6cf68 |
|
19-Jun-2006 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] nommu: we need the TLS register emulation for nommu mode Since there can be no fixed location for the TLS value with nommu systems, we must provide TLS register emulation in order to support TLS binaries on CPUs without the thread register. Part of a patch from Hyok S. Choi, and cleaned up by rmk. Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
#
3434d9d9 |
|
24-Jun-2006 |
Ben Dooks <ben-linux@fluff.org> |
[ARM] 3636/1: S3C2412: Add selection of CPU_ARM926 Patch from Ben Dooks Select CONFIG_CPU_ARM926 when CONFIG_CPU_S3C2412 is selected. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
#
bb6d8c88 |
|
19-Jun-2006 |
Sascha Hauer <sascha@saschahauer.de> |
[ARM] 3567/2: arm: base support for Hilscher netX Patch from Sascha Hauer This patch adds the base support for Hilscher's netX network processors. Signed-off-by: Robert Schwebel <r.schwebel@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
#
78818e47 |
|
16-May-2006 |
Vitaly Wool <vwool@ru.mvista.com> |
[ARM] 3466/1: [2/3] Support for Philips PNX4008 platform: chip support Patch from Vitaly Wool This patch adds basic chip support for PNX4008 ARM platform. It's basically the same as the previous one, but with the rmk's comments taken into account. Signed-off-by: Vitaly Wool <vwool@ru.mvista.com> Signed-off-by: Dmitry Pervushin <dpervushin@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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23bdf86a |
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28-Mar-2006 |
Lennert Buytenhek <buytenh@wantstofly.org> |
[ARM] 3377/2: add support for intel xsc3 core Patch from Lennert Buytenhek This patch adds support for the new XScale v3 core. This is an ARMv5 ISA core with the following additions: - L2 cache - I/O coherency support (on select chipsets) - Low-Locality Reference cache attributes (replaces mini-cache) - Supersections (v6 compatible) - 36-bit addressing (v6 compatible) - Single instruction cache line clean/invalidate - LRU cache replacement (vs round-robin) I attempted to merge the XSC3 support into proc-xscale.S, but XSC3 cores have separate errata and have to handle things like L2, so it is simpler to keep it separate. L2 cache support is currently a build option because the L2 enable bit must be set before we enable the MMU and there is no easy way to capture command line parameters at this point. There are still optimizations that can be done such as using LLR for copypage (in theory using the exisiting mini-cache code) but those can be addressed down the road. Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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e7736d47 |
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20-Mar-2006 |
Lennert Buytenhek <buytenh@wantstofly.org> |
[ARM] 3369/1: ep93xx: add core cirrus ep93xx support Patch from Lennert Buytenhek This patch adds support for the Cirrus ep93xx series of CPUs. The ep93xx is an ARM920T based CPU with two VICs, PL010 based UARTs, IrDA, MaverickCrunch floating point coprocessor, between 24 and 64 GPIOs, ethernet, OHCI USB and, depending on the model, pcmcia, raster engine, graphics accelerator, IDE controller and a bunch of other stuff. This patch adds the core ep93xx support code, and support for the Glomation GESBC-9312-sx and the Technologic Systems TS-72xx SBCs. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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48fa14f7 |
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16-Mar-2006 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] select TLS_REG_EMUL and NEEDS_SYSCALL_FOR_CMPXCHG Rather than having a growing dependency line, use select to set these configuration symbols. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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73a59c1c |
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09-Jan-2006 |
SAN People <andrew@sanpeople.com> |
[ARM] 3240/2: AT91RM9200 support for 2.6 (Core) Patch from SAN People Following changes were made to clock.c: 1) Replaced <asm/hardware/clock.h> with <linux/clk.h> 2) Removed old unused clk_enable & clk_disable. 3) Replaced clk_use/clk_unuse with clk_enable/clk_disable. Otherwise it's the same as the previous patch. Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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0fec53a2 |
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08-Jan-2006 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] Remove EPXA10DB machine support EPXA10DB seems to be uncared for: - the "PLD" code has never been merged - no one has reported that this platform has been broken since at least 2.6.10 - interest seems to have dried up around March 2003. Therefore, remove EPXA10DB support. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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1dbae815 |
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10-Nov-2005 |
Tony Lindgren <tony@atomide.com> |
[ARM] 3145/1: OMAP 3a/5: Add support for omap24xx Patch from Tony Lindgren This patch adds support for omap24xx series of processors. The files live in arch/arm/mach-omap2, and share common files with omap15xx and omap16xx processors in arch/arm/plat-omap. Omap24xx support was originally added for 2.6.9 by TI. This code was then improved and integrated to share common code with omap15xx and omap16xx processors by various omap developers, such as Paul Mundt, Juha Yrjola, Imre Deak, Tony Lindgren, Richard Woodruff, Nishant Menon, Komal Shah et al. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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3179a019 |
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10-Nov-2005 |
Tony Lindgren <tony@atomide.com> |
[ARM] 3141/1: OMAP 1/5: Update omap1 specific files Patch from Tony Lindgren This patch syncs the mainline kernel with linux-omap tree. The highlights of the patch are: - Omap1 serial pport and framebuffer init updates by Imre Deak - Add support for omap310 processor and Palm Tungsten E PDA by Laurent Gonzales, Romain Goyet, et al. Omap310 and omap1510 processors are now handled as omap15xx. - Omap1 specific changes to shared omap clock framework by Tony Lindgren - Omap1 specific changes to shared omap pin mux framework by Tony Lindgren - Other misc fixes, such as update memory timings for smc91x, omap1 specific device initialization etc. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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4a5f79e7 |
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03-Nov-2005 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM SMP] Add configuration option for ARMv6K processors The 'K' extension adds several new instructions to the ARMv6 ISA which are primerily useful for SMP. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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8ad68bbf |
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31-Oct-2005 |
Catalin Marinas <catalin.marinas@arm.com> |
[ARM] Add support for ARM RealView board Support for RealView EB. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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e03eb527 |
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05-Oct-2005 |
Catalin Marinas <catalin.marinas@arm.com> |
[ARM] 2954/1: Allow D and I cache and branch prediction disabling for ARMv6 Patch from Catalin Marinas There is no reason to not allow these config options. They are useful when the hardware has problems. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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22d8be86 |
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17-Aug-2005 |
Sean Lee <beginner2arm@eyou.com> |
[ARM] 2852/1: Correct the mistake in arch/arm/mm/Kconfig file Patch from Sean Lee In the arch/arm/mm/Kconfig file, the CPU_DCACHE_WRITETHROUGH option is depend on the CPU_DISABLE_DCACHE, but the "Disable D-Cache" option is configured as CPU_DCACHE_DISABLE. The CPU_DISABLE_DCACHE should be CPU_DCACHE_DISABLE Signed-off-by: Sean Lee <beginner2arm@eyou.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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b288f75f |
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10-Jul-2005 |
Tony Lindgren <tony@atomide.com> |
[PATCH] ARM: 2798/1: OMAP update 2/11: Change ARM Kconfig to support omap1 and omap2 Patch from Tony Lindgren This patch by Paul Mundt and other OMAP developers modifies ARM specific Kconfig to allow sharing code between OMAP1 and OMAP2 architectures. In order to share code between OMAP1 and OMAP2, all OMAP1 specific code is moved into mach-omap1 directory in the following patch. A new mach-omap2 directory will be added later on. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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038c5b60 |
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20-Jun-2005 |
Bellido Nicolas <nb-ml@be.rmk.(none)> |
[PATCH] ARM: 2686/2: AAEC-2000 Core support Patch from Bellido Nicolas Core support for AAEC-2000 based platforms. This is an updated version of the previous patch, and takes into account Russell's comments. AAED-2000 default configuration will follow as soon as some problems with the bootloader are sorted out... Signed-off-by: Nicolas Bellido Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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dcef1f63 |
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08-Jun-2005 |
Nicolas Pitre <nico@org.rmk.(none)> |
[PATCH] ARM: 2664/2: add support for atomic ops on pre-ARMv6 SMP systems Patch from Nicolas Pitre Not that there might be many of them on the planet, but at least RMK apparently has one. Signed-off-by: Nicolas Pitre Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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f8f98a93 |
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08-Jun-2005 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[PATCH] ARM: Fix Xscale copy_page implementation The ARM copypage changes in 2.6.12-rc4-git1 removed the preempt locking from the copypage functions which broke the XScale implementation. This patch fixes the locking on XScale and removes the now unneeded minicache code. Signed-off-by: Russell King <rmk@arm.linux.org.uk> Checked-by: Richard Purdie
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70489c88 |
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12-May-2005 |
Nicolas Pitre <nico@org.rmk.(none)> |
[PATCH] ARM: 2680/1: refine TLS reg availability some more again Patch from Nicolas Pitre Not all ARMv6 processors implement the TLS register. Signed-off-by: Nicolas Pitre Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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fa435435 |
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10-May-2005 |
Nicolas Pitre <nico@org.rmk.(none)> |
[PATCH] ARM: 2663/2: I can't type Patch from Nicolas Pitre Signed-off-by: Nicolas Pitre Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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4b0e07a5 |
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05-May-2005 |
Nicolas Pitre <nico@org.rmk.(none)> |
[PATCH] ARM: 2663/1: straightify TLS register emulation a bit more Patch from Nicolas Pitre This better express things, and should cover RMK's weird SMP toys. Signed-off-by: Nicolas Pitre Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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48af7215 |
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03-May-2005 |
Nicolas Pitre <nico@org.rmk.(none)> |
[PATCH] ARM: 2662/1: missing "default y" for CONFIG_HAS_TLS_REG Patch from Nicolas Pitre Signed-off-by: Nicolas Pitre Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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2d2669b6 |
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29-Apr-2005 |
Nicolas Pitre <nico@org.rmk.(none)> |
[PATCH] ARM: 2651/3: kernel helpers for NPTL support Patch from Nicolas Pitre This patch entirely reworks the kernel assistance for NPTL on ARM. In particular this provides an efficient way to retrieve the TLS value and perform atomic operations without any instruction emulation nor special system call. This even allows for pre ARMv6 binaries to be forward compatible with SMP systems without any penalty. The problematic and performance critical operations are performed through segment of kernel provided user code reachable from user space at a fixed address in kernel memory. Those fixed entry points are within the vector page so we basically get it for free as no extra memory page is required and nothing else may be mapped at that location anyway. This is different from (but doesn't preclude) a full blown VDSO implementation, however a VDSO would prevent some assembly tricks with constants that allows for efficient branching to those code segments. And since those code segments only use a few cycles before returning to user code, the overhead of a VDSO far call would add a significant overhead to such minimalistic operations. The ARM_NR_set_tls syscall also changed number. This is done for two reasons: 1) this patch changes the way the TLS value was previously meant to be retrieved, therefore we ensure whatever library using the old way gets fixed (they only exist in private tree at the moment since the NPTL work is still progressing). 2) the previous number was allocated in a range causing an undefined instruction trap on kernels not supporting that syscall and it was determined that allocating it in a range returning -ENOSYS would be much nicer for libraries trying to determine if the feature is present or not. Signed-off-by: Nicolas Pitre Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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1da177e4 |
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16-Apr-2005 |
Linus Torvalds <torvalds@ppc970.osdl.org> |
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
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