#
d1ff2559 |
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04-Jun-2022 |
Miaoqian Lin <linmq006@gmail.com> |
cpufreq: zynq: Fix refcount leak in zynq_get_revision of_find_compatible_node() returns a node pointer with refcount incremented, we should use of_node_put() on it when done. Add missing of_node_put() to avoid refcount leak. Fixes: 00f7dc636366 ("ARM: zynq: Add support for SOC_BUS") Signed-off-by: Miaoqian Lin <linmq006@gmail.com> Link: https://lore.kernel.org/r/20220605082807.21526-1-linmq006@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
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#
65fddcfc |
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08-Jun-2020 |
Mike Rapoport <rppt@kernel.org> |
mm: reorder includes after introduction of linux/pgtable.h The replacement of <asm/pgrable.h> with <linux/pgtable.h> made the include of the latter in the middle of asm includes. Fix this up with the aid of the below script and manual adjustments here and there. import sys import re if len(sys.argv) is not 3: print "USAGE: %s <file> <header>" % (sys.argv[0]) sys.exit(1) hdr_to_move="#include <linux/%s>" % sys.argv[2] moved = False in_hdrs = False with open(sys.argv[1], "r") as f: lines = f.readlines() for _line in lines: line = _line.rstrip(' ') if line == hdr_to_move: continue if line.startswith("#include <linux/"): in_hdrs = True elif not moved and in_hdrs: moved = True print hdr_to_move print line Signed-off-by: Mike Rapoport <rppt@linux.ibm.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Borislav Petkov <bp@alien8.de> Cc: Brian Cain <bcain@codeaurora.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Chris Zankel <chris@zankel.net> Cc: "David S. Miller" <davem@davemloft.net> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Greentime Hu <green.hu@gmail.com> Cc: Greg Ungerer <gerg@linux-m68k.org> Cc: Guan Xuetao <gxt@pku.edu.cn> Cc: Guo Ren <guoren@kernel.org> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: Helge Deller <deller@gmx.de> Cc: Ingo Molnar <mingo@redhat.com> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Mark Salter <msalter@redhat.com> Cc: Matthew Wilcox <willy@infradead.org> Cc: Matt Turner <mattst88@gmail.com> Cc: Max Filippov <jcmvbkbc@gmail.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Michal Simek <monstr@monstr.eu> Cc: Nick Hu <nickhu@andestech.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: Richard Weinberger <richard@nod.at> Cc: Rich Felker <dalias@libc.org> Cc: Russell King <linux@armlinux.org.uk> Cc: Stafford Horne <shorne@gmail.com> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Tony Luck <tony.luck@intel.com> Cc: Vincent Chen <deanbo422@gmail.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Will Deacon <will@kernel.org> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Link: http://lkml.kernel.org/r/20200514170327.31389-4-rppt@kernel.org Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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#
ca5999fd |
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08-Jun-2020 |
Mike Rapoport <rppt@kernel.org> |
mm: introduce include/linux/pgtable.h The include/linux/pgtable.h is going to be the home of generic page table manipulation functions. Start with moving asm-generic/pgtable.h to include/linux/pgtable.h and make the latter include asm/pgtable.h. Signed-off-by: Mike Rapoport <rppt@linux.ibm.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Borislav Petkov <bp@alien8.de> Cc: Brian Cain <bcain@codeaurora.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Chris Zankel <chris@zankel.net> Cc: "David S. Miller" <davem@davemloft.net> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Greentime Hu <green.hu@gmail.com> Cc: Greg Ungerer <gerg@linux-m68k.org> Cc: Guan Xuetao <gxt@pku.edu.cn> Cc: Guo Ren <guoren@kernel.org> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: Helge Deller <deller@gmx.de> Cc: Ingo Molnar <mingo@redhat.com> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Mark Salter <msalter@redhat.com> Cc: Matthew Wilcox <willy@infradead.org> Cc: Matt Turner <mattst88@gmail.com> Cc: Max Filippov <jcmvbkbc@gmail.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Michal Simek <monstr@monstr.eu> Cc: Nick Hu <nickhu@andestech.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: Richard Weinberger <richard@nod.at> Cc: Rich Felker <dalias@libc.org> Cc: Russell King <linux@armlinux.org.uk> Cc: Stafford Horne <shorne@gmail.com> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Tony Luck <tony.luck@intel.com> Cc: Vincent Chen <deanbo422@gmail.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Will Deacon <will@kernel.org> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Link: http://lkml.kernel.org/r/20200514170327.31389-3-rppt@kernel.org Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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#
1a1a9faf |
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12-Feb-2020 |
Geert Uytterhoeven <geert+renesas@glider.be> |
ARM: zynq: Replace <linux/clk-provider.h> by <linux/of_clk.h> The Zynq platform code is not a clock provider, and just needs to call of_clk_init(). Hence it can include <linux/of_clk.h> instead of <linux/clk-provider.h>. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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#
9c92ab61 |
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29-May-2019 |
Thomas Gleixner <tglx@linutronix.de> |
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282 Based on 1 normalized pattern(s): this software is licensed under the terms of the gnu general public license version 2 as published by the free software foundation and may be copied distributed and modified under those terms this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 285 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141900.642774971@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
62e59c4e |
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18-Apr-2019 |
Stephen Boyd <sboyd@kernel.org> |
clk: Remove io.h from clk-provider.h Now that we've gotten rid of clk_readl() we can remove io.h from the clk-provider header and push out the io.h include to any code that isn't already including the io.h header but using things like readl/writel, etc. Found with this grep: git grep -l clk-provider.h | grep '.c$' | xargs git grep -L 'linux/io.h' | \ xargs git grep -l \ -e '\<__iowrite32_copy\>' --or \ -e '\<__ioread32_copy\>' --or \ -e '\<__iowrite64_copy\>' --or \ -e '\<ioremap_page_range\>' --or \ -e '\<ioremap_huge_init\>' --or \ -e '\<arch_ioremap_pud_supported\>' --or \ -e '\<arch_ioremap_pmd_supported\>' --or \ -e '\<devm_ioport_map\>' --or \ -e '\<devm_ioport_unmap\>' --or \ -e '\<IOMEM_ERR_PTR\>' --or \ -e '\<devm_ioremap\>' --or \ -e '\<devm_ioremap_nocache\>' --or \ -e '\<devm_ioremap_wc\>' --or \ -e '\<devm_iounmap\>' --or \ -e '\<devm_ioremap_release\>' --or \ -e '\<devm_memremap\>' --or \ -e '\<devm_memunmap\>' --or \ -e '\<__devm_memremap_pages\>' --or \ -e '\<pci_remap_cfgspace\>' --or \ -e '\<arch_has_dev_port\>' --or \ -e '\<arch_phys_wc_add\>' --or \ -e '\<arch_phys_wc_del\>' --or \ -e '\<memremap\>' --or \ -e '\<memunmap\>' --or \ -e '\<arch_io_reserve_memtype_wc\>' --or \ -e '\<arch_io_free_memtype_wc\>' --or \ -e '\<__io_aw\>' --or \ -e '\<__io_pbw\>' --or \ -e '\<__io_paw\>' --or \ -e '\<__io_pbr\>' --or \ -e '\<__io_par\>' --or \ -e '\<__raw_readb\>' --or \ -e '\<__raw_readw\>' --or \ -e '\<__raw_readl\>' --or \ -e '\<__raw_readq\>' --or \ -e '\<__raw_writeb\>' --or \ -e '\<__raw_writew\>' --or \ -e '\<__raw_writel\>' --or \ -e '\<__raw_writeq\>' --or \ -e '\<readb\>' --or \ -e '\<readw\>' --or \ -e '\<readl\>' --or \ -e '\<readq\>' --or \ -e '\<writeb\>' --or \ -e '\<writew\>' --or \ -e '\<writel\>' --or \ -e '\<writeq\>' --or \ -e '\<readb_relaxed\>' --or \ -e '\<readw_relaxed\>' --or \ -e '\<readl_relaxed\>' --or \ -e '\<readq_relaxed\>' --or \ -e '\<writeb_relaxed\>' --or \ -e '\<writew_relaxed\>' --or \ -e '\<writel_relaxed\>' --or \ -e '\<writeq_relaxed\>' --or \ -e '\<readsb\>' --or \ -e '\<readsw\>' --or \ -e '\<readsl\>' --or \ -e '\<readsq\>' --or \ -e '\<writesb\>' --or \ -e '\<writesw\>' --or \ -e '\<writesl\>' --or \ -e '\<writesq\>' --or \ -e '\<inb\>' --or \ -e '\<inw\>' --or \ -e '\<inl\>' --or \ -e '\<outb\>' --or \ -e '\<outw\>' --or \ -e '\<outl\>' --or \ -e '\<inb_p\>' --or \ -e '\<inw_p\>' --or \ -e '\<inl_p\>' --or \ -e '\<outb_p\>' --or \ -e '\<outw_p\>' --or \ -e '\<outl_p\>' --or \ -e '\<insb\>' --or \ -e '\<insw\>' --or \ -e '\<insl\>' --or \ -e '\<outsb\>' --or \ -e '\<outsw\>' --or \ -e '\<outsl\>' --or \ -e '\<insb_p\>' --or \ -e '\<insw_p\>' --or \ -e '\<insl_p\>' --or \ -e '\<outsb_p\>' --or \ -e '\<outsw_p\>' --or \ -e '\<outsl_p\>' --or \ -e '\<ioread8\>' --or \ -e '\<ioread16\>' --or \ -e '\<ioread32\>' --or \ -e '\<ioread64\>' --or \ -e '\<iowrite8\>' --or \ -e '\<iowrite16\>' --or \ -e '\<iowrite32\>' --or \ -e '\<iowrite64\>' --or \ -e '\<ioread16be\>' --or \ -e '\<ioread32be\>' --or \ -e '\<ioread64be\>' --or \ -e '\<iowrite16be\>' --or \ -e '\<iowrite32be\>' --or \ -e '\<iowrite64be\>' --or \ -e '\<ioread8_rep\>' --or \ -e '\<ioread16_rep\>' --or \ -e '\<ioread32_rep\>' --or \ -e '\<ioread64_rep\>' --or \ -e '\<iowrite8_rep\>' --or \ -e '\<iowrite16_rep\>' --or \ -e '\<iowrite32_rep\>' --or \ -e '\<iowrite64_rep\>' --or \ -e '\<__io_virt\>' --or \ -e '\<pci_iounmap\>' --or \ -e '\<virt_to_phys\>' --or \ -e '\<phys_to_virt\>' --or \ -e '\<ioremap_uc\>' --or \ -e '\<ioremap\>' --or \ -e '\<__ioremap\>' --or \ -e '\<iounmap\>' --or \ -e '\<ioremap\>' --or \ -e '\<ioremap_nocache\>' --or \ -e '\<ioremap_uc\>' --or \ -e '\<ioremap_wc\>' --or \ -e '\<ioremap_wc\>' --or \ -e '\<ioremap_wt\>' --or \ -e '\<ioport_map\>' --or \ -e '\<ioport_unmap\>' --or \ -e '\<ioport_map\>' --or \ -e '\<ioport_unmap\>' --or \ -e '\<xlate_dev_kmem_ptr\>' --or \ -e '\<xlate_dev_mem_ptr\>' --or \ -e '\<unxlate_dev_mem_ptr\>' --or \ -e '\<virt_to_bus\>' --or \ -e '\<bus_to_virt\>' --or \ -e '\<memset_io\>' --or \ -e '\<memcpy_fromio\>' --or \ -e '\<memcpy_toio\>' I also reordered a couple includes when they weren't alphabetical and removed clk.h from kona, replacing it with clk-provider.h because that driver doesn't use clk consumer APIs. Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Tero Kristo <t-kristo@ti.com> Acked-by: Sekhar Nori <nsekhar@ti.com> Cc: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Mark Brown <broonie@kernel.org> Cc: Chris Zankel <chris@zankel.net> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Acked-by: John Crispin <john@phrozen.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
ba5d08c0 |
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26-May-2017 |
Daniel Lezcano <daniel.lezcano@linaro.org> |
clocksource/drivers: Rename clocksource_probe to timer_probe The function name is now renamed to 'timer_probe' for consistency with the CLOCKSOURCE_OF_DECLARE => TIMER_OF_DECLARE change. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
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#
7a3cc2a7 |
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31-Oct-2016 |
Kyle Roeschley <kyle.roeschley@ni.com> |
ARM: zynq: Reserve correct amount of non-DMA RAM On Zynq, we haven't been reserving the correct amount of DMA-incapable RAM to keep DMA away from it (per the Zynq TRM Section 4.1, it should be the first 512k). In older kernels, this was masked by the memblock_reserve call in arm_memblock_init(). Now, reserve the correct amount excplicitly rather than relying on swapper_pg_dir, which is an address and not a size anyway. Fixes: 46f5b96 ("ARM: zynq: Reserve not DMAable space in front of the kernel") Signed-off-by: Kyle Roeschley <kyle.roeschley@ni.com> Tested-by: Nathan Rossi <nathan@nathanrossi.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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#
435ebcbc |
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01-Jun-2016 |
Kefeng Wang <wangkefeng.wang@huawei.com> |
arm: use of_platform_default_populate() to populate Use helper of_platform_default_populate() in linux/of_platform when possible, instead of calling of_platform_populate() with the default match table. Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Krzysztof Halasa <khalasa@piap.pl> Cc: Sekhar Nori <nsekhar@ti.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Russell King <linux@arm.linux.org.uk> Cc: Roland Stigge <stigge@antcom.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Ray Jui <rjui@broadcom.com> Cc: Viresh Kumar <vireshk@kernel.org> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Rob Herring <robh@kernel.org> Cc: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by: Rob Herring <robh@kernel.org>
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#
5e4249c6 |
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22-Apr-2016 |
Viresh Kumar <viresh.kumar@linaro.org> |
cpufreq: zynq: Use generic platdev driver The cpufreq-dt-platdev driver supports creation of cpufreq-dt platform device now, reuse that and remove similar code from platform code. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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#
9388187f |
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02-Feb-2016 |
Josh Cartwright <joshc@ni.com> |
ARM: zynq: initialize slcr mapping earlier In preparation for performing additional configuration prior to bringing up L2, move the slcr initialization earlier in the boot process. Signed-off-by: Josh Cartwright <joshc@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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#
3722ed23 |
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28-Sep-2015 |
Marc Zyngier <maz@kernel.org> |
clocksource: cosmetic: Drop OF 'dependency' from symbols Seeing the 'of' characters in a symbol that is being called from ACPI seems to freak out people. So let's do a bit of pointless renaming so that these folks do feel at home. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: Hanjun Guo <hanjun.guo@linaro.org> Acked-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Hanjun Guo <hanjun.guo@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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#
0d3f2c92 |
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15-Jul-2015 |
Sudeep Holla <sudeep.holla@arm.com> |
irqchip/gic: Remove redundant gic_set_irqchip_flags Now that the GIC chip implementation enables IRQCHIP_SKIP_SET_WAKE and IRQCHIP_MASK_ON_SUSPEND by default, the platforms requiring them need not override the irqchip flags as before. This patch removes all the users of gic_set_irqchip_flags and the function itself. Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Simon Horman <horms@verge.net.au> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Magnus Damm <magnus.damm@gmail.com> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: linux-arm-kernel@lists.infradead.org Link: http://lkml.kernel.org/r/1436971109-20189-2-git-send-email-sudeep.holla@arm.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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#
6632d4fd |
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12-May-2015 |
Thomas Betker <thomas.betker@rohde-schwarz.com> |
ARM: zynq: Set bit 22 in PL310 AuxCtrl register (6395/1) This patch is based on the commit 1a8e41cd672f ("ARM: 6395/1: VExpress: Set bit 22 in the PL310 (cache controller) AuxCtlr register") Clearing bit 22 in the PL310 Auxiliary Control register (shared attribute override enable) has the side effect of transforming Normal Shared Non-cacheable reads into Cacheable no-allocate reads. Coherent DMA buffers in Linux always have a cacheable alias via the kernel linear mapping and the processor can speculatively load cache lines into the PL310 controller. With bit 22 cleared, Non-cacheable reads would unexpectedly hit such cache lines leading to buffer corruption. For Zynq, this fix avoids memory inconsistencies between Gigabit Ethernet controller (GEM) and CPU when DMA_CMA is disabled. Suggested-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com> Signed-off-by: Thomas Betker <thomas.betker@rohde-schwarz.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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#
64e68617 |
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19-Mar-2015 |
Josh Cartwright <joshc@ni.com> |
ARM: zynq: Use restart_handler mechanism for slcr reset By making use of the restart_handler chain mechanism, the SLCR-based reset mechanism can be prioritized amongst other mechanisms available on a particular board. Choose a default high-ish priority of 192 for this restart mechanism. Signed-off-by: Josh Cartwright <joshc@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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#
008e4d67 |
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11-Mar-2015 |
Marc Zyngier <maz@kernel.org> |
ARM: zynq: switch from gic_arch_extn to gic_set_irqchip_flags Instead of directly touching gic_arch_extn, which is about to be removed, use gic_set_irqchip_flags instead. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1426088737-15817-5-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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#
3329659d |
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11-Dec-2014 |
Michal Simek <michal.simek@xilinx.com> |
ARM: zynq: Simplify SLCR initialization Based on "mfd: syscon: Decouple syscon interface from platform devices" (sha1: bdb0066df96e74a4002125467ebe459feff1ebef) SLCR driver can use syscon/regmap drivers directly. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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#
bbcf0719 |
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09-Sep-2014 |
Viresh Kumar <viresh.kumar@linaro.org> |
cpufreq: cpu0: rename driver and internals to 'cpufreq_dt' The naming convention of this driver was always under the scanner, people complained that it should have a more generic name than cpu0, as it manages all CPUs that are sharing clock lines. Also, in future it will be modified to support any number of clusters with separate clock/voltage lines. Lets rename it to 'cpufreq_dt' from 'cpufreq_cpu0'. Tested-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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#
8097171e |
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29-Aug-2014 |
Michal Simek <michal.simek@xilinx.com> |
ARM: zynq: Remove useless L2C AUX setting AUX setting has no effect that's why remove it. Warning log: L2C: platform provided aux values match the hardware, so have no effect. Please remove them. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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#
0beb2bd3 |
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02-Sep-2014 |
Soren Brinkmann <soren.brinkmann@xilinx.com> |
ARM: zynq: PM: Enable DDR clock stop The DDR controller can detect idle periods and leverage low power features clock stop. When new requests occur, the DDRC resumes normal operation. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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#
ae88b85e |
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02-Sep-2014 |
Soren Brinkmann <soren.brinkmann@xilinx.com> |
ARM: zynq: PM: Enable A9 internal clock gating feature Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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#
dcf9c7f9 |
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28-Apr-2014 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: l2c: zynq: convert to generic l2c OF initialisation Remove the explicit call to l2x0_of_init(), converting to the generic infrastructure instead. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
2c4133c5 |
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18-Mar-2014 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: l2c: zynq: remove cache size override The cache size should already be present in the L2 cache auxiliary control register: it is part of the integration process to configure the hardware IP. Most platforms get this right, yet still many cargo-cult program, and assume that they always need specifying to the L2 cache code. Remove them so we can find out which really need this. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
00f7dc63 |
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31-Jul-2013 |
Michal Simek <michal.simek@xilinx.com> |
ARM: zynq: Add support for SOC_BUS Provide information through SOC_BUS to user space. Silicon revision is provided through devcfg device. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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#
4a32c74e |
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05-Feb-2014 |
Michal Simek <michal.simek@xilinx.com> |
ARM: zynq: Move of_clk_init from clock driver Move of_clk_init() from clock driver to enable options not to use zynq clock driver. Use for example fixed clock setting. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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#
cd325295 |
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19-Feb-2014 |
Soren Brinkmann <soren.brinkmann@xilinx.com> |
arm: zynq: Add support for cpufreq The generic cpufreq-cpu0 driver can scale the CPU frequency on Zynq SOCs. Add the required platform device to the BSP and appropriate OPPs to the dts. Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Russell King <linux@arm.linux.org.uk> Cc: devicetree@vger.kernel.org Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Michal Simek <michal.simek@xilinx.com>
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#
46f5b960 |
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30-Jan-2014 |
Michal Simek <michal.simek@xilinx.com> |
ARM: zynq: Reserve not DMAable space in front of the kernel Reserve space from 0x0 - __pa(swapper_pg_dir), if kernel is loaded from 0, which is not DMAable. It is causing problem with MMC driver and others which want to add dma buffers to this space. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Kevin Hilman <khilman@linaro.org>
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#
b0504e39 |
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18-Nov-2013 |
Michal Simek <michal.simek@xilinx.com> |
ARM: zynq: Map I/O memory on clkc init The clkc has its registers in the range of the slcr. Instead of passing around the slcr base address pointer, let the clkc get the address from the DT. This prepares the slcr to be a real driver with multiple memory ranges (slcr, clocks, pinctrl,...) Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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#
016f4dca |
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26-Nov-2013 |
Michal Simek <michal.simek@xilinx.com> |
ARM: zynq: Split slcr in two parts Split the slcr into an early part for unlocking and cpu starting and a later syscon driver. Also add "syscon" compatible property for slcr. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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#
6f69c7f2 |
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25-Jun-2013 |
Steffen Trumtrar <s.trumtrar@pengutronix.de> |
ARM: zynq: Move clock_init from slcr to common Preparation step for next changes. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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#
9f4f5d26 |
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31-Oct-2013 |
Soren Brinkmann <soren.brinkmann@xilinx.com> |
arm: zynq: Set proper GIC flags Zynq is able to wake up on any IRQ, so flag it with IRQCHIP_SKIP_SET_WAKE, and we want to mask off the IRQs when going to suspend to avoid transient effects so also flag this with IRQCHIP_MASK_ON_SUSPEND. This is essentially, making the same changes as commit 'ARM: ux500: set proper GIC flags' (sha1: 7e1f97ea8ffa66679252520dbbbd6ec413ecae68) for Zynq. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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#
f4d5d7b7 |
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31-Oct-2013 |
Soren Brinkmann <soren.brinkmann@xilinx.com> |
arm: zynq: Use of_platform_populate instead of bus_probe All new boards should be using this function instead of of_platform_bus_probe. Two side effects: 1. Possible to probe node which are not in the bus 2. Remove bus_id table from platform code Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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#
3e8ceca6 |
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21-Sep-2013 |
Daniel Lezcano <daniel.lezcano@linaro.org> |
ARM: zynq: cpuidle: convert to platform driver As the ux500 and the kirkwood driver, make the zynq driver a platform driver Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
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#
fe08bf9f |
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27-Jun-2013 |
Vincent Stehlé <vincent.stehle@freescale.com> |
ARM: zynq: fix compilation warning Fix the following compilation warning: arch/arm/mach-zynq/common.c:110:2: warning: initialization from incompatible pointer type [enabled by default] arch/arm/mach-zynq/common.c:110:2: warning: (near initialization for ‘__mach_desc_XILINX_EP107.restart’) [enabled by default] Signed-off-by: Vincent Stehlé <vincent.stehle@freescale.com> Cc: Robin Holt <holt@sgi.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: trivial@kernel.org Signed-off-by: Olof Johansson <olof@lixom.net>
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#
514a5908 |
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13-Jun-2013 |
Arnd Bergmann <arnd@arndb.de> |
ARM: zynq: use DT_MACHINE_START The zynq platform code only supports DT based booting, so we should use DT_MACHINE_START rather than MACHINE_START. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Michal Simek <michal.simek@xilinx.com>
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#
7fa5ac3f |
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13-Jun-2013 |
Soren Brinkmann <soren.brinkmann@xilinx.com> |
arm: zynq: Remove board specific compatibility string It is not necessary to have board specific compatibility strings in the platform code. The board dts files can use the more generic 'xlnx,zynq-7000' string. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Reviewed-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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#
7ac161c4 |
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14-May-2013 |
Maxime Ripard <mripard@kernel.org> |
ARM: zynq: Remove init_irq declaration in machine description Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is specified") removed the need to explictly setup the init_irq field in the machine description when using only irqchip_init. Remove that declaration for zynq as well. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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#
aa7eb2bb |
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20-Mar-2013 |
Michal Simek <michal.simek@xilinx.com> |
arm: zynq: Add smp support Zynq is dual core Cortex A9 which starts always at zero. Using simple trampoline ensure long jump to secondary_startup code. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
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#
889faa88 |
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27-Mar-2013 |
Michal Simek <michal.simek@xilinx.com> |
arm: zynq: Get rid of xilinx function prefix Xilinx is vendor name not SoC name. Use zynq instead. Also remove one checkpatch warning: WARNING: static const char * array should probably be static const char * const +static const char *xilinx_dt_match[] = { Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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#
96790f0a |
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20-Mar-2013 |
Michal Simek <michal.simek@xilinx.com> |
arm: zynq: Add support for system reset Do system reset via slcr registers. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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#
64b889b3 |
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26-Mar-2013 |
Michal Simek <michal.simek@xilinx.com> |
arm: zynq: Move slcr initialization to separate file Create separate slcr driver instead of polluting common code. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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#
732078c3 |
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20-Mar-2013 |
Michal Simek <michal.simek@xilinx.com> |
arm: zynq: Load scu baseaddress at run time Use Cortex a9 cp15 to read scu baseaddress. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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#
c5263bb8 |
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20-Mar-2013 |
Michal Simek <michal.simek@xilinx.com> |
arm: zynq: Move timer to clocksource interface Use clocksource timer initialization. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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#
e932900a |
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20-Mar-2013 |
Michal Simek <michal.simek@xilinx.com> |
arm: zynq: Use standard timer binding Use cdns,ttc because this driver is Cadence Rev06 Triple Timer Counter and everybody can use it without xilinx specific function name or probing. Also use standard dt description for timer and also prepare for moving to clocksource initialization. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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#
00f4c14d |
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28-Jan-2013 |
Michal Simek <michal.simek@xilinx.com> |
arm: zynq: Add missing irqchip.h to common.c The patch: "ARM: use common irqchip_init for GIC init" (sha1: 0529e315bbda5d502c93df2cfafba9bb337fbdf4) should also add linux/irqchip.h header. Error message: arch/arm/mach-zynq/common.c:99:14: error: 'irqchip_init' undeclared here (not in a function) Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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#
f184c5ca |
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19-Dec-2012 |
Soren Brinkmann <soren.brinkmann@xilinx.com> |
arm: zynq: timer: Replace PSS through PS The acronym PSS is deprecated by Xilinx. The correct term, which is also used in Xilinx documentation is PS (processing system). This is just a search and replace: - s/PSS/PS/g - s/pss/ps/g Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Tested-by: Josh Cartwright <josh.cartwright@ni.com>
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#
c0675617 |
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28-Jan-2013 |
Michal Simek <michal.simek@xilinx.com> |
arm: zynq: Add missing irqchip.h to common.c The patch: "ARM: use common irqchip_init for GIC init" (sha1: 0529e315bbda5d502c93df2cfafba9bb337fbdf4) should also add linux/irqchip.h header. Error message: arch/arm/mach-zynq/common.c:99:14: error: 'irqchip_init' undeclared here (not in a function) Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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#
0529e315 |
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05-Nov-2012 |
Rob Herring <rob.herring@calxeda.com> |
ARM: use common irqchip_init for GIC init Convert all GIC DT initialization over to use common irqchip_init function. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Kukjin Kim <kgene.kim@samsung.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: David Brown <davidb@codeaurora.org> Cc: Daniel Walker <dwalker@fifo99.com> Cc: Bryan Huntsman <bryanh@codeaurora.org> Cc: Tony Lindgren <tony@atomide.com> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Magnus Damm <magnus.damm@gmail.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Viresh Kumar <viresh.linux@gmail.com> Cc: Shiraz Hashim <shiraz.hashim@st.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Cc: Linus Walleij <linus.walleij@linaro.org>
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#
1d5cc604 |
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20-Nov-2012 |
Rob Herring <rob.herring@calxeda.com> |
ARM: remove mach .handle_irq for GIC users Now that the GIC initialization sets up the handle_arch_irq pointer, we can remove it for all machines and make it static. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Anton Vorontsov <avorontsov@mvista.com> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: David Brown <davidb@codeaurora.org> Cc: Daniel Walker <dwalker@fifo99.com> Cc: Bryan Huntsman <bryanh@codeaurora.org> Acked-by: Tony Lindgren <tony@atomide.com> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Magnus Damm <magnus.damm@gmail.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Shiraz Hashim <shiraz.hashim@st.com> Acked-by: Stephen Warren <swarren@nvidia.com> Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Cc: Linus Walleij <linus.walleij@linaro.org> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Arnd Bergmann <arnd@arndb.de>
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#
6bb27d73 |
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08-Nov-2012 |
Stephen Warren <swarren@nvidia.com> |
ARM: delete struct sys_timer Now that the only field in struct sys_timer is .init, delete the struct, and replace the machine descriptor .timer field with the initialization function itself. This will enable moving timer drivers into drivers/clocksource without having to place a public prototype of each struct sys_timer object into include/linux; the intent is to create a single of_clocksource_init() function that determines which timer driver to initialize by scanning the device dtree, much like the proposed irqchip_init() at: http://www.spinics.net/lists/arm-kernel/msg203686.html Includes mach-omap2 fixes from Igor Grinberg. Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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#
9a45eb69 |
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19-Nov-2012 |
Josh Cartwright <josh.cartwright@ni.com> |
ARM: zynq: add support for ARCH_MULTIPLATFORM The majority of changes are necessary to remove dependencies on header files within arch/arm/mach-zynq/include/mach: uncompress.h - Deleted. It is unused for ARCH_MULTIPLATFORM builds. uart.h: - Move uart definitions out of uart.h into debug/zynq.S, which is now the only user zynq_soc.h: - Move SCU address definitions into common.c. - Other #defines, such as PERIPHERAL_CLOCK_RATE, TTC0_BASE, etc, are unused and can be dropped Signed-off-by: Josh Cartwright <josh.cartwright@ni.com> Tested-by: Michal Simek <michal.simek@xilinx.com>
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#
385f02b1 |
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19-Nov-2012 |
Josh Cartwright <josh.cartwright@ni.com> |
ARM: zynq: make use of debug_ll_io_init() Convert low-level debugging routines to make use of debug_ll_io_init(). This is part of the preparation for ARCH_MULTIPLATFORM support for Zynq. Signed-off-by: Josh Cartwright <josh.cartwright@ni.com> Tested-by: Michal Simek <michal.simek@xilinx.com>
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#
667f2988 |
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19-Nov-2012 |
Josh Cartwright <josh.cartwright@ni.com> |
ARM: zynq: remove TTC early mapping Now that the TTC driver has proper support for DT bindings, it is not necessary for the registers to be mapped early. They will be mapped during clock initialization using of_iomap(). Remove the early mapping. In addition, remove the extraneous zynq_soc.h include from the timer driver. Signed-off-by: Josh Cartwright <josh.cartwright@ni.com> Tested-by: Michal Simek <michal.simek@xilinx.com>
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#
0f586fbf |
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07-Nov-2012 |
Josh Cartwright <josh.cartwright@ni.com> |
ARM: zynq: use zynq clk bindings Make the Zynq platform use the newly created zynq clk bindings. Signed-off-by: Josh Cartwright <josh.cartwright@ni.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
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#
e06f1a9e |
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31-Oct-2012 |
Josh Cartwright <josh.cartwright@ni.com> |
ARM: zynq: dts: split up device tree The purpose of the created zynq-7000.dtsi file is to describe the hardware common to all Zynq 7000-based boards. Also, get rid of the zynq-ep107 device tree, since it is not hardware anyone can purchase. Add a zc702 dts file based on the zynq-7000.dtsi. Add it to the dts/Makefile so it is built with the 'dtbs' target. Signed-off-by: Josh Cartwright <josh.cartwright@ni.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
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#
aaf5e0be |
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05-Nov-2012 |
Nick Bowler <nbowler@elliptictech.com> |
ARM: zynq: Allow UART1 to be used as DEBUG_LL console. The main UART on the Xilinx ZC702 board is UART1, located at address e0001000. Add a Kconfig option to select this device as the low-level debugging port. This allows the really early boot printouts to reach the USB serial adaptor on this board. For consistency's sake, add a choice entry for UART0 even though it is the the default if UART1 is not selected. Signed-off-by: Nick Bowler <nbowler@elliptictech.com> Tested-by: Josh Cartwright <josh.cartwright@ni.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
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#
03e07595 |
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31-Oct-2012 |
Josh Cartwright <josh.cartwright@ni.com> |
ARM: zynq: move arm-specific sys_timer out of ttc Move the sys_timer definition out of ttc driver and make it part of the common zynq code. This is preparation for renaming and COMMON_CLK support. Signed-off-by: Josh Cartwright <josh.cartwright@ni.com> Tested-by: Michal Simek <michal.simek@xilinx.com>
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#
f5800776 |
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21-Oct-2012 |
Josh Cartwright <josh.cartwright@ni.com> |
zynq: move static peripheral mappings Shifting them up into the vmalloc region prevents the following warning, when booting a zynq qemu target with more than 512mb of RAM: BUG: mapping for 0xe0000000 at 0xe0000000 out of vmalloc space In addition, it allows for reuse of these mappings when the proper drivers issue requests via ioremap(). There are currently unknown issues with the early uart mapping. For now, the uart will be mapped to a known working address. Signed-off-by: Josh Cartwright <josh.cartwright@ni.com> Cc: John Linn <john.linn@xilinx.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Tested-by: Michal Simek <michal.simek@xilinx.com>
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#
f7977939 |
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24-Oct-2012 |
Josh Cartwright <josh.cartwright@ni.com> |
zynq: remove use of CLKDEV_LOOKUP The Zynq support in mainline does not (yet) make use of any of the generic clk or clk lookup functionality. Remove what is upstream for now, until the out-of-tree implementation is in suitable form for merging. An important side effect of this patch is that it allows the building of a Zynq kernel without running into unresolved symbol problems: drivers/built-in.o: In function `amba_get_enable_pclk': clkdev.c:(.text+0x444): undefined reference to `clk_enable' drivers/built-in.o: In function `amba_remove': clkdev.c:(.text+0x488): undefined reference to `clk_disable' drivers/built-in.o: In function `amba_probe': clkdev.c:(.text+0x540): undefined reference to `clk_disable' drivers/built-in.o: In function `amba_device_add': clkdev.c:(.text+0x77c): undefined reference to `clk_disable' drivers/built-in.o: In function `enable_clock': clkdev.c:(.text+0x29738): undefined reference to `clk_enable' drivers/built-in.o: In function `disable_clock': clkdev.c:(.text+0x29778): undefined reference to `clk_disable' drivers/built-in.o: In function `__pm_clk_remove': clkdev.c:(.text+0x297f8): undefined reference to `clk_disable' drivers/built-in.o: In function `pm_clk_suspend': clkdev.c:(.text+0x29bc8): undefined reference to `clk_disable' drivers/built-in.o: In function `pm_clk_resume': clkdev.c:(.text+0x29c28): undefined reference to `clk_enable' make[2]: *** [vmlinux] Error 1 make[1]: *** [sub-make] Error 2 make: *** [all] Error 2 In addition, eliminate Zynq's "use" of the versatile platform, as it is no longer needed. As Nick Bowler points out: For the record, I think this was introduced by commit 56a34b03ff427 ("ARM: versatile: Make plat-versatile clock optional") which forgot to select PLAT_VERSATILE_CLOCK on Zynq. This is not all that surprising, because the fact that Zynq "uses" PLAT_VERSATILE is secretly hidden in the Makefile. Nevertheless, the only feature from versatile that Zynq needed was the clock support, so this patch should *also* delete the secret use of plat-versatile by removing this line from arch/arm/Makefile: plat-$(CONFIG_ARCH_ZYNQ) += versatile Signed-off-by: Josh Cartwright <josh.cartwright@ni.com> Cc: John Linn <john.linn@xilinx.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Tested-by: Michal Simek <michal.simek@xilinx.com>
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#
0fcfdbca |
|
23-Oct-2012 |
Josh Cartwright <josh.cartwright@ni.com> |
zynq: use pl310 device tree bindings The Zynq has a PL310 L2 cache controller. Convert in-tree uses to using the device tree. Signed-off-by: Josh Cartwright <josh.cartwright@ni.com> Cc: John Linn <john.linn@xilinx.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Tested-by: Michal Simek <michal.simek@xilinx.com>
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#
f447ed2d |
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17-Oct-2012 |
Josh Cartwright <josh.cartwright@ni.com> |
zynq: use GIC device tree bindings The Zynq uses the cortex-a9-gic. This eliminates the need to hardcode register addresses. Signed-off-by: Josh Cartwright <josh.cartwright@ni.com> Cc: John Linn <john.linn@xilinx.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Tested-by: Michal Simek <michal.simek@xilinx.com>
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#
368b8e25 |
|
06-Sep-2011 |
Marc Zyngier <maz@kernel.org> |
ARM: zynq: convert to CONFIG_MULTI_IRQ_HANDLER Convert the zynq platform to be using the gic_handle_irq function as its primary interrupt handler. Acked-by: John Linn <john.linn@xilinx.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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#
3d64b449 |
|
07-Jul-2011 |
Arnd Bergmann <arnd@arndb.de> |
ARM: Xilinx: merge board file into main platform code The zynq platform will never have board files other than the device tree one, so there is no point splitting it from common.c. This makes the code more compact. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: John Linn <john.linn@xilinx.com>
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#
b85a3ef4 |
|
20-Jun-2011 |
John Linn <john.linn@xilinx.com> |
ARM: Xilinx: Adding Xilinx board support The 1st board support is minimal to get a system up and running on the Xilinx platform. This platform reuses the clock implementation from plat-versatile, and it depends entirely on CONFIG_OF support. There is only one board support file which obtains all device information from a device tree dtb file which is passed to the kernel at boot time. Signed-off-by: John Linn <john.linn@xilinx.com>
|