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ca5999fd |
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08-Jun-2020 |
Mike Rapoport <rppt@kernel.org> |
mm: introduce include/linux/pgtable.h The include/linux/pgtable.h is going to be the home of generic page table manipulation functions. Start with moving asm-generic/pgtable.h to include/linux/pgtable.h and make the latter include asm/pgtable.h. Signed-off-by: Mike Rapoport <rppt@linux.ibm.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Borislav Petkov <bp@alien8.de> Cc: Brian Cain <bcain@codeaurora.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Chris Zankel <chris@zankel.net> Cc: "David S. Miller" <davem@davemloft.net> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Greentime Hu <green.hu@gmail.com> Cc: Greg Ungerer <gerg@linux-m68k.org> Cc: Guan Xuetao <gxt@pku.edu.cn> Cc: Guo Ren <guoren@kernel.org> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: Helge Deller <deller@gmx.de> Cc: Ingo Molnar <mingo@redhat.com> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Mark Salter <msalter@redhat.com> Cc: Matthew Wilcox <willy@infradead.org> Cc: Matt Turner <mattst88@gmail.com> Cc: Max Filippov <jcmvbkbc@gmail.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Michal Simek <monstr@monstr.eu> Cc: Nick Hu <nickhu@andestech.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: Richard Weinberger <richard@nod.at> Cc: Rich Felker <dalias@libc.org> Cc: Russell King <linux@armlinux.org.uk> Cc: Stafford Horne <shorne@gmail.com> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Tony Luck <tony.luck@intel.com> Cc: Vincent Chen <deanbo422@gmail.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Will Deacon <will@kernel.org> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Link: http://lkml.kernel.org/r/20200514170327.31389-3-rppt@kernel.org Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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9c92ab61 |
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29-May-2019 |
Thomas Gleixner <tglx@linutronix.de> |
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282 Based on 1 normalized pattern(s): this software is licensed under the terms of the gnu general public license version 2 as published by the free software foundation and may be copied distributed and modified under those terms this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 285 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141900.642774971@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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87dfb311 |
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14-May-2019 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace #include <asm/sizes.h> with #include <linux/sizes.h> Since commit dccd2304cc90 ("ARM: 7430/1: sizes.h: move from asm-generic to <linux/sizes.h>"), <asm/sizes.h> and <asm-generic/sizes.h> are just wrappers of <linux/sizes.h>. This commit replaces all <asm/sizes.h> and <asm-generic/sizes.h> to prepare for the removal. Link: http://lkml.kernel.org/r/1553267665-27228-1-git-send-email-yamada.masahiro@socionext.com Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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a359de1b |
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11-Apr-2019 |
Dmitry Osipenko <digetx@gmail.com> |
Revert "ARM: tegra: Restore memory arbitration on resume from LP1 on Tegra30+" Turned out that the actual bug was in the Memory Controller driver that programmed shadowed registers without latching the new values and then there was a bug on EMEM arbitration configuration calculation that results in a wrong value being latched on resume from suspend. The Memory Controller has been fixed properly now, hence the workaround patch could be reverted safely. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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1c6279b4 |
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24-Nov-2018 |
Dmitry Osipenko <digetx@gmail.com> |
ARM: tegra: Restore memory arbitration on resume from LP1 on Tegra30+ The external memory arbitration configuration is getting reset after memory entering into self-refresh mode, it shall be restored on the exit. Note that MC_EMEM_ARB_CFG register is shadowed and latching happens on the EMC timing update. This fixes 2x GPU performance degradation after resuming from LP1 on Tegra30. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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7e939de1 |
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29-Apr-2015 |
Thierry Reding <treding@nvidia.com> |
soc/tegra: fuse: Unify Tegra20 and Tegra30 drivers Unifying the drivers makes it easier to restrict the legacy probing paths to 32-bit ARM. This in turn will come in handy as support for new 64-bit ARM SoCs is added. Signed-off-by: Thierry Reding <treding@nvidia.com>
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1a703bff |
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11-Mar-2015 |
Marc Zyngier <maz@kernel.org> |
ARM: tegra: remove old LIC support Now that all DTs have been updated, entierely drop support for the non-DT code. This is likely to break platforms that do not update their DT, so print a warning at boot time. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1426088583-15097-7-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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6dee8200 |
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29-Oct-2013 |
Stephen Warren <swarren@nvidia.com> |
ARM: tegra: use section-sized static mappings for LPAE too The static mappings for Tegra's PPSB and APB regions were sized at 1MB in order to allow mapping via sections in order to avoid burning RAM for PTEs. On LPAE, sections are 2MB, so the static mappings need to be larger in order to gain the same benefit. Set IO_{PPSB,APB}_SIZE to SECTION_SIZE so this adjusts automatically. While we're fiddling with iomap.h, compress IO_{IRAM,CPU}_VIRT together to save virtual address space in the vmalloc region; these two regions are mapped using PTEs. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
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f0c4ac13 |
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11-Oct-2013 |
Joseph Lo <josephl@nvidia.com> |
ARM: tegra: add LP1 support code for Tegra124 The LP1 suspend procedure is the same with Tegra30 and Tegra114. Just need to update the difference of the register address, then we can continue to share the code. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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4cf6791a |
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20-Aug-2013 |
Stephen Warren <swarren@nvidia.com> |
ARM: tegra: remove much of iomap.h iomap.h defines the base address of Tegra peripherals. Most of this information comes from device tree now, and hence can be deleted. Entries are kept for various system peripherals that low-level code (such as initial boot, system suspend/resume, debug) still requires. Removing the values removes the temptation for someone to use them. Signed-off-by: Stephen Warren <swarren@nvidia.com>
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fddb770d |
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20-Aug-2013 |
Stephen Warren <swarren@nvidia.com> |
ARM: tegra: move resume vector define to irammap.h irammap.h's purpose is to define the layout/usage of IRAM. As such, TEGRA_IRAM_CODE_AREA should have been added there rather than iomap.h. Move the define, and rename it something more descriptive. Cc: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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d1523b52 |
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09-Aug-2013 |
Thierry Reding <thierry.reding@avionic-design.de> |
PCI: tegra: Move PCIe driver to drivers/pci/host Move the PCIe driver from arch/arm/mach-tegra into the drivers/pci/host directory. The motivation is to collect various host controller drivers in the same location in order to facilitate refactoring. The Tegra PCIe driver has been largely rewritten, both in order to turn it into a proper platform driver and to add MSI (based on code by Krishna Kishore <kthota@nvidia.com>) as well as device tree support. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> [swarren, split DT changes into a separate patch in another branch] Signed-off-by: Stephen Warren <swarren@nvidia.com>
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e9f62449 |
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12-Aug-2013 |
Joseph Lo <josephl@nvidia.com> |
ARM: tegra: add LP1 suspend support for Tegra114 The LP1 suspend mode will power off the CPU, clock gated the PLLs and put SDRAM to self-refresh mode. Any interrupt can wake up device from LP1. The sequence when LP1 suspending: * tunning off L1 data cache and the MMU * storing some EMC registers, DPD (deep power down) status, clk source of mselect and SCLK burst policy * putting SDRAM into self-refresh * switching CPU to CLK_M (12MHz OSC) * tunning off PLLM, PLLP, PLLA, PLLC and PLLX * switching SCLK to CLK_S (32KHz OSC) * shutting off the CPU rail The sequence of LP1 resuming: * re-enabling PLLM, PLLP, PLLA, PLLC and PLLX * restoring the clk source of mselect and SCLK burst policy * setting up CCLK burst policy to PLLX * restoring DPD status and some EMC registers * resuming SDRAM to normal mode * jumping to the "tegra_resume" from PMC_SCRATCH41 Due to the SDRAM will be put into self-refresh mode, the low level procedures of LP1 suspending and resuming should be copied to TEGRA_IRAM_CODE_AREA (TEGRA_IRAM_BASE + SZ_4K) when suspending. Before restoring the CPU context when resuming, the SDRAM needs to be switched back to normal mode. And the PLLs need to be re-enabled, SCLK burst policy be restored. Then jumping to "tegra_resume" that was expected to be stored in PMC_SCRATCH41 to restore CPU context and back to kernel. Based on the work by: Bo Yan <byan@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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5b795d05 |
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12-Aug-2013 |
Joseph Lo <josephl@nvidia.com> |
ARM: tegra: add common resume handling code for LP1 resuming Add support to the Tegra CPU reset vector to detect whether the CPU is resuming from LP1 suspend state. If it is, branch to the LP1-specific resume code. When Tegra enters the LP1 suspend state, the SDRAM controller is placed into a self-refresh state. For this reason, we must place the LP1 resume code into IRAM, so that it is accessible before SDRAM access has been re-enabled. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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16a665f8 |
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17-Dec-2012 |
Venu Byravarasu <vbyravarasu@nvidia.com> |
ARM: tegra: remove USB address related macros from iomap.h USB register base address and sizes defined in iomap.h are not used in any files other than board-dt-tegra20.c. Hence removed those defines from header file and using the absolute values in board files. Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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adc18315 |
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01-Oct-2012 |
Stephen Warren <swarren@nvidia.com> |
ARM: tegra: simplify DEBUG_LL UART selection options Delete CONFIG_TEGRA_DEBUG_UART_AUTO_SCRATCH; it's not useful any more: * No upstream bootloader currently or will ever support this option. * CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA is a much more direct alternative. Merge the fixed and automatic UART selection menus into a single choice for simplicity; now you either pick AUTO_ODMDATA or a single fixed UART, rather than potentially having an AUTO option override whatever fixed option was chosen. Remove TEGRA_DEBUG_UART_NONE; if you don't want a Tegra DEBUG_LL UART, simply don't turn on DEBUG_LL. NONE used to be the default option, so pick AUTO_ODMDATA as the new default. Signed-off-by: Stephen Warren <swarren@nvidia.com>
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2be39c07 |
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04-Oct-2012 |
Stephen Warren <swarren@nvidia.com> |
ARM: tegra: move iomap.h to mach-tegra Nothing outside mach-tegra uses this file, so there's no need for it to be in <mach/>. Since uncompress.h and debug-macro.S remain in include/mach, they need to include "../../iomap.h" becaue of this change. uncompress.h will soon be deleted in later multi-platform/single-zImage patches. debug-macro.S will need to continue to include this header using an explicit relative path, to avoid duplicating the physical->virtual address mapping that iomap.h dictates. Signed-off-by: Stephen Warren <swarren@nvidia.com>
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