#
36bee3f6 |
|
10-Sep-2023 |
Tony Lindgren <tony@atomide.com> |
ARM: omap2+: Downgrade u-boot version warnings to debug statements We should be able to see real issues with dmesg -l err,warn. The u-boot revision warning should be a debug statement rather than a warning. Cc: Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com> Cc: Carl Philipp Klemm <philipp@uvos.xyz> Cc: Merlijn Wajer <merlijn@wizzup.org> Cc: Pavel Machek <pavel@ucw.cz> Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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#
a282e5ef |
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12-Jan-2023 |
Tony Lindgren <tony@atomide.com> |
cpuidle, OMAP4: Push RCU-idle into omap4_enter_lowpower() OMAP4 uses full SoC suspend modes as idle states, as such it needs the whole power-domain and clock-domain code from the idle path. All that code is not suitable to run with RCU disabled, as such push RCU-idle deeper still. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Ingo Molnar <mingo@kernel.org> Tested-by: Tony Lindgren <tony@atomide.com> Tested-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Acked-by: Frederic Weisbecker <frederic@kernel.org> Link: https://lkml.kernel.org/r/Yqcv6crSNKuSWoTu@atomide.com Link: https://lore.kernel.org/r/20230112195541.660272394@infradead.org
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#
caf8c87d |
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16-Oct-2019 |
Tony Lindgren <tony@atomide.com> |
ARM: OMAP2+: Allow core oswr for omap4 Commit f74297dd9354 ("ARM: OMAP2+: Make sure LOGICRETSTATE bits are not cleared") disabled oswr (open switch retention) for per and core domains as various GPIO related issues were noticed if the bootloader had configured the bits for LOGICRETSTATE for per and core domains. With the recent gpio-omap fixes, mostly related to commit e6818d29ea15 ("gpio: gpio-omap: configure edge detection for level IRQs for idle wakeup"), things now behave for enabling core oswr for omap4. Cc: Merlijn Wajer <merlijn@wizzup.org> Cc: Pavel Machek <pavel@ucw.cz> Cc: Sebastian Reichel <sre@kernel.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
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#
623429d5 |
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16-Oct-2019 |
Tony Lindgren <tony@atomide.com> |
ARM: OMAP2+: Allow per oswr for omap4 Commit f74297dd9354 ("ARM: OMAP2+: Make sure LOGICRETSTATE bits are not cleared") disabled oswr (open switch retention) for per and core domains as various GPIO related issues were noticed if the bootloader had configured the bits for LOGICRETSTATE for per and core domains. With the recent gpio-omap fixes, mostly related to commit e6818d29ea15 ("gpio: gpio-omap: configure edge detection for level IRQs for idle wakeup"), things now behave for enabling per oswr for omap4. Cc: Merlijn Wajer <merlijn@wizzup.org> Cc: Pavel Machek <pavel@ucw.cz> Cc: Sebastian Reichel <sre@kernel.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
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#
dfc065aa |
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16-Oct-2019 |
Tony Lindgren <tony@atomide.com> |
ARM: OMAP2+: Drop bogus wkup domain oswr setting The wkup domain is always on and does not have logic off setting. This got accidentally added by commit f74297dd9354 ("ARM: OMAP2+: Make sure LOGICRETSTATE bits are not cleared") but is harmless. Cc: Merlijn Wajer <merlijn@wizzup.org> Cc: Pavel Machek <pavel@ucw.cz> Cc: Sebastian Reichel <sre@kernel.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
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#
d2912cb1 |
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04-Jun-2019 |
Thomas Gleixner <tglx@linutronix.de> |
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500 Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
f74297dd |
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17-May-2018 |
Tony Lindgren <tony@atomide.com> |
ARM: OMAP2+: Make sure LOGICRETSTATE bits are not cleared We may have LOGICRETSTATE cleared by the bootloader or kexec boot. Currently this means we will see lost GPIO interrupts at least for network interfaces such as wlcore and smsc911x if PER hits retention. Let's fix the issue by making sure LOGICRETSTATE is set. Once we have GPIOs working with wakeirqs then we should be able to clear it. Cc: Keerthy <j-keerthy@ti.com> Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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#
7abdb0e2 |
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07-Nov-2016 |
Santosh Shilimkar <santosh.shilimkar@ti.com> |
ARM: OMAP5: Add basic cpuidle MPU CSWR support Add OMAP5 CPUIDLE support. This patch adds MPUSS low power states in cpuidle. C1 - CPU0 WFI + CPU1 WFI + MPU ON C2 - CPU0 RET + CPU1 RET + MPU CSWR Modified from TI kernel tree commit 605967fd2205 ("ARM: DRA7: PM: cpuidle MPU CSWR support") except enable cpuidle for omap5 instead of dra7. According to Nishanth Menon <nm@ti.com>, cpuidle on dra7 is not supported properly in the hardware so we don't want to enable it. However, for omap5 this adds some nice power savings. Note that the TI 3.8 based tree has other cpuidle states that we may be able to enable later on. On omap5-uevm, the power consumption eventually settles down to about 920mW with ehci-omap and ohci-omap3 unloaded compared to about 1.7W without these patches. Note that it seems to take few minutes after booting for the idle power to go down to 920mW from 1.3W, no idea so far what might be causing that. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> [ j-keerthy@ti.com rework on 3.14] Signed-off-by: Keerthy <j-keerthy@ti.com> [nm@ti.com: updates based on profiling] [tony@atomide.com: dropped CPUIDLE_FLAG_TIME_VALID no longer used, changed for omap5 only as requested by Nishanth, updated comments] Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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#
ae428a72 |
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17-Sep-2015 |
Javier Martinez Canillas <javier@osg.samsung.com> |
ARM: OMAP2+: Remove unneeded semicolons Remove the unneded semicolons since they are clearly a typo error. Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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#
b9f5fe64 |
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21-Oct-2014 |
Nishanth Menon <nm@ti.com> |
ARM: OMAP4+: PM: Centralize static dependency mapping table As we add more static dependency mapping for various errata, the logic gets clunkier. Since it is a simple lookup and map logic, centralize the same and provide the mapping as a simple list. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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#
9008d83f |
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21-Oct-2014 |
Nishanth Menon <nm@ti.com> |
ARM: OMAP4: PM: Only do static dependency configuration in omap4_init_static_deps Commit 705814b5ea6f ("ARM: OMAP4+: PM: Consolidate OMAP4 PM code to re-use it for OMAP5") Moved logic generic for OMAP5+ as part of the init routine by introducing omap4_pm_init. However, the patch left the powerdomain initial setup, an unused omap4430 es1.0 check and a spurious log "Power Management for TI OMAP4." in the original code. Remove the duplicate code which is already present in omap4_pm_init from omap4_init_static_deps. As part of this change, also move the u-boot version print out of the static dependency function to the omap4_pm_init function. Fixes: 705814b5ea6f ("ARM: OMAP4+: PM: Consolidate OMAP4 PM code to re-use it for OMAP5") Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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#
6099dd37 |
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27-May-2013 |
Rajendra Nayak <rnayak@ti.com> |
ARM: OMAP5 / DRA7: Enable CPU RET on suspend On OMAP5 / DRA7, prevent a CPU powerdomain OFF and resulting MPU OSWR and instead attempt a CPU RET and side effect, MPU RET in suspend. NOTE: the hardware was originally designed to be capable of achieving deep power states such as OFF and OSWR, however due to various issues and risks, deepest valid state was determined to be CSWR - hence we use the errata framework to handle this case. Signed-off-by: Rajendra Nayak <rnayak@ti.com> [nm@ti.com: updates] Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org>
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#
d2136bce |
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06-Feb-2013 |
Santosh Shilimkar <santosh.shilimkar@ti.com> |
ARM: OMAP5 / DRA7: PM: Set MPUSS-EMIF clock-domain static dependency With EMIF clock-domain put under hardware supervised control, memory corruption and untraceable crashes are observed on OMAP5. Further investigation revealed that there is a weakness in the PRCM on this specific dynamic depedency. The recommendation is to set MPUSS static dependency towards EMIF clock-domain to avoid issues. This recommendation holds good for DRA7 family of devices as well. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> [rnayak@ti.com: DRA7] Signed-off-by: Rajendra Nayak <rnayak@ti.com> [nm@ti.com: conflict resolution, dra7] Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org>
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#
bd7593c6 |
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06-Jun-2014 |
Nishanth Menon <nm@ti.com> |
ARM: OMAP4+: PM: use only valid low power state for suspend We are using power domain state as RET and logic state as OFF. This state is OSWR. This may not always be supported on ALL power domains. In fact, on certain power domains, this might result in a hang on certain platforms. Instead, depend on powerdomain data to provide accurate information about the supported powerdomain states and use the appropriate function to query and use it as part of suspend path. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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#
46ba5526 |
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05-Jun-2014 |
Nishanth Menon <nm@ti.com> |
ARM: OMAP4+: PM: Make logic state programmable Move the logic state as different for each power domain. This allows us to customize the deepest power state we should target over all for each powerdomain in the follow on patches. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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#
2e4b62dc |
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12-May-2014 |
Dave Gerlach <d-gerlach@ti.com> |
ARM: OMAP2+: Remove suspend_set_ops from common pm late init In omap2_common_pm_late_init suspend_set_ops was called to set common suspend handling functions for all omap platforms. This created two problems. First, these suspend ops were being set for all platforms, regardless of whether or not suspend support has been integrated so in the case of AM33XX, suspend to mem was presented as available but failed every time. Second, some platforms will need to define a completely separate set of suspend ops, such as AM33XX, due to differences from previous omap platforms so there is no need to always set the common omap ops. This patch moves the suspend_set_ops call from omap2_common_pm_late_init into a separate function that then gets called in the omap*_pm_init functions for each platform. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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#
de70af49 |
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20-Jan-2014 |
Nishanth Menon <nm@ti.com> |
ARM: OMAP4+: move errata initialization to omap4_pm_init_early Move all OMAP4 PM errata initializations to centralized location in omap4_pm_init_early. This allows for users to utilize the erratas in various submodules as needed. Reported-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
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#
705814b5 |
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12-Apr-2012 |
Santosh Shilimkar <santosh.shilimkar@ti.com> |
ARM: OMAP4+: PM: Consolidate OMAP4 PM code to re-use it for OMAP5 OMAP5 has backward compatible PRCM block and it's programming model is mostly similar to OMAP4. Same is going to be maintained for future OMAP4 based SOCs. Hence consolidate the OMAP4 power management code so that it can be re-used on OMAP5 and later devices. While at it, update the kernel-doc for omap4_pm_init(). Acked-by: Nishanth Menon <nm@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Kevin Hilman <khilman@linaro.org>
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#
62006324 |
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29-Mar-2013 |
Paul Bolle <pebolle@tiscali.nl> |
pm44xx: Fix comment for "CONFIG_CPU_IDLE" Signed-off-by: Paul Bolle <pebolle@tiscali.nl> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
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#
d5336a5a |
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16-Feb-2013 |
Santosh Shilimkar <santosh.shilimkar@ti.com> |
ARM: OMAP4: PM: Now remove L4 per clockdomain static depedency with MPU UART driver slave idle issue has been taken care by driver using hwmod framework. So we can now ger rid off the L4 per clockdomain static dependency with MPU which was used to wrok around UART wakeup and console sluggishnesh issue on OMAP4 SOCs. Acked-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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#
6cf38956 |
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16-Feb-2013 |
Santosh Shilimkar <santosh.shilimkar@ti.com> |
ARM: OMAP4: PM: Remove L4 wakeup depedency with MPU since errata fix exist now With commit bfd6d021 {ARM: OMAP3+: Implement timer workaround for errata i103 and i767}, the sync and gptimer synchronization errata got fixed. Hence the l4_wakeup static dependency with MPU can can be removed now. Static dependency was one of the proposed workaround but from power savings perspective, it isn't an ideal workaround. Acked-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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#
6b85638b |
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11-Feb-2013 |
Santosh Shilimkar <santosh.shilimkar@ti.com> |
ARM: OMAP2+: PM: Remove bogus fiq_[enable/disable] tuple On OMAP platform, FIQ is reserved for secure environment only. If at all the FIQ needs to be disabled, it involves going through security API call. Hence the local_fiq_[enable/disable]() in the OMAP code is bogus. On GP devices too, the fiq is disabled for non-secure software. So just get rid of it. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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#
60480098 |
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04-Feb-2013 |
Rajendra Nayak <rnayak@ti.com> |
ARM: OMAP4: PM: Warn users about usage of older bootloaders OMAP4 CHIP level PM works only with newer bootloaders. The dependency on the bootloader comes from the fact that the kernel is missing reset and initialization code for some devices. While the right thing to do is to add reset and init code in the kernel, for some co-processor IP blocks like DSP and IVA it means downloading firmware into each one of them to execute idle instructions. While a feasible solution is worked upon on how such IP blocks can be better handled in the kernel, in the interim, to avoid any further frustration to users testing PM on OMAP4 and finding it broken, warn them about the bootloader being a possible cause. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Cc: Tero Kristo <t-kristo@ti.com> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: R Sricharan <r.sricharan@ti.com> [paul@pwsan.com: tweaked warning messages and comments slightly] Acked-by: Kevin Hilman <khilman@linaro.org> [paul@pwsan.com: fixed checkpatch warning] Signed-off-by: Paul Walmsley <paul@pwsan.com>
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#
93640735 |
|
14-Nov-2012 |
Kevin Hilman <khilman@ti.com> |
ARM: OMAP4: PM: fix errata handling when CONFIG_PM=n commit c9621844 (ARM: OMAP4: PM: add errata support) introduced errata handling for OMAP4, but was broken when CONFIG_PM=n. When CONFIG_PM=n, pm44xx.c is not compiled, yet that is where pm44xx_errata is defined. However, these errata are needed for the SMP boot/hotplug case also, and are primarily used in omap-smp.c. Move the definition of pm44xx_errata to omap-smp.c so that it's available even in the CONFIG_PM=n case. Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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#
0c7018e2 |
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17-Oct-2012 |
Rajendra Nayak <rnayak@ti.com> |
ARM: OMAP4: suspend: Program all domains to retention Remove the FIXME's in the suspend sequence since we now intend to support system level RET support. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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#
c9621844 |
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17-Oct-2012 |
Tero Kristo <t-kristo@ti.com> |
ARM: OMAP4: PM: add errata support Added similar PM errata flag support as omap3 has. This should be used in similar manner, set the flags during init time, and check the flag values during runtime. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
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#
e4c060db |
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05-Oct-2012 |
Tony Lindgren <tony@atomide.com> |
ARM: OMAP: Split plat/cpu.h into local soc.h for mach-omap1 and mach-omap2 We want to remove plat/cpu.h. To do this, let's first split it to private soc.h to mach-omap1 and mach-omap2. We have to keep plat/cpu.h around until the remaining drivers are fixed, so let's include the local soc.h in plat/cpu.h and for drivers still including plat/cpu.h. Once the drivers are fixed not to include plat/cpu.h, we can remove the file. This is needed for the ARM common zImage support. [tony@atomide.com: updated to not print a warning] Signed-off-by: Tony Lindgren <tony@atomide.com>
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#
7852ec05 |
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26-Jul-2012 |
Paul Walmsley <paul@pwsan.com> |
ARM: OMAP: unwrap strings Find and unwrap wrapped strings in the style: pr_debug("clockdomain: hardware cannot set/clear wake up of " "%s when %s wakes up\n", clkdm1->name, clkdm2->name); Keeping these strings contiguous seems to be the current Linux kernel policy. The offending lines were found with the following command: pcregrep -rnM '"\s*$\s*"' arch/arm/*omap* While here, some messages have been clarified, some pr_warning( ... calls have been converted to pr_warn( ..., and some printk(KERN_* ... have been converted to pr_*. Signed-off-by: Paul Walmsley <paul@pwsan.com>
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#
bbd707ac |
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26-Apr-2012 |
Shawn Guo <shawn.guo@linaro.org> |
ARM: omap2: use machine specific hook for late init Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Tony Lindgren <tony@atomide.com>
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#
9f97da78 |
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28-Mar-2012 |
David Howells <dhowells@redhat.com> |
Disintegrate asm/system.h for ARM Disintegrate asm/system.h for ARM. Signed-off-by: David Howells <dhowells@redhat.com> cc: Russell King <linux@arm.linux.org.uk> cc: linux-arm-kernel@lists.infradead.org
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#
68523f42 |
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12-Mar-2012 |
Santosh Shilimkar <santosh.shilimkar@ti.com> |
ARM: OMAP4: Workaround the OCP synchronisation issue with 32K synctimer. On OMAP4, recently a synchronisation bug is discovered by hardware team, which leads to incorrect timer value read from 32K sync timer IP when the IP is comming out of idle. The issue is due to the synchronization methodology used in the SYNCTIMER IP. The value of the counter register in 32kHz domain is synchronized to the OCP domain register only at count up event, and if the OCP clock is switched off, the OCP register gets out of synch until the first count up event after the clock is switched back -at the next falling edge of the 32kHz clock. Further investigation revealed that it applies to gptimer1 and watchdog timer2 as well which may run on 32KHz. This patch fixes the issue for all the applicable modules. The BUG has not made it yet to the OMAP errata list and it is applicable to OMAP1/2/3/4/5. OMAP1/2/3 it is taken care indirectly by autodeps. By enabling static depedency of wakeup clockdomain with MPU, as soon as MPU is woken up from lowpower state(idle) or whenever MPU is active, PRCM forces the OCP clock to be running and allow the counter value to be updated properly in the OCP clock domain. The bug is going to fixed in future OMAP versions. Reported-Tested-by: dave.long@linaro.org [dave.long@linaro.org: Reported the oprofile time stamp issue with synctimer and helped to test this patch] Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
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#
1416408d |
|
02-Feb-2012 |
Paul Walmsley <paul@pwsan.com> |
ARM: OMAP2+: PM: share some suspend-related functions across OMAP2, 3, 4 The platform_suspend_ops can be shared across OMAP2, 3, and 4, along with all of the functions referenced in that structure. This patch shares them. It also removes the suspend_state file-scoped variable in the OMAP2 and 3 PM code; it does not appear to be actually needed by anything. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Rajendra Nayak <rnayak@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> [khilman@ti.com: minor rework needed due to rebase/merge with conflicting changes] Signed-off-by: Kevin Hilman <khilman@ti.com>
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#
92206fd2 |
|
02-Feb-2012 |
Paul Walmsley <paul@pwsan.com> |
ARM: OMAP2+: PM: share clkdms_setup() across OMAP2, 3, 4 clkdms_setup() is identical across OMAP2, 3, and 4, so share it. Signed-off-by: Paul Walmsley <paul@pwsan.com> Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Rajendra Nayak <rnayak@ti.com> Tested-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
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#
ae940913 |
|
19-Dec-2011 |
Nicolas Pitre <nico@fluxnic.net> |
ARM: substitute arch_idle() Now that all implementations of arch_idle() are equivalent to cpu_do_idle() we can just use the later directly and stop including mach/system.h. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Acked-by: H Hartley Sweeten <hsweeten@visionengravers.com> Acked-and-tested-by: Jamie Iles <jamie@jamieiles.com> Acked-by: Tony Lindgren <tony@atomide.com> Tested-by: Stephen Warren <swarren@nvidia.com>
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#
0bcd24b0 |
|
04-Jan-2012 |
Nicolas Pitre <nico@fluxnic.net> |
ARM: OMAP: convert idle handlers from pm_idle to arm_pm_idle Signed-off-by: Nicolas Pitre <nico@linaro.org> Tested-by: Tony Lindgren <tony@atomide.com>
|
#
98272660 |
|
16-Aug-2011 |
Santosh Shilimkar <santosh.shilimkar@ti.com> |
ARM: OMAP4: PM: Add CPUidle support Add OMAP4 CPUIDLE support. CPU1 is left with defualt idle and the low power state for it is managed via cpu-hotplug. This patch adds MPUSS low power states in cpuidle. C1 - CPU0 ON + CPU1 ON + MPU ON C2 - CPU0 OFF + CPU1 OFF + MPU CSWR C3 - CPU0 OFF + CPU1 OFF + MPU OSWR OMAP4460 onwards, MPUSS power domain doesn't support OFF state any more anymore just like CORE power domain. The deepest state supported is OSWr. Ofcourse when MPUSS and CORE PD transitions to OSWR along with device off mode, even the memory contemts are lost which is as good as the PD off state. On OMAP4 because of hardware constraints, no low power states are targeted when both CPUs are online and in SMP mode. The low power states are attempted only when secondary CPU gets offline to OFF through hotplug infrastructure. Thanks to Nicole Chalhoub <n-chalhoub@ti.com> for doing exhaustive C-state latency profiling. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
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#
3ba2a739 |
|
06-Jun-2011 |
Santosh Shilimkar <santosh.shilimkar@ti.com> |
ARM: OMAP4: PM: Add MPUSS power domain OSWR support This patch adds the MPUSS OSWR (Open Switch Retention) support. The MPUSS OSWR configuration is as below. - CPUx L1 and logic lost, MPUSS logic lost, L2 memory is retained OMAP4460 onwards, MPUSS power domain doesn't support OFF state any more anymore just like CORE power domain. The deepest state supported is OSWR. On OMAP4430 secure devices too, MPUSS off mode can't be used because of a bug which alters Ducati and Tesla states. Hence MPUSS off mode as an independent state isn't supported on OMAP44XX devices. Ofcourse when MPUSS power domain transitions to OSWR along with device off mode, it eventually hits off state since memory contents are lost. Hence the MPUSS off mode independent state is not attempted without device off mode. All the necessary infrastructure code for MPUSS off mode is in place as part of this series. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
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e44f9a77 |
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16-Jun-2010 |
Santosh Shilimkar <santosh.shilimkar@ti.com> |
ARM: OMAP4: suspend: Add MPUSS power domain RETENTION support This patch adds MPUSS(MPU Sub System) power domain CSWR(Close Switch Retention) support to system wide suspend. For MPUSS power domain to hit retention(CSWR or OSWR), both CPU0 and CPU1 power domains need to be in OFF or DORMANT state, since CPU power domain CSWR is not supported by hardware Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
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72826b9f |
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17-Jul-2011 |
Santosh Shilimkar <santosh.shilimkar@ti.com> |
ARM: OMAP4: PM: Use custom omap_do_wfi() for default idle. Default arch_idle() isn't good enough for OMAP4 because of aync bridge errata and necessity of NOPs post WFI to avoid speculative prefetch aborts. Hence Use OMAP4 custom omap_do_wfi() hook for default idle. Later in the series, async bridge errata work-around patch updates the omap_do_wfi() with necessary interconnects barriers. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
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b2b9762f |
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16-Jun-2010 |
Santosh Shilimkar <santosh.shilimkar@ti.com> |
ARM: OMAP4: PM: Add CPUX OFF mode support This patch adds the CPU0 and CPU1 off mode support. CPUX close switch retention (CSWR) is not supported by hardware design. The CPUx OFF mode isn't supported on OMAP4430 ES1.0 CPUx sleep code is common for hotplug, suspend and CPUilde. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
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3c50729b |
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05-Jan-2011 |
Santosh Shilimkar <santosh.shilimkar@ti.com> |
ARM: OMAP4: PM: Initialise all the clockdomains to supported states Initialise hardware supervised mode for all clockdomains if it's supported. Initiate sleep transition for other clockdomains, if they are not being used. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
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361b02f3 |
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11-Mar-2011 |
Santosh Shilimkar <santosh.shilimkar@ti.com> |
ARM: OMAP4: PM: Avoid omap4_pm_init() on OMAP4430 ES1.0 On OMAP4430 ES1.0, Power Management features are not supported. Avoid omap4_pm_init() on ES1.0 silicon so that we can continue to use same kernel binary to boot on all OMAP4 silicons. The ES1.0 boot failure with OMAP4 PM series was because of the clockdomain initialisation code. Hardware supervised clockdomain mode isn't functional for all clockdomains on OMAP4430 ES1.0 silicon so avoid the same. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Reported-by: Kevin Hilman <khilman@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
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12f27826 |
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08-Mar-2011 |
Santosh Shilimkar <santosh.shilimkar@ti.com> |
ARM: OMAP4: PM: Keep static dep between MPUSS-EMIF and MPUSS-L3/L4 and DUCATI-L3 As per OMAP4430 TRM, the dynamic dependency between MPUSS -> EMIF and MPUSS -> L4PER/L3_* and DUCATI -> L3_* clockdomains is enable by default. Refer register CM_MPU_DYNAMICDEP description for details. But these dynamic dependencies doesn't work as expected. The hardware recommendation is to enable static dependencies for above clockdomains. Without this, system locks up or randomly crashes. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Paul Walmsley <paul@pwsan.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
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4e65331c |
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10-Nov-2011 |
Tony Lindgren <tony@atomide.com> |
ARM: 7159/1: OMAP: Introduce local common.h files As suggested by Russell King - ARM Linux <linux@arm.linux.org.uk>, there's no need to keep local prototypes in non-local headers. Add mach-omap1/common.h and mach-omap2/common.h and move the local prototypes there from plat/common.h and mach/omap4-common.h. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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34549009 |
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27-Apr-2011 |
Nishanth Menon <nm@ti.com> |
OMAP4: PM: remove redundant #ifdef CONFIG_PM pm44xx.c is built only when CONFIG_PM is setup, remove redundant CONFIG_PM check. This also fixes: https://bugzilla.kernel.org/show_bug.cgi?id=25022 Reported-by: Martin Etti <ettl.martin@gmx.de> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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72e06d08 |
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21-Dec-2010 |
Paul Walmsley <paul@pwsan.com> |
OMAP2+: powerdomain: move header file from plat-omap to mach-omap2 The OMAP powerdomain code and data is all OMAP2+-specific. This seems unlikely to change any time soon. Move plat-omap/include/plat/powerdomain.h to mach-omap2/powerdomain.h. The primary point of doing this is to remove the temptation for unrelated upper-layer code to access powerdomain code and data directly. As part of this process, remove the references to powerdomain data from the GPIO "driver" and the OMAP PM no-op layer, both in plat-omap. Change the DSPBridge code to point to the new location for the powerdomain headers. The DSPBridge code should not be including the powerdomain headers; these should be removed. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Kevin Hilman <khilman@deeprootsystems.com> Cc: Omar Ramirez Luna <omar.ramirez@ti.com> Cc: Felipe Contreras <felipe.contreras@gmail.com> Cc: Greg Kroah-Hartman <greg@kroah.com>
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c166381d |
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09-Dec-2010 |
Jean Pihet <j-pihet@ti.com> |
OMAP2+: disable idle early in the suspend sequence Some bad interaction between the idle and the suspend paths has been identified: the idle code is called during the suspend enter and exit sequences. This could cause corruption or lock-up of resources. The solution is to move the calls to disable_hlt at the very beginning of the suspend sequence (ex. in omap3_pm_begin instead of omap3_pm_prepare), and the call to enable_hlt at the very end of the suspend sequence (ex. in omap3_pm_end instead of omap3_pm_finish). Tested with RET and OFF on Beagle and OMAP3EVM. Signed-off-by: Jean Pihet <j-pihet@ti.com> Cc: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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2f55ac07 |
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16-Nov-2010 |
Lionel Debroux <lionel_debroux@yahoo.fr> |
suspend: constify platform_suspend_ops While at it, fix two checkpatch errors. Several non-const struct instances constified by this patch were added after the introduction of platform_suspend_ops in checkpatch.pl's list of "should be const" structs (79404849e90a41ea2109bd0e2f7c7164b0c4ce73). Patch against mainline. Inspired by hunks of the grsecurity patch, updated for newer kernels. Signed-off-by: Lionel Debroux <lionel_debroux@yahoo.fr> Acked-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
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5643aebb |
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02-Aug-2010 |
Rajendra Nayak <rnayak@ti.com> |
omap4: suspend: Add basic system suspend support This patch adds support for basic suspend doing a CPUx wfi for OMAP4. All powerdomains are for now are kept programmed in ON state. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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