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0fdebc5e |
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07-Jun-2022 |
Thomas Gleixner <tglx@linutronix.de> |
treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_56.RULE (part 1) Based on the normalized pattern: this file is licensed under the terms of the gnu general public license version 2 this program is licensed as is without any warranty of any kind whether express or implied extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference. Reviewed-by: Allison Randal <allison@lohutok.net> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
7af2ea3b |
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13-Apr-2019 |
Nicholas Mc Guire <hofrat@osadl.org> |
ARM: mvebu: drop return from void function The return statement is unnecessary here - so drop it. Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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3972863a |
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25-Jul-2018 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
ARM: mvebu: use dt_fixup to provide fallback for enable-method We need to maintain backwards compatibility with device trees that don't define an enable method. At the same time we want the device tree to be able to specify an enable-method and have it stick. Previously by having smp assigned in the DT_MACHINE definition this would be picked up by setup_arch() and override whatever arm_dt_init_cpu_maps() had configured. Now we move the initial assignment of default smp_ops to a dt_fixup and let arm_dt_init_cpu_maps() override that if the device tree defines an enable-method. [olof@lixom.net: Wrap set_smp_ops() in CONFIG_SMP.] Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Tested-by: Gregory CLEMENT <gregory.clement@bootlin.com> (on AX3) Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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#
850bea23 |
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01-Jun-2016 |
Kefeng Wang <wangkefeng.wang@huawei.com> |
arm: Remove unnecessary of_platform_populate with default match table After patch "of/platform: Add common method to populate default bus", it is possible for arch code to remove unnecessary callers of of_platform_populate with default match table. Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Ray Jui <rjui@broadcom.com> Cc: Lee Jones <lee@kernel.org> Cc: Krzysztof Halasa <khalasa@piap.pl> Cc: Kukjin Kim <kgene@kernel.org> Cc: Rob Herring <robh@kernel.org> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Santosh Shilimkar <ssantosh@kernel.org> Cc: Roland Stigge <stigge@antcom.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Haojian Zhuang <haojian.zhuang@gmail.com> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Viresh Kumar <vireshk@kernel.org> Cc: Shiraz Hashim <shiraz.linux.kernel@gmail.com> Cc: Tony Prisk <linux@prisktech.co.nz> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Russell King <linux@arm.linux.org.uk> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by: Rob Herring <robh@kernel.org>
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ef2cdccd |
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14-Oct-2015 |
Lucas Stach <l.stach@pengutronix.de> |
ARM: mvebu: remove the workaround imprecise abort fault handler This is not needed anymore. Handling a potentially pending imprecise external abort left behind by the bootloader is now done in a slightly safer way inside the common ARM startup code. [gregory.clement@free-electrons.com: Beside the Armada 375 Z1 which initially required this, is no more supported] Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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c81c1166 |
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23-Jun-2015 |
Stephen Boyd <sboyd@codeaurora.org> |
ARM: mvebu: Remove clk-provider.h include This file doesn't use the clk provider APIs. Remove the include. Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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242ede0b |
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03-Mar-2015 |
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
ARM: mvebu: add core support for Armada 39x This commit adds the core support for Armada 39x, which is quite simple: - a new Kconfig option which selects the appropriate clock and pinctrl drivers as well as other common features (GIC, L2 cache, SMP, etc.) - a new DT_MACHINE_START which references the top-level compatible strings supported for the Marvell Armada 39x. - a new SMP enable-method. The mechanism to enable CPUs for Armada 39x appears to be the same as Armada 38x. However, we do not want to use marvell,armada-380-smp in the Device Tree, in the case of the discovery of a subtle difference in the future, which would require changing the Device Tree. And the enable-method isn't a compatible string: you can't specify several values and expect a fallback on the second string if the first one isn't supported. Therefore, we simply declare the SMP enable method "marvell,armada-390-smp" as doing the same thing as the "marvell,armada-380-smp" one. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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bc2d7a58 |
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03-Mar-2015 |
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
ARM: mvebu: add __initconst specifiers on DT_MACHINE_START dt_compat tables As suggested by Stephen Boyd, this commit adds the __initconst specifier to the dt_compat table declarations used by the DT_MACHINE_START structures in mach-mvebu land. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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8da2b2f7 |
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21-Nov-2014 |
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
ARM: mvebu: reserve the first 10 KB of each memory bank for suspend/resume When going out of suspend to RAM, the Marvell EBU platforms go through the bootloader, which re-configures the DRAM controller. To achieve this, the bootloader executes a piece of code called the "DDR3 training code". It does some reads/writes to the memory to find out the optimal timings for the memory chip being used. This has the nasty side effect that the first 10 KB of each DRAM chip-select are overwritten by the bootloader when exiting the suspend to RAM state. Therefore, this commit implements the ->reserve() hook for the 'struct machine_desc' used on Armada XP, to reserve the 10 KB of each DRAM chip-select using the memblock API. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1416585613-2113-11-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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316fbbc4 |
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29-Oct-2014 |
Gregory CLEMENT <gregory.clement@bootlin.com> |
ARM: mvebu: Clean-up the Armada XP support This patch removes the unneeded include of the armada-370-xp.h header. It also moves some declarations from this file into more accurate places. Finally, it also adds a comment explaining that we can't remove yet the smp field in the dt machine struct due to backward compatibly of the device tree. In a few releases, when the old device tree will be obsolete, we will be able to remove the smp field and then the armada-370-xp.h header. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1414669184-16785-2-git-send-email-gregory.clement@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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#
172ed82c |
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04-Nov-2014 |
Ezequiel Garcia <ezequiel.garcia@free-electrons.com> |
ARM: mvebu: Remove thermal quirk for A375 Z1 revision The Armada 375 Z1 SoC revision is no longer supported. This commit removes the quirk required to "fix" the reg property and the compatible string of the thermal devicetree node. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1415116839-4323-3-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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#
5129ee22 |
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26-Jul-2014 |
Andrew Lunn <andrew@lunn.ch> |
ARM: mvebu: armada xp: Generalize use of i2c quirk A second product has come to light which makes use of the A0 stepping of the Armada XP SoC. A0 stepping has a hardware bug in the i2c core meaning that hardware offload does not work, resulting in the kernel failing to boot. The quirk detects that the kernel is running on an A0 stepping SoC and disables the use of hardware offload. Currently the quirk is only enabled for PlatHome Openblocks AX3. The AX3 has been produced with both A0 and B0 stepping SoCs. The second product is the Lenovo Iomega IX4-300d. It seems likely that this device will also swap from A0 to B0 SoC sometime during its life. If there are two products using A0, it seems likely there are more products with A0. Also, since the number of A0 SoCs is limited, these products are also likely to transition to B0. Hence detecting at run time is the safest option. So enable the quirk for all Armada XP boards. Tested on an AX3 with A0 stepping. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: stable@vger.kernel.org # v3.12+ Fixes: 930ab3d403ae: ("i2c: mv64xxx: Add I2C Transaction Generator support") Link: https://lkml.kernel.org/r/1406395238-29758-2-git-send-email-andrew@lunn.ch Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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#
6a2b5343 |
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23-Jul-2014 |
Gregory CLEMENT <gregory.clement@bootlin.com> |
ARM: mvebu: export the SCU address The SCU address will be needed in other files than board-v7.c, especially in pmsu.c for cpuidle related activities. So this patch adds a function that allows to retrieve the virtual address at which the SCU has been mapped. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1406120453-29291-10-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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#
01178890 |
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12-Jun-2014 |
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
ARM: mvebu: update L2/PCIe deadlock workaround after L2CC cleanup Commit 497a92308af8e9385fa3d135f7f416a997e4b93b ("ARM: mvebu: implement L2/PCIe deadlock workaround") introduced some logic in coherency.c to adjust the PL310 cache controller Device Tree node of Armada 375 and Armada 38x platform to include the 'arm,io-coherent' property if the system is running with hardware I/O coherency enabled. However, with the L2CC driver cleanup done by Russell King, the initialization of the L2CC driver has been moved earlier, and is now part of the init_IRQ() ARM function in arch/arm/kernel/irq.c. Therefore, calling coherency_init() in ->init_time() is now too late, as the Device Tree property gets added too late (after the L2CC driver has been initialized). In order to fix this, this commit removes the ->init_time() callback use in board-v7.c and replaces it with an ->init_irq() callback. We therefore no longer use the default ->init_irq() callback, but we now use the default ->init_time() callback. In this newly introduced ->init_irq() callback, we call irqchip_init() which is the default behavior when ->init_irq() isn't defined, and then do the initialization related to the coherency: SCU, coherency fabric, and mvebu-mbus (which is needed to start secondary CPUs). Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1402585772-10405-4-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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752ef800 |
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12-Jun-2014 |
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
ARM: mvebu: move Armada 375 external abort logic as a quirk In preparation to a small re-organization of the initialization sequence in board-v7.c, this commit moves the registration of the custom external abort handler on Armada 375 later in the boot sequence, and makes it more similar to the other quirks that we already have. There is indeed no need to register this abort handler particularly early, it simply needs to be registered before switching to userspace. In addition to this, this commit makes the registration of the custom abort handler conditional on Armada 375 Z1, because Armada 375 A0 and later iterations are not affected by the issue. This commit was tested on both Armada 375 Z1 and Armada 375 A0 platforms. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1402585772-10405-3-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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9d637348 |
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10-Jun-2014 |
Ezequiel Garcia <ezequiel.garcia@free-electrons.com> |
ARM: mvebu: Don't apply the thermal quirk if the SoC revision is unknown Currently, the thermal quirk is skipped only if the SoC revision is known to be one that does not need them, but if the SoC revision cannot be obtained, the quirk is applied assuming it's needed. However, this quirk must be applied only we are sure the SoC needs it, for it breaks the thermal support if applied on a SoC that doesn't need it. The reason for this is that the quirk consists in changing the thermal devicetree compatible string and register offsets, to workaround a hardware bug in the early SoC revision. Such changes are wrong if the SoC is a new revision and doesn't need the workaround. Therefore, this commit changes the behavior, by requiring the SoC revision to be known in order to peform a quirk. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1402425283-24989-1-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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9e47aaef |
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06-Jun-2014 |
Linus Torvalds <torvalds@linux-foundation.org> |
Fix ARM merge mistake in mvebu board file Russell King points out that my ARM merge (commit eb3d3ec567e8) was broken wrt the arch/arm/mach-mvebu/board-v7.c file, leaving in a stale l2x0_of_init() call (it's now handled by the DT description). Which is kind of embarrassing, since I knew about it as it wasn't the only file that had similar merge issues. At least I got the other ones right. Reported-by: Russell King <rmk@arm.linux.org.uk> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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9847cf04 |
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28-Apr-2014 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: l2c: mvebu: convert to generic l2c OF initialisation Remove the explicit call to l2x0_of_init(), converting to the generic infrastructure instead. Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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d453ef75 |
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18-Mar-2014 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: l2c: remove unnecessary UL-suffix to mask values They're u32, they're not unsigned long. The UL suffix is not required here. Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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c1a01a03 |
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05-May-2014 |
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
ARM: mvebu: fix thermal quirk SoC revision check In commit 54fe26a900bc528f3df1e4235cb6b9ca5c6d4dc2 ('ARM: mvebu: Add thermal quirk for the Armada 375 DB board'), a check on the Armada SoC revision was added to decide whether a quirk for the thermal device should be applied or not. However, the quirk implementation has a bug: it assumes mvebu_get_soc_id() returns true on success, but it returns 0. Therefore, the condition: if (mvebu_get_soc_id(&dev, &rev) && rev > ARMADA_375_Z1_REV) is always false (as long as mvebu-soc-id is properly initialized). As a consequence, the quirk is always applied, even on A0 steppings, for which the quirk should not be applied. This was spotted by testing the thermal driver on Armada 375 A0, which Ezequiel could not do since he does not have access to the A0 revision of the SoC for the moment. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1399302326-6917-2-git-send-email-thomas.petazzoni@free-electrons.com Fixes: 54fe26a900bc528f3df1e4235cb6b9ca5c6d4dc2 ('ARM: mvebu: Add thermal quirk for the Armada 375 DB board') Acked-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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5fd62066 |
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24-Apr-2014 |
Ezequiel Garcia <ezequiel.garcia@free-electrons.com> |
ARM: mvebu: Add thermal quirk for the Armada 375 DB board The initial release of the Armada 375 DB board has an Armada 375 Z1 stepping silicon. This commit introduces a quirk that allows to workaround a series of issues with the thermal sensor in this stepping, but updating the devicetree: * Updates the compatible string for the thermal, so the driver can perform a specific initialization of the sensor. * Moves the offset of the thermal control register. This quirk allows to specifiy the correct (A0 stepping) offset in the devicetree. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1398371004-15807-9-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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8eee0f81 |
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19-Apr-2014 |
Gregory CLEMENT <gregory.clement@bootlin.com> |
ARM: mvebu: fix the name of the parameter used in mvebu_get_soc_id The name of the two parameters of mvebu_get_soc_id were inverted. This patch fix it in order to have a more readable code. Reported-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1397925170-8202-3-git-send-email-gregory.clement@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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c42e1ffa |
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19-Apr-2014 |
Gregory CLEMENT <gregory.clement@bootlin.com> |
ARM: mvebu: remove unnecessary ifdef around l2x0_of_init l2x0_of_init function is always defined arch/arm/include/asm/hardware/cache-l2x0.h: in case of CONFIG_CACHE_L2X0 is not selected then a placeholder is defined. Then there is no need to have ifdef around l2x0_of_init. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1397925170-8202-2-git-send-email-gregory.clement@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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8e6ac203 |
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14-Apr-2014 |
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
ARM: mvebu: enable the ARM SCU on Armada 375 and Armada 38x Contrary to the Armada 370 and XP that used the PJ4B Marvell cores, the Armada 375 and Armada 38x use the ARM Cortex-A9. A consequence of this is that the unit responsible for the coherency between CPUs is now the ARM SCU, and not the Marvell coherency unit (which is still present to do coherency with I/O devices). Therefore this commit: * Ensures that the selection of the Armada 375 or Armada 38x SoC support enables the ARM SCU support in the kernel. * Make sure to initialize the SCU at boot time. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1397483228-25625-6-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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5686a1e5 |
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14-Apr-2014 |
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
bus: mvebu: pass the coherency availability information at init time Until now, the mvebu-mbus was guessing by itself whether hardware I/O coherency was available or not by poking into the Device Tree to see if the coherency fabric Device Tree node was present or not. However, on some upcoming SoCs, the presence or absence of the coherency fabric DT node isn't sufficient: in CONFIG_SMP, the coherency can be enabled, but not in !CONFIG_SMP. In order to clean this up, the mvebu_mbus_dt_init() function is extended to get a boolean argument telling whether coherency is enabled or not. Therefore, the logic to decide whether coherency is available or not now belongs to the core SoC code instead of the mvebu-mbus driver itself, which is much better. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1397483228-25625-4-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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9aa30f1c |
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17-Feb-2014 |
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
ARM: mvebu: add initial support for the Armada 380/385 SOCs This commit adds the basic support for the Armada 380 and Armada 385 SOCs. These SoCs share most of their IP with the Armada 370/XP SoCs. The main difference is the use of a Cortex A9 CPU instead of the PJ4B CPU. The Armada 380 is a single core Cortex-A9, while the Armada 385 is a dual-core Cortex-A9. The support is introduced in board-v7.c, together with Armada 370/XP, but a separate DT structure is added, because Armada 38x will need a different set of SMP operations when the SMP support is introduced. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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ca4a6f87 |
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17-Feb-2014 |
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
ARM: mvebu: add workaround for data abort issue on Armada 375 Early versions of Armada 375 SoC have a bug where the BootROM leaves an external data abort pending. The kernel is hit by this data abort as soon as it enters userspace, because it unmasks the data aborts at this moment. We register a custom abort handler below to ignore the first data abort to work around this problem. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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d3ce7f25 |
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17-Feb-2014 |
Gregory CLEMENT <gregory.clement@bootlin.com> |
ARM: mvebu: add initial support for the Armada 375 SOCs This commit adds the basic support for the Armada 375 SOCs. These SoCs share most of their IP with the Armada 370/XP SoCs. The main difference is the use of a Cortex A9 CPU instead of the PJ4B CPU. The interrupt controller and the L2 cache controller are also different they are respectively the GIC and the PL310. The support is introduced in board-v7.c, together with Armada 370/XP, but a separate DT structure is added, because Armada 375 will need a different set of SMP operations when the SMP support is introduced. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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a017dbb6 |
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17-Feb-2014 |
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
ARM: mvebu: rename DT machine structure for Armada 370/XP Due to a mistake made when merging Armada 370 and Armada XP DT machine structures, the name of the structure was incorrectly chosen as being ARMADA_XP_DT, while the structure also covers Armada 370. Therefore, we rename the structure to ARMADA_370_XP_DT. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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99b3d294 |
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17-Feb-2014 |
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
ARM: mvebu: rename armada-370-xp.c to board-v7.c In preparation to the introduction of the support of Armada 375 and Armada 38x, this commit renames arch/arm/mach-mvebu/armada-370-xp.c to arch/arm/mach-mvebu/board-v7.c. The board-v7.c name as we expect this file to ultimately contain the DT_MACHINE_START definitions for all ARMv7 Marvell EBU platforms (370, 375, 38x, XP and Dove as of today). In relation to this file rename, this commit also: * Renames the hidden Kconfig symbol MACH_ARMADA_370_XP to MACH_MVEBU_V7. This hidden symbol is selected by the various per-SoC visible Kconfig options to trigger the build of board-v7.c. * Renames a certain number of functions in board-v7.c so that their armada_370_xp prefix is replaced by a mvebu prefix. The .dt_compat array keeps its armada_370_xp prefix because the new SOCs will be introduced with separate .dt_compat arrays, due to the need for different SMP operations. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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