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2f618d5e |
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09-Mar-2022 |
Arnd Bergmann <arnd@arndb.de> |
ARM: remove support for NOMMU ARMv4/v5 It is possible to build MMU-less kernels for Cortex-M base microcrontrollers as well as a couple of older platforms that have not been converted to CONFIG_ARCH_MULTIPLATFORM, specifically ep93xx, footbridge, dove, sa1100 and s3c24xx. It seems unlikely that anybody has tested those configurations in recent years, as even building them is frequently broken. A patch I submitted caused another build time regression in this configuration. I sent a patch for that, but it seems better to also remove the option entirely, leaving ARMv7-M as the only supported Arm NOMMU target for simplicity. A couple of platforms have dependencies on CONFIG_MMU, those can all be removed now. Notably, mach-integrator tries to support MMU-less CPU cores, but those have not actually been selectable for a long time. This addresses several build failures in randconfig builds that have accumulated over the years. Cc: Vladimir Murzin <vladimir.murzin@arm.com> Cc: Russell King <linux@armlinux.org.uk> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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d2912cb1 |
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04-Jun-2019 |
Thomas Gleixner <tglx@linutronix.de> |
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500 Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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c94e4ad2 |
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19-Aug-2016 |
Russell King <rmk+kernel@armlinux.org.uk> |
ARM: document and update UNCACHEABLE_ADDR definitions Document the UNCACHEABLE_ADDR definitions for footbridge and SA1100 so that we know where they're located and/or what they're accessing. Change RiscPC to calculate the UNCACHEABLE_ADDR value from FLUSH_BASE as that's where we locate that. UNCACHEABLE_ADDR is used to perform an uncached access (ARMv4 terminology) necessary to force a CPU clock-switch to the memory- speed clock, as required for entering WFI. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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43024ed6 |
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30-Nov-2013 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: footbridge: cleanup LEDs code Cleanup the LEDs code to use ioremap()/writeb() to access the register. This allows us to move the definitions out of a header file directly into the ebsa285 support code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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bd31b859 |
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03-Jul-2009 |
Thomas Gleixner <tglx@linutronix.de> |
locking, ARM: Annotate low level hw locks as raw Annotate the low level hardware locks which must not be preempted. In mainline this change documents the low level nature of the lock - otherwise there's no functional difference. Lockdep and Sparse checking will work as usual. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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c9d95fbe |
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28-Jun-2011 |
Rob Herring <rob.herring@calxeda.com> |
ARM: convert PCI defines to variables Convert PCIBIOS_MIN_IO and PCIBIOS_MIN_MEM to variables to allow multi-platform builds. This also removes the requirement for a platform to have a mach/hardware.h. The default values for i/o and mem are 0x1000 and 0x01000000, respectively. Per Arnd Bergmann, other values are likely to be incorrect, but this commit does not try to address that issue. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
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dc8d966b |
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29-Jun-2011 |
Rob Herring <rob.herring@calxeda.com> |
ARM: pci: make pcibios_assign_all_busses use pci_has_flag Convert pcibios_assign_all_busses from a define to inline so platforms can control this setting. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
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6fa85e5c |
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09-Mar-2011 |
Stepan Moskovchenko <stepanm@codeaurora.org> |
ARM: 6796/1: Footbridge: Fix I/O mappings for NOMMU mode Use the correct I/O address definitions for Footbridge peripherals when the kernel is compiled without MMU support. Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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70d13e08 |
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06-Dec-2008 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] netwinder: clean up GPIO naming Netwinder was using gpio_xxx names which could clash with the GPIO layer. Add a 'nw_' prefix to ensure that these remain separate. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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3a72d8ae |
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28-Nov-2008 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] footbridge: mach/hardware.h doesn't require mach/memory.h Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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32687817 |
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28-Nov-2008 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] footbridge: avoid polluting the kernel's namespace Avoid unnecessarily pollution of the kernel's namespace by avoiding mach/hardware.h in mach/io.h. Include this header file where necessary. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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a09e64fb |
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05-Aug-2008 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] Move include/asm-arm/arch-* to arch/arm/*/include/mach This just leaves include/asm-arm/plat-* to deal with. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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