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e1fca695 |
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12-Dec-2023 |
Nandhini Srikandan <nandhini.srikandan@intel.com> |
spi: dw: Remove Intel Thunder Bay SOC support Remove Intel Thunder Bay specific code as the product got cancelled and there are no end customers or users. Signed-off-by: Nandhini Srikandan <nandhini.srikandan@intel.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://msgid.link/r/20231213060836.29203-3-nandhini.srikandan@intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
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9f778f37 |
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25-Sep-2023 |
Rob Herring <robh@kernel.org> |
spi: dt-bindings: Make "additionalProperties: true" explicit Make it explicit that child nodes have additional properties and the child node schema is not complete. The complete schemas are applied separately based the compatible strings. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20230925212614.1974243-1-robh@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
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7bac98a3 |
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06-Jun-2023 |
Abe Kohandel <abe.kohandel@intel.com> |
spi: dt-bindings: snps,dw-apb-ssi: Add compatible for Intel Mount Evans SoC Document the DesignWare SSI controller compatible for Intel Mount Evans Integrated Management Complex SoC. Signed-off-by: Abe Kohandel <abe.kohandel@intel.com> Link: https://lore.kernel.org/r/20230606145402.474866-3-abe.kohandel@intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
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6282a6ce |
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10-Apr-2023 |
Brad Larson <blarson@amd.com> |
spi: dw: Add AMD Pensando Elba SoC SPI Controller The AMD Pensando Elba SoC has integrated the DW APB SPI Controller Signed-off-by: Brad Larson <blarson@amd.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Serge Semin <fancer.lancer@gmail.com> Link: https://lore.kernel.org/r/20230410184526.15990-5-blarson@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
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99a7fa0e |
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24-Jan-2023 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
spi: dt-bindings: drop unneeded quotes Cleanup by removing unneeded quotes from refs and redundant blank lines. No functional impact except adjusting to preferred coding style. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> # aspeed Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> # meson Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> # st Reviewed-by: Heiko Stuebner <heiko@sntech.de> # rockchip Reviewed-by: Serge Semin <fancer.lancer@gmail.com> # synopsys Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230124083342.34869-1-krzysztof.kozlowski@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
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52069b2a |
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23-Aug-2022 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
spi: dt-bindings: snps,dw-apb-ssi: drop ref from reg-io-width reg-io-width is a standard property, so no need for defining its type Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220823100937.386880-1-krzysztof.kozlowski@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
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0d085723 |
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12-Jul-2022 |
Nandhini Srikandan <nandhini.srikandan@intel.com> |
spi: Add bindings for Intel Thunder Bay SOC Add documentation for SPI controller in Intel Thunder Bay SoC. Signed-off-by: Nandhini Srikandan <nandhini.srikandan@intel.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Serge Semin <fancer.lancer@gmail.com> Link: https://lore.kernel.org/r/20220713042223.1458-3-nandhini.srikandan@intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
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8b037cab |
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29-Jun-2022 |
Conor Dooley <conor.dooley@microchip.com> |
spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width Most users of dw-apb-ssi use spi-{r,t}x-bus-width of 1, however the Canaan k210 is wired up for a width of 4. Quoting Serge: The modern DW APB SSI controllers of v.4.* and newer also support the enhanced SPI Modes too (Dual, Quad and Octal). Since the IP-core version is auto-detected at run-time there is no way to create a DT-schema correctly constraining the Rx/Tx SPI bus widths. /endquote As such, drop the restriction on only supporting a bus width of 1. Link: https://lore.kernel.org/all/20220620205654.g7fyipwytbww5757@mobilestation/ Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Serge Semin <fancer.lancer@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Tested-by: Niklas Cassel <niklas.cassel@wdc.com> Link: https://lore.kernel.org/r/20220629184343.3438856-5-mail@conchuod.ie Signed-off-by: Mark Brown <broonie@kernel.org>
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b658be56 |
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25-May-2022 |
Rob Herring <robh@kernel.org> |
spi: dt-bindings: Move 'rx-sample-delay-ns' to spi-peripheral-props.yaml SPI bus per device properties must be defined in spi-peripheral-props.yaml for unevaluatedProperties checks to work correctly on device nodes. This has the side effect of promoting 'rx-sample-delay-ns' to be a common property, but functionally it's no different if it was defined in a Synopsys specific schema file. Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220525210053.2488756-1-robh@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
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d7a48e27 |
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20-Sep-2021 |
Apurva Nandan <a-nandan@ti.com> |
spi: Use 'flash' node name instead of 'spi-flash' in example Change the nodename in the example with spi-nand from 'spi-flash@1' to 'flash@1' to make the schema uniform with both spi-nand and spi-nor flashes. jedec,spi-nor.yaml uses 'flash@' nodename for spi-nor flashes, so make the spi-nand examples in dt-bindings use it too for uniformity. Signed-off-by: Apurva Nandan <a-nandan@ti.com> Reviewed-by: Serge Semin <fancer.lancer@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210920142713.129295-3-a-nandan@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
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029d32a8 |
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06-May-2021 |
Geert Uytterhoeven <geert+renesas@glider.be> |
spi: dw-apb-ssi: Integrate Renesas RZ/N1 SPI controller Originally, the Renesas RZ/N1 SPI Controller DT bindings were not integrated in the main DT bindings for the Synopsys DesignWare Synchronous Serial Interface, but in its own file, as the RZ/N1 controller has additional registers for software CS control and DMA. As so far DMA is not supported on RZ/N1, and json-schema can handle any possible differences fine, integrate the RZ/N1 compatible values in the main DT bindings for the Synopsys DW SSI. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/aef15aa119ed02487ded4691141678bc1040c3b4.1620301936.git.geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org>
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7b14a272 |
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05-Dec-2020 |
Damien Le Moal <damien.lemoal@wdc.com> |
dt-bindings: spi: dw-apb-ssi: Add Canaan K210 SPI controller Update the snps,dw-apb-ssi.yaml document to include the compatibility string "canaan,k210-spi" compatible string for the Canaan Kendryte K210 RISC-V SoC DW apb_ssi V4 SPI controller. Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> Acked-by: Serge Semin <fancer.lancer@gmail.com> Link: https://lore.kernel.org/r/20201206011817.11700-2-damien.lemoal@wdc.com Signed-off-by: Mark Brown <broonie@kernel.org>
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ca4e2ac2 |
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07-Oct-2020 |
Serge Semin <Sergey.Semin@baikalelectronics.ru> |
spi: dw: Add Baikal-T1 SPI Controller bindings These controllers are based on the DW APB SSI IP-core and embedded into the SoC, so two of them are equipped with IRQ, DMA, 64 words FIFOs and 4 native CS, while another one as being utilized by the Baikal-T1 System Boot Controller has got a very limited resources: no IRQ, no DMA, only a single native chip-select and just 8 bytes Tx/Rx FIFOs available. That's why we have to mark the IRQ to be optional for the later interface. The SPI controller embedded into the Baikal-T1 System Boot Controller can be also used to directly access an external SPI flash by means of a dedicated FSM. The corresponding MMIO region availability is switchable by the embedded multiplexor, which phandle can be specified in the dts node. * We added a new example to test out the non-standard Baikal-T1 System Boot SPI Controller DT binding. Co-developed-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru> Signed-off-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20201007235511.4935-21-Sergey.Semin@baikalelectronics.ru Signed-off-by: Mark Brown <broonie@kernel.org>
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5ce78f44 |
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24-Aug-2020 |
Lars Povlsen <lars.povlsen@microchip.com> |
dt-bindings: snps, dw-apb-ssi: Add sparx5 support, plus rx-sample-delay-ns property This has the following changes for the snps,dw-apb-ss DT bindings: - Add "microchip,sparx5-spi" as the compatible for the Sparx5 SoC controller - Add the property "rx-sample-delay-ns" Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20200824203010.2033-5-lars.povlsen@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
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164c05f0 |
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29-May-2020 |
Serge Semin <Sergey.Semin@baikalelectronics.ru> |
spi: Convert DW SPI binding to DT schema Modern device tree bindings are supposed to be created as YAML-files in accordance with dt-schema. This commit replaces two DW SPI legacy bare text bindings with YAML file. As before the bindings file states that the corresponding dts node is supposed to be compatible either with generic DW APB SSI controller or with Microsemi/Amazon/Renesas/Intel vendors-specific controllers, to have registers, interrupts and clocks properties. Though in case of Microsemi version of the controller there must be two registers resources specified. Properties like clock-names, reg-io-width, cs-gpio, num-cs, DMA and slave device sub-nodes are optional. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Reviewed-by: Rob Herring <robh@kernel.org> Cc: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru> Cc: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: Feng Tang <feng.tang@intel.com> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: linux-mips@vger.kernel.org Link: https://lore.kernel.org/r/20200529182544.9807-1-Sergey.Semin@baikalelectronics.ru Signed-off-by: Mark Brown <broonie@kernel.org>
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