dt-bindings: mailbox: fsl,mu: add i.MX95 Generic/ELE/V2X MU compatible

Add i.MX95 Generic, Secure Enclave and V2X Message Unit compatible string.
And the MUs in AONMIX has internal RAMs for SCMI shared buffer usage.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>

dt-bindings: mailbox: fsl,mu: add new tx doorbell channel

Add new tx doorbell channel for i.MX95 SCMI mailbox usage.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>

dt-bindings: mailbox: imx-mu: add RST channel

i.MX MU has a MUR bit which is to reset both the Processor B and the
Processor A sides of the MU module, forcing all control and status
registers to return to their default values (except the BHR bit in the ACR
register and BHRM bit in BCR register), and all internal states to be
cleared.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>

dt-bindings: mailbox: imx-mu: add i.MX93 S4 MU support

Similar to i.MX8ULP S4 MU, i.MX93 MU is dedicated for communication
between Sentinel and Cortex-A cores from hardware design, it could not be
reused for other purpose.

However i.MX93 S4 MU use separate tx/rx interrupt, so update
interrupts and add interrupt-names property.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>

dt-bindings: mailbox: imx-mu: add i.MX93 MU

Add bindings for i.MX93 MU which derived from i.MX8ULP

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>

dt-bindings: mailbox: imx-mu: add i.MX8 SECO MU support

Similar to i.MX8QM/QXP SCU, i.MX8 SECO MU is dedicated for
communication between SECO and Cortex-A cores from hardware design,
it could not be reused for other purpose. To use SECO MU more
effectivly, add "fsl,imx8-mu-seco" compatile to support fast IPC.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>

dt-bindings: mailbox: imx-mu: add i.MX8ULP S400 MU support

Similar to i.MX8QM/QXP SCU, i.MX8ULP SCU MU is dedicated for
communication between S400 and Cortex-A cores from hardware design,
it could not be reused for other purpose. To use S400 MU more
effectivly, add "fsl,imx8ulp-mu-s4" compatile to support fast IPC.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>

dt-bindings: mailbox: imx-mu: add i.MX8ULP MU support

The register layout and bits definition of i.MX8ULP MU is different
compared with others, let's add the compatible for the new MU.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>

dt-bindings: mailbox: mu: add imx8qm support

Add imx8qm support

Cc: devicetree@vger.kernel.org
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

dt-bindings: mailbox: fsl,mu: Add missing power-domains

Add quite common property - power-domains - to fix dtbs_check warnings
like:

arch/arm64/boot/dts/freescale/imx8qxp-mek.dt.yaml:
mailbox@5d280000: 'power-domains' does not match any of the regexes: 'pinctrl-[0-9]+'

Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20201002161837.5784-1-krzk@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>

dt-bindings: mailbox: fsl,mu: Fix i.MX 8QXP compatible matching

The Mailbox on i.MX 8QXP (fsl,imx8qxp-mu) can also be compatible with
fsl,imx8-mu-scu (for fast IPC) so adjust the compatibles to fix
dtbs_check warnings like:

arch/arm64/boot/dts/freescale/imx8qxp-mek.dt.yaml: mailbox@5d1f0000:
compatible: ['fsl,imx8-mu-scu', 'fsl,imx8qxp-mu', 'fsl,imx6sx-mu']
is not valid under any of the given schemas (Possible causes of the failure):

arch/arm64/boot/dts/freescale/imx8qxp-mek.dt.yaml: mailbox@5d1f0000:
compatible: ['fsl,imx8-mu-scu', 'fsl,imx8qxp-mu', 'fsl,imx6sx-mu'] is too long

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20200903195325.5394-1-krzk@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>

dt-bindings: Whitespace clean-ups in schema files

Clean-up incorrect indentation, extra spaces, long lines, and missing
EOF newline in schema files. Most of the clean-ups are for list
indentation which should always be 2 spaces more than the preceding
keyword.

Found with yamllint (which I plan to integrate into the checks).

Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-clk@vger.kernel.org
Cc: dri-devel@lists.freedesktop.org
Cc: linux-spi@vger.kernel.org
Cc: linux-gpio@vger.kernel.org
Cc: linux-remoteproc@vger.kernel.org
Cc: linux-hwmon@vger.kernel.org
Cc: linux-i2c@vger.kernel.org
Cc: linux-fbdev@vger.kernel.org
Cc: linux-iio@vger.kernel.org
Cc: linux-input@vger.kernel.org
Cc: linux-pm@vger.kernel.org
Cc: linux-media@vger.kernel.org
Cc: alsa-devel@alsa-project.org
Cc: linux-mmc@vger.kernel.org
Cc: linux-mtd@lists.infradead.org
Cc: netdev@vger.kernel.org
Cc: linux-rtc@vger.kernel.org
Cc: linux-serial@vger.kernel.org
Cc: linux-usb@vger.kernel.org
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Rob Herring <robh@kernel.org>

dt-bindings: mailbox: Convert imx mu to json-schema

Convert the i.MX MU binding to DT schema format using json-schema

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Rob Herring <robh@kernel.org>