dt-bindings: cpufreq: qcom-hw: document SM8650 CPUFREQ Hardware

Document the CPUFREQ Hardware on the SM8650 Platform.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>

dt-bindings: cpufreq: cpufreq-qcom-hw: Add SDX75 compatible

Add compatible for EPSS CPUFREQ-HW on SDX75.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>

dt-bindings: cpufreq: cpufreq-qcom-hw: add SDM670 compatible

The bindings for Qualcomm CPU frequency have a compatible for each SoC.
Add the compatible for SDM670.

Fixes: 0c665213d126 ("arm64: dts: qcom: sdm670: add cpu frequency scaling")
Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>

dt-bindings: cpufreq: qcom-hw: add a 4th frequency domain

On new platforms, a 4th frequency domain is used, document it.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>

dt-bindings: cpufreq: cpufreq-qcom-hw: Add QCM2290

Document the OSM CPUFREQ_HW present on QCM2290, featuring just one
lonely frequency domain.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>

dt-bindings: cpufreq: cpufreq-qcom-hw: Sanitize data per compatible

Introduce per-SoC compatibles for OSM targets (read: pre-sm8250) and
sanitize the number of interrupt{s,-names} and reg/-names per-compatible.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>

dt-bindings: cpufreq: cpufreq-qcom-hw: Allow just 1 frequency domain

Some SoCs implementing CPUFREQ-HW only have a single frequency domain.
Allow such case.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>

dt-bindings: cpufreq: qcom-hw: add a compatible for sa8775p

Add the compatible for the cpufreq engine present on sa8775p platforms.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>

dt-bindings: cpufreq: cpufreq-qcom-hw: Add SM8550 compatible

Add compatible for EPSS CPUFREQ-HW on SM8550.
Also document the interrupts.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>

dt-bindings: cpufreq: cpufreq-qcom-hw: Add missing compatibles

Document the cpufreq-epss compatibles currently used in the tree, plus
the sc7280 which will be added in a separate commit.

Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>

dt-bindings: cpufreq: cpufreq-qcom-hw: document interrupts

The Qualcomm Soc cpufreq hardware engine has LMh/thermal throttling
interrupts (already present in SM8250 and SM8450 DTS) and Linux driver
uses them:

sm8250-hdk.dtb: cpufreq@18591000: 'interrupt-names', 'interrupts' do not match any of the regexes: 'pinctrl-[0-9]+'
sm8450-qrd.dtb: cpufreq@17d91000: 'interrupt-names', 'interrupts' do not match any of the regexes: 'pinctrl-[0-9]+'

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>

dt-bindings: cpufreq: cpufreq-qcom-hw: Add QDU1000/QRU1000 cpufreq

Add cpufreq epss for QDU1000 and QRU1000 SoCs.

Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>

dt-bindings: cpufreq: cpufreq-qcom-hw: Add cpufreq clock provider

Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks
to the CPU cores. Document the same in the binding to reflect the actual
implementation.

CPUFreq HW will become the clock provider and CPU cores will become the
clock consumers.

The clock index for each CPU core is based on the frequency domain index.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>

dt-bindings: cpufreq: qcom: Add missing cache related properties

The examples' cache nodes are incomplete as 'cache-unified' and
'cache-level' are required cache properties.

Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>

dt-bindings: cpufreq: cpufreq-qcom-hw: Add SM6375 compatible

Add compatible for EPSS CPUFREQ-HW on SM6375.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>

dt-bindings: cpufreq: cpufreq-qcom-hw: Convert to YAML bindings

Convert Qualcomm cpufreq devicetree binding to YAML.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>