History log of /linux-master/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
Revision Date Author Comments
# 9a042e71 17-Jun-2019 Chris Packham <chris.packham@alliedtelesis.co.nz>

dt-bindings: clock: mvebu: Add compatible string for 98dx1135 core clock

Add compatible string for the core clock on the 98dx1135 switch with
integrated CPU.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>


# b4bcfccb 16-Feb-2017 Chris Packham <chris.packham@alliedtelesis.co.nz>

ARM: dts: mvebu: Move mv98dx3236 clock bindings

Previously the coreclk binding for the 98dx3236 SoC was inherited from
the armada-370/xp. This block is present in as much as it is possible to
read from the register location without causing any harm. However the
actual sampled at reset values are reflected in the DFX block.

Moving the binding to the DFX block enables support for different clock
strapping options in hardware.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>


# 57d0ee07 19-May-2016 Jamie Lentin <jm@lentin.co.uk>

clk: mvebu: Add clk support for the orion5x SoC mv88f5181

Referring to the u-boot sources for the Netgear WNR854T, add support
for the mv88f5181.

[gregory.clement@free-electrons.com: fix commit title]
Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>


# 9baf9688 03-Mar-2015 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>

devicetree: bindings: update DT bindings for Marvell EBU clock support

With the introduction of the Marvell Armada 39x SoC, the DT bindings
for Marvell EBU clocks need to be extended. This commit include the
corresponding update to the Device Tree bindings documentation.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>


# 66ecbfea 22-Apr-2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>

clk: mvebu: add Orion5x clock driver

This commit adds a core clock driver for the Orion5x SoC, with support
for the tclk, the CPU frequency and the DDR frequency. All the details
about the Sample-At-Reset register were extracted from the U-Boot
sources for Orion5x.

Note that Orion5x does not have gatable clocks, so this core clock
driver is sufficient to support clocking on Orion5x platforms.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Link: https://lkml.kernel.org/r/1398202002-28530-5-git-send-email-thomas.petazzoni@free-electrons.com
Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>


# 3e8947ae 10-Feb-2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>

dt: Update binding information for mvebu core clocks with Armada 380/385

Add the binding information for the core clocks of the Armada 380 and
Armada 385 SoCs

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>


# dc04f2b2 10-Feb-2014 Gregory CLEMENT <gregory.clement@bootlin.com>

dt: Update binding information for mvebu core clocks with Armada 375

Add the binding information for the core clocks of the Armada 375 SoCs

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>


# 97fa4cf4 17-Nov-2012 Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

clk: mvebu: add mvebu core clocks.

This driver allows to provide DT clocks for core clocks found on
Marvell Kirkwood, Dove & 370/XP SoCs. The core clock frequencies and
ratios are determined by decoding the Sample-At-Reset registers.

Although technically correct, using a divider of 0 will lead to
div_by_zero panic. Let's use a ratio of 0/1 instead to fail later
with a zero clock.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Tested-by Gregory CLEMENT <gregory.clement@free-electrons.com>