dt-bindings: arm: pmu: Add Cortex A520, A715, A720, X3, and X4

Add compatible strings for the Arm Cortex-A520, Cortex-A715,
Cortex-A720, Cortex-X3, and Cortex-X4 CPU PMUs.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230706205505.308523-1-robh@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>

dt-bindings: arm-pmu: Add PMU compatible strings for Apple M2 cores

The PMUs on the Apple M2 cores avalanche and blizzard CPU are compatible
with M1 ones. As on M1 we don't know exactly what the counters count so
use a distinct compatible for each micro-architecture.
Apple's PMU counter description omits a counter for M2 so there
is some variation on the interpretation of the counters.

Signed-off-by: Janne Grunau <j@jannau.net>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Hector Martin <marcan@marcan.st>
Link: https://lore.kernel.org/r/20230214-apple_m2_pmu-v1-1-9c9213ab9b63@jannau.net
Signed-off-by: Will Deacon <will@kernel.org>

dt-bindings: Improve phandle-array schemas

The 'phandle-array' type is a bit ambiguous. It can be either just an
array of phandles or an array of phandles plus args. Many schemas for
phandle-array properties aren't clear in the schema which case applies
though the description usually describes it.

The array of phandles case boils down to needing:

items:
maxItems: 1

The phandle plus args cases should typically take this form:

items:
- items:
- description: A phandle
- description: 1st arg cell
- description: 2nd arg cell

With this change, some examples need updating so that the bracketing of
property values matches the schema.

Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Vinod Koul <vkoul@kernel.org>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Georgi Djakov <djakov@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Marc Kleine-Budde <mkl@pengutronix.de>
Link: https://lore.kernel.org/r/20220119015038.2433585-1-robh@kernel.org

dt-bindings: arm-pmu: Document Apple PMU compatible strings

As we are about to add support fur the Apple PMUs, document the compatible
strings associated with the two micro-architectures present in the Apple M1.

Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Hector Martin <marcan@marcan.st>
Signed-off-by: Marc Zyngier <maz@kernel.org>

dt-bindings: arm: pmu: Document Denver and Carmel PMUs

Add compatible strings for the NVIDIA Denver and Carmel PMUs.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20211207150746.444478-1-thierry.reding@gmail.com
Signed-off-by: Rob Herring <robh@kernel.org>

dt-bindings: arm: Catch up with Cortex/Neoverse CPUs again

Add bindings for the 2020 and 2021 cohorts of Cortex-A and Neoverse
CPUs, now featuring their Cortex-X cousins as well.

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Link: https://lore.kernel.org/r/a36014d06d308c73d3fa1ed55e8967fb8adadf0d.1638900542.git.robin.murphy@arm.com
Signed-off-by: Rob Herring <robh@kernel.org>

dt-bindings: arm: add Cortex-A78 binding

Add compatible for Cortex-A78 PMU

Signed-off-by: Seiya Wang <seiya.wang@mediatek.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Link: https://lore.kernel.org/r/20210203055348.4935-3-seiya.wang@mediatek.com
Signed-off-by: Will Deacon <will@kernel.org>

dt-bindings: Another round of adding missing 'additionalProperties'

Another round of wack-a-mole. The json-schema default is additional
unknown properties are allowed, but for DT all properties should be
defined.

Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Baolin Wang <baolin.wang7@gmail.com>
Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Liam Girdwood <lgirdwood@gmail.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-By: Vinod Koul <vkoul@kernel.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> # for iio
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Mark Brown <broonie@kernel.org>
Reviewd-by: Corey Minyard <cminyard@mvista.com>
Acked-by: Pavel Machek <pavel@ucw.cz>
Acked-by: Sebastian Reichel <sre@kernel.org>
Link: https://lore.kernel.org/r/20201002234143.3570746-1-robh@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>

dt-bindings: ARM: Clean up PMU compatible list

The "alpha by vendor, reverse-alpha by model" sorting of compatibles
that we seem to have ended up with is decidedly odd. Make it less so.

Also copy the comment from the generic "arm,armv8" CPU binding to help
clarify that the "arm,armv8-pmuv3" binding is rather intended to be a
counterpart to that, for describing implementations without a specific
microarchitecture like the AEMv8 software model.

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Rob Herring <robh@kernel.org>

dt-bindings: ARM: Add recent Cortex/Neoverse PMUs

Add new PMU definitions to correspond with the CPU bindings.

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Rob Herring <robh@kernel.org>

dt-bindings: arm: Convert PMU binding to json-schema

Convert ARM PMU binding to DT schema format using json-schema.

Cc: Will Deacon <will.deacon@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: devicetree@vger.kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>