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fa557843 |
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27-Nov-2022 |
X512 <danger_mail@list.ru> |
riscv: use atomic CSR bit set/clear operations, refactor Fix race conditions that cause broken timer interrupts. Change-Id: I78e13a18d394b1566977e894a1def16a66c9ca5f Reviewed-on: https://review.haiku-os.org/c/haiku/+/5883 Reviewed-by: X512 <danger_mail@list.ru> Reviewed-by: Alex von Gluck IV <kallisti5@unixzen.com> Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
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