intel_extreme: log srcclk info, Sandy/Ivy eDP detect BIOS pipe setup and use that.

intel_extreme: PLLs post skylake work differently again. Refclk update.

intel_extreme: fix overflow in SKL PLL calculation

* RGB 4K@60Hz clock is 594MHz, that multiplied by 5 overflows int value.

Change-Id: Idda04119d582fa4e30c7729296ad5959b29dba77
Reviewed-on: https://review.haiku-os.org/c/haiku/+/4738
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
Reviewed-by: Rudolf Cornelissen <rudhaiku@gmail.com>

intel_extreme: skylake PLL works, all outputs fully functional.

intel_extreme: fix 64-bit build, use

intel_extreme: add haswell/skylake PLL calcs, no functional change yet.

intel_extreme: reduce use of display_mode where display_timing is enough

In most cases we don't need to use the complete display_mode struct and
we just need the timings. This will avoid future confusion between the
virtual width/height and the actual display timings, if we implement
scrolling someday.

Change-Id: I6c4430b84130b956a47ea0a01afb0843f5a34fd2
Reviewed-on: https://review.haiku-os.org/c/haiku/+/4665
Reviewed-by: waddlesplash <waddlesplash@gmail.com>

intel_extreme: updated PLL restricts, updated set- and proposemode. Requested modes are now set more precise.

intel_extreme: disable CK505 clock source

Using the CK505 clock source may need some more checks or configuration
we currently don't do, leading to a blank screen in some systems.
Whatever the reason, disabling it makes the driver work on my machine.

Fixes #16357

Change-Id: If207ffdddcf6e6eb73bc69ce5a8bd2842fd2141b
Reviewed-on: https://review.haiku-os.org/c/haiku/+/3867
Reviewed-by: Adrien Destugues <pulkomandy@gmail.com>

intel_extreme: fix PLL limits again

In hrev53618 I swapped both the LVDS and SVDO limits for i9xx to be in
the same order (always use "min" for the smallest value and "max" for
the largest, both for dividers and multipliers). But I missed the fact
that P2 is not searched for values in the range as are the other
parameters.

So, the code that picks the appropriate P2 value needs to be adjusted
accordingly. Now that this is clear, put the values always in the same
order (smallest value in "min", largest value in "max") and adjust the
code to comute P2.

Fixes #15573.

intel_extreme: Fix swapping of p2 values for 9xx cards

This would lead to no valid PLL combination being found, and
uninitialized stack memory eventually used to set the PLL. Add a memset
and a debugger() call to make this easier to notice.

Should fix #14368

Change-Id: Iff307439dc82a8b81bb46c1b73b63c21ee1c8279
Reviewed-on: https://review.haiku-os.org/c/haiku/+/1898
Reviewed-by: Adrien Destugues <pulkomandy@gmail.com>

intel_extreme: fix PLL limits for G4x

As for other devices, N=1 makes no sense because N-2 is eventually
written to the hardware register, so wherever these values come from,
they can't be correct. Replace with the values from the Intel manual.

Also fix confusion as to when the + 2 or - 2 is applied to M1 and M2
values. The documentation says M1+2 and M2+2 are used in frequency
computations, but we instead write M1-2 and M2-2 to the registers, so
the M1 and M2 in our limit structs has an offset of 2 from the docs.

Should fix #13694.

Change-Id: I87157154d22a5e6caf622d71a2f0e0b9ff21a2fa
Reviewed-on: https://review.haiku-os.org/c/haiku/+/1902
Reviewed-by: waddlesplash <waddlesplash@gmail.com>

Rework PLL calculations for Iron Lake

The limits were wrong in several places. Checked the sandy bridge, ivy
brige and haswell docs, they all say mostly the same.

- The value of p2 is either 7, 14, 5 or 10 depending on 1 bit in the
config register and on the display type. We can guess which values are
right according to the global P limit (5-80 when using 5/10,
28-something when using 14/7). The values are different because CRT
need a precise, but rather low pixel clock, while modern display
interface can accomodate being faster than required by a few MHz, but
need a much higher speed (the bits are transferred serially, so they
need to be at least 8 times faster than a DAC).

- The limits for N were obviously wrong, as the register is written with
N-2, so values less than 2 make no sense. Use 3-8 as specified in the
datasheet.

- The reference frequency (set by the driver) was wrong, too. It is
120MHz, not 96. It is 100MHz in some cases (FDI, etc), we should see
when this happens and switch to the right reference for PLL
computations.

- There was an attempt to minimize the value of N (a powersaving effort,
I guess?), but it would basically force the loop to stop at the first
value of N tested, resulting in way off timings in some cases.

- To ease testing and stop sending patches and syslogs back and forth
with vidrep, extract the "test mode" from pll.cpp into a proper test
executable, making it a little easier to experiment with the code and
fix the problems.

This should fix #13669 and possibly other cases of "out of range", black
screen, bad timings, etc.

Change-Id: Ic4c1c159701f352b7c1ef15a647f023c82ac26c
Reviewed-on: https://review.haiku-os.org/360
Reviewed-by: Axel Dörfler <axeld@pinc-software.de>
Reviewed-by: waddlesplash <waddlesplash@gmail.com>

Restore PLL limits for old 85x devices.

These went lost in driver refactoring, and the limits for 9xx were used
instead.

Should help with #13535.

intel_extreme: IronLake reference clock activation

intel_extreme: Improve PCH detection

* Detect PCH model based on ISA bridge and save
into shared info for later use.
* On CougarPoint PCH systems, assign pipes via
special CPT registers
* Drop HasPlatformControlHub as PCH should be
based on more than just generation.

intel_extreme: Fix PLL calculation on g4x and later

intel_extreme: Introduce PLL simulation mode

* Intel extreme PLL calculations are insane at times
* This code allows us to simulate PLL calculations on
cards without the real hardware.

intel_extreme: Rework PLL calculation

* More like linux, improved G4x calculations
* Reduce un-needed pll limit complexity
* Improved pll limits on ports based on type

intel_extreme: Fix LVDS pll DAC timing

pll: Cleanup PLL post dividers, add VLV and CHV limits

intel_extreme: Rework PLL and id PineView as PIN

intel_extreme: Tweak pll limits on 9xx

intel-extreme: Fix N pll limits on 9xx

intel_extreme: Program more LVDS regs. Set +/- @ lvds port

intel_extreme: tracing cleanup; no functional change

intel_extreme: Rework card identification defines

* Be more verbose on flag type
* Add additional groups
* Add additional families
* Correctly assign later models

intel_extreme: Start doing mode-setting at port level

* I really hope we can kill head_mode some day
* Break pll code out from mode code
* The LVDS and Digital are smooshed together and
likely need broken apart.