intel_extreme: added more pipeC support, fixes for eDP on DDI systems

intel_extreme: Sandy/IvyBridge fix 4 lanes DP detect, fully pgm eDP link

intel_extreme: decoupled PIPE/eDP link programming from FDI train, fixed eDP pgm error.

intel_extreme:DP links on sky- upto/incl coffeelake are now done (refclk detection added)

intel_extreme: skylake PLL works, all outputs fully functional.

intel_extreme: add haswell/skylake PLL calcs, no functional change yet.

intel_extreme: displayport now scales to BIOS set mode.

intel driver: added panelfitter pgmming.

intel_extreme: use the panel fitter for generation 4 devices

LVDS panels must really be driven at their native resolution, otherwise
they will simply not work. This means we should basically never touch
the video timings on that side. We need to only set the source size in
the pipe configuration, and let the panel fitter figure out the scaling.

On my G45 laptop, this allows me to use non-native resolutions on the
laptop display. This also means when booting with a VGA display
connected, I do get a valid display on the internal panel (using the VGA
resolution). VGA still gets "out of range", so we're still not setting
up something there.

If I switch to VGA display in the BIOS, I get a working picture there
and garbage on the internal display, which is progress (before I would
get a black screen on the internal display)

Fixes #12723.

intel_extreme: Add general pipe configuration and adjust color space

intel_extreme: Move rest of pipe control into pipe class

intel_extreme: Fix i965 LVDS panel programming

* polarity regs move on LVDS vs analog
* add knowledge or transcoder registers, they
exist seperately on PCH-split
* Native resolutions now work on LVDS under i965

intel_extreme: Don't store pipes within ports

* Store pipes within accelerant, and tell ports
about them.
* Rebrand DisplayPipe class to Pipe