| #
629f071b |
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27-Feb-2024 |
X512 <danger_mail@list.ru> |
pci: extend MSI interrupt vector number to 32 bits
Also increase MSI message data size to 32 bits according to PCIe spec.
Remove 0xff check for MSI interrupts because it is potentially valid
interrupt vector number. Reject 0xff only for legacy pin interrupts.
- MSI-X supports up to 2048 interrupts per device that do not fit to
`uint8`.
- Non-x86 systems may use separate interrupt vector ranges for
hard-wired interrupts and MSI interrupts so `uint8` is not enough to
represent all of them.
Change-Id: Iaf9ffb197ec23db0f97ffe3ea756d28d7bfc8705
Reviewed-on: https://review.haiku-os.org/c/haiku/+/7433
Reviewed-by: waddlesplash <waddlesplash@gmail.com>
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
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| #
e942269a |
|
12-Dec-2022 |
X512 <danger_mail@list.ru> |
pci: generic MSI interrupts support
Change-Id: Ib4fd23f6bca867a2b428bf2651234d719ee08672
Reviewed-on: https://review.haiku-os.org/c/haiku/+/6221
Reviewed-by: waddlesplash <waddlesplash@gmail.com>
Reviewed-by: Adrien Destugues <pulkomandy@pulkomandy.tk>
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| #
66395144 |
|
19-Dec-2013 |
Pawel Dziepak <pdziepak@quarnos.org> |
x86[_64]: Support assigning MSI IRQs to arbitrary CPU
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| #
46f7a54d |
|
26-Jul-2013 |
Jérôme Duval <jerome.duval@gmail.com> |
MSI: Use the effective APIC id of the boot CPU for the address destination.
* This should only affect systems where the CPU ids aren't sequential (mostly
non Intel).
* Fixes #9807.
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| #
33fbe254 |
|
13-Apr-2010 |
Michael Lotz <mmlr@mlotz.ch> |
* Add code to allocate and free interrupt vectors for message signaled
interrupts (MSI).
* Add the remaining IDT entries and redirection functions in the interrupt code.
* Make the PIC end_of_interrupt() return a result to indicate whether the vector
was handled by this PIC. If it isn't we now issue a apic_end_of_interrupt()
in the assumption of apic local interrupt, MSI or IPI. This also removes
the need for the gUsingIOAPIC global and doing manual apic_end_of_interrupt()
calls in the SMP and timer code.
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@36221 a95241bf-73f2-0310-859d-f6bbb57e9c96
|
| #
663951443784bb63d60abe742f1d1379fb153e18 |
|
19-Dec-2013 |
Pawel Dziepak <pdziepak@quarnos.org> |
x86[_64]: Support assigning MSI IRQs to arbitrary CPU
|
| #
46f7a54d8c545ff61d59d6b336232d2b65c3b1fd |
|
26-Jul-2013 |
Jérôme Duval <jerome.duval@gmail.com> |
MSI: Use the effective APIC id of the boot CPU for the address destination.
* This should only affect systems where the CPU ids aren't sequential (mostly
non Intel).
* Fixes #9807.
|
| #
33fbe254964dff2c8b8a3e1522bbefff14d51ea1 |
|
13-Apr-2010 |
Michael Lotz <mmlr@mlotz.ch> |
* Add code to allocate and free interrupt vectors for message signaled
interrupts (MSI).
* Add the remaining IDT entries and redirection functions in the interrupt code.
* Make the PIC end_of_interrupt() return a result to indicate whether the vector
was handled by this PIC. If it isn't we now issue a apic_end_of_interrupt()
in the assumption of apic local interrupt, MSI or IPI. This also removes
the need for the gUsingIOAPIC global and doing manual apic_end_of_interrupt()
calls in the SMP and timer code.
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@36221 a95241bf-73f2-0310-859d-f6bbb57e9c96
|