kernel/x86: add a hybrid type per cpu, to be dumped when the feature exists.

for AlderLake CPUs

Change-Id: I4beba04e3ac95d7564684ee86de99c894b57a15c
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5988
Reviewed-by: waddlesplash <waddlesplash@gmail.com>
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>

kernel: load cpu amd microcode update if loaded by the bootloader

we detect basically the cpu info before loading the microcode,
to be able to detect the vendor, and avoid any update on hypervisor.

I couldn't test because my cpu doesn't have any update available.

Change-Id: I6aea830158423b3ee13b640be8a788fc9041e23c
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5859
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
Reviewed-by: Jérôme Duval <jerome.duval@gmail.com>

amd_pstates: introduce a AMD P-states driver for Ryzen with the CPPC feature

tested on Zen2 (Ryzen 3 5300U)
This support was submitted in October for inclusion in Linux.
Haiku supports only two profiles. We could probably add some more, and let the driver says which it supports.

Change-Id: Id7754b445bc32a691d58a1e4af630351562abc22
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5826
Reviewed-by: waddlesplash <waddlesplash@gmail.com>
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>

kernel/x86: init the tsc frequency and clock speed from MSR when available

only for AMD newer CPUs. tested on R5300U

Change-Id: I44be2efca37b1738a759a15140e5fd8d3b5ac7b0
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5804
Reviewed-by: Jérôme Duval <jerome.duval@gmail.com>

kernel/x86_64: configure LFENCE as a serializing instruction on AMD

Change-Id: I152bf41c3479f81fc458abdf8d89874ffa3a08d7
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5691
Reviewed-by: Jérôme Duval <jerome.duval@gmail.com>

kernel/x86: rework get_frequency_for

we don't sample if the last sample is too recent and use the cached result.

Change-Id: I17ed29bda7fe7276f1a4148b3e1985c9d32ae032
Reviewed-on: https://review.haiku-os.org/c/haiku/+/4101
Reviewed-by: Jérôme Duval <jerome.duval@gmail.com>
Reviewed-by: Adrien Destugues <pulkomandy@gmail.com>

x86_64: fix build

This code was accidentally removed but is still needed.

Fix definition of PAGESIZE and B_PAGE_SIZE

On sparc, the minimal page size we can use is 8K. Since B_PAGE_SIZE and
PAGESIZE defines were hardcoded to 4K, this resulted in a lot of
confusion in all code trying to manipulate pages.

- Remove cpu.h from headers/private/kernel/arch/*. It dates back from
NewOS and was not used anymore since our kernel uses B_PAGE_SIZE
(PAGE_SIZE was the only thing defined in this header).
- Add posix/arch/*/limits.h with the arch specific page size and include
it from the main limits.h.
- Adjust bios_ia32/debug.cpp which was the only place using the
PAGE_SIZE constant from the deleted headers.
- Change OS.h to define B_PAGE_SIZE to be the same as POSIX PAGESIZE.
- Define PAGESIZE in the build header if the host OS doesn't.

Change-Id: I8c3732cf952ea3c2f088aa16d216678fbf198b96
Reviewed-on: https://review.haiku-os.org/c/haiku/+/3558
Reviewed-by: Adrien Destugues <pulkomandy@gmail.com>

kernel/x86: extend CR4 flags

Change-Id: I4861f6cd61d0daeeb2403d07e703b83cd6a00666
Reviewed-on: https://review.haiku-os.org/c/haiku/+/3280
Reviewed-by: Rene Gollent <rene@gollent.com>

x86: identify Hygon vendor

it's a Zen-based CPU: rely on AMD support code.

Change-Id: Ia980a42457575bf8d1130d813310a285bf137691
Reviewed-on: https://review.haiku-os.org/c/haiku/+/3217
Reviewed-by: Adrien Destugues <pulkomandy@gmail.com>

kernel/x86: add MSR for HWP and extended CR0 flags

Change-Id: I9e5d5421dabbdf7d4ecf6334509178f8f892591f
Reviewed-on: https://review.haiku-os.org/c/haiku/+/3215
Reviewed-by: Jérôme Duval <jerome.duval@gmail.com>

kernel/x86: detect power subfeatures

Change-Id: Id159f0d7fc7816b6a40b9cf28f53dfdbebd04a73
Reviewed-on: https://review.haiku-os.org/c/haiku/+/3211
Reviewed-by: Axel Dörfler <axeld@pinc-software.de>

kernel/x86: Enable machine check exceptions if supported.

This enables generation of exceptions that are due to uncorrected
hardware errors. The exception handlers were already in place and will
now actually trigger kernel panics.

Note that this is the simplest form of MCE "handling" and does not add
anything of the broader machine check architecture (MCA) that also allow
reporting of corrected errors. As MCEs are generally hard to decode due
to their hardware specifity, this merely makes such problems more
obvious.

Might help to discern hardware issues in cases that would otherwise just
triple fault and cause a reboot.

Change-Id: I9e3a2640458f7c562066478d0ca90e3a46c3a325
Reviewed-on: https://review.haiku-os.org/c/haiku/+/3155
Reviewed-by: waddlesplash <waddlesplash@gmail.com>
Reviewed-by: Axel Dörfler <axeld@pinc-software.de>

efi: Refactor CPU code to be arch-specific

* Migrate some platform agnostic architecture code into
boot/arch from efi/arch. This helps to avoid conflicts
between kernel and boot sources as well.
* Conflicts between arch_cpu in efi and kernel code means
bootcode really should *never* directly use kernel arch
headers. (other platforms don't, which is why they don't
have this same issue)
* We carefully thread any needed kernel headers (namely
assembly helper macros) into the bootloader headers without
mixing in the whole conflicting kernel/arch headers.
* ARM now properly get its cpu init code called, and we
progress further into the EFI bootloader.

Change-Id: If67ec9758b5ce68563ebd9eb45d5196401911c67
Reviewed-on: https://review.haiku-os.org/c/haiku/+/2975
Reviewed-by: waddlesplash <waddlesplash@gmail.com>

kernel/x86_64: AVX support

xsave or xsavec are supported.
breaks vregs compatibility.
change the thread structure object cache alignment to 64
the xsave fpu_state size isn't defined, it is for instance 832 here, thus I picked 1024.

Change-Id: I4a0cab0bc42c1d37f24dcafb8259f8ff24a330d2
Reviewed-on: https://review.haiku-os.org/c/haiku/+/2849
Reviewed-by: Adrien Destugues <pulkomandy@gmail.com>

kernel/x86: detect xsave subfeatures

Change-Id: Ida635441faaea4fb060e9f77ca3f4f167dc4bfe4
Reviewed-on: https://review.haiku-os.org/c/haiku/+/2617
Reviewed-by: Adrien Destugues <pulkomandy@gmail.com>

kernel: load cpu microcode update if loaded by the bootloader

add optional fields for microcode in kernel_args.

Change-Id: Ic5fb54cf6c9f489a2d1cdda00f63980c11dcdaeb
Reviewed-on: https://review.haiku-os.org/c/haiku/+/2264
Reviewed-by: Adrien Destugues <pulkomandy@gmail.com>

kernel/x86: add a compiler level memory barrier to wbinvd

Change-Id: Id96e37b83110f413a2b30f2967921ce90f31dd94
Reviewed-on: https://review.haiku-os.org/c/haiku/+/2272
Reviewed-by: Adrien Destugues <pulkomandy@gmail.com>

kernel/x86: stores cpu number in TSC_AUX if rdtscp is available

On modern x86, one can use __rdtscp to get the current cpu in userland.

Change-Id: I1767e379606230a75e4622637c7a5aed9cdf9ab0
Reviewed-on: https://review.haiku-os.org/c/haiku/+/2248
Reviewed-by: Adrien Destugues <pulkomandy@gmail.com>

kernel: x86: add some more cpuid flags.

Change-Id: If81c8e38c4e5a8347b5818440a7516298be585bc
Reviewed-on: https://review.haiku-os.org/c/haiku/+/2242
Reviewed-by: Jérôme Duval <jerome.duval@gmail.com>

kernel/x86_64: Add errata patching.

The patched errata are only the AMD ones FreeBSD patches
(it seems there are no Intel errata that can be patched
this way, they are all in microcode updates ... or can't
be patched in the CPU at all.)

This also seems to be roughly the point in the boot that
FreeBSD patches these, too, despite how "critical" some
of them seem.

Change-Id: I9065f8d025332418a21c2cdf39afd7d29405edcc
Reviewed-on: https://review.haiku-os.org/c/haiku/+/1740
Reviewed-by: Jessica Hamilton <jessica.l.hamilton@gmail.com>

kernel/x86: additional msr and cpuid items

Adds SSBD and L1TF related items

Change-Id: Iccea2bb9e057e0d011a18609212f175f9b5e678d
Reviewed-on: https://review.haiku-os.org/825
Reviewed-by: Adrien Destugues <pulkomandy@pulkomandy.tk>

Revert team and thread changes for COMPAT_MODE (hrev52010 & hrev52011).

This reverts commit c558f9c8fe54bc14515aa62bac7826271289f0e4.
This reverts commit 44f24718b1505e8d9c75e00e59f2f471a79b5f56.
This reverts commit a69cb330301c4d697daae57e6019a307f285043e.
This reverts commit 951182620e297d10af7fdcfe32f2b04d56086ae9.

There have been multiple reports that these changes break mounting NTFS partitions
(on all systems, see #14204), and shutting down (on certain systems, see #12405.)
Until they can be fixed, they are being backed out.

kernel/x86_64: add compatibility source files to the build.

* add x86 versions of fnsave frstor.
* add missing declaration for elf32_resolve_symbol().

How-to build a x86_64/x86 bootstrap build:
mkdir generated_bootstrap; cd generated_bootstrap
../configure --bootstrap /dir/to/haikuporter/haikuporter /dir/to/haikuports.cross \
/dir/to/haikuports --build-cross-tools x86_64 /dir/to/buildtools --build-cross-tools x86 -j8 --use-gcc-pipe
jam -q -sHAIKU_PORTER_EXTRA_OPTIONS="-j8 --sourceforge-mirror=freefr --no-source-packages" @bootstrap-raw

Change-Id: I6eae3653c42a53683ae307107fae595c4b8ebcfb

kernel: x86: add some msr and cpuid features

* for arch capabilities.
* for spec ctrl and pred cmd.

kernel: support for Intel SMAP and SMEP on x86_64.

SMAP will generated page faults when the kernel tries to access user pages unless overriden.
If SMAP is enabled, the override instructions are written where needed in memory with
binary "altcodepatches".
Support is enabled by default, might be disabled per safemode setting.

Change-Id: Ife26cd765056aeaf65b2ffa3cadd0dcf4e273a96

kernel: x86: add some more cpuid flags.

kernel: x86: add cpuid feature 7 flags.

x86: added a MSR definition.

x86: added two MSR definitions.

kernel/x86_64: save fpu state at interrupts

The kernel is allowed to use fpu anywhere so we must make sure that
user state is not clobbered by saving fpu state at interrupt entry.
There is no need to do that in case of system calls since all fpu
data registers are caller saved.

We do not need, though, to save the whole fpu state at task swich
(again, thanks to calling convention). Only status and control
registers are preserved. This patch actually adds xmm0-15 register
to clobber list of task swich code, but the only reason of that is
to make sure that nothing bad happens inside the function that
executes that task swich. Inspection of the generated code shows
that no xmm registers are actually saved.

Signed-off-by: Paweł Dziepak <pdziepak@quarnos.org>

boot/x86_64: enable sse early

Enable SSE as a part of the "preparation of the environment to run any
C or C++ code" in the entry points of stage2 bootloader.

SSE2 is going to be used by memset() and memcpy().

Signed-off-by: Paweł Dziepak <pdziepak@quarnos.org>

kernel/x86[_64]: remove get_optimized_functions from cpu modules

The possibility to specify custom memcpy and memset implementations
in cpu modules is currently unused and there is generally no point
in such feature.

There are only 2 x86 vendors that really matter and there isn't
very big difference in performance of the generic optmized versions
of these funcions across different models. Even if we wanted different
versions of memset and memcpy depending on the processor model or
features much better solution would be to use STT_GNU_IFUNC and save
one indirect call.

Long story short, we don't really benefit in any way from
get_optimized_functions and the feature it implements and it only adds
unnecessary complexity to the code.

Signed-off-by: Paweł Dziepak <pdziepak@quarnos.org>

kernel/x86_64: implement x86_swap_pgdir in C++

No reason not to inline this function.

Signed-off-by: Paweł Dziepak <pdziepak@quarnos.org>

kernel/x86_64: inline x86_{read, write}_msr()

This patch makes it possible to inline rdmsr and wrmsr instruction. The
performance impact shouldn't be significant since they are used relatively
rarely and wrmsr is usually a serializing instruction, but there is no reason
not to do so.

kernel/x86_64: improve context switch implementation

The goal of this patch is to amortize the cost of context switch by making
the compiler aware that context switch clobbers all registers. Because all
register need to be saved anyway there is no additional cost of using
callee saved register in the function that does the context switch.

x86: Implement multicast ICIs

x86: Let each CPU have its own GDT

kernel: Reduce lock contention when processing ICIs

kernel: Rework cpuidle module

* Create new interface for cpuidle modules (similar to the cpufreq
interface)
* Generic cpuidle module is no longer needed
* Fix and update Intel C-State module

kernel: Make CACHE_LINE_ALIGN visible in the whole kernel

kernel: Add cpufreq module for Intel P-states

Since Sandy Bridge managing P-states on Intel processors is much easier
and more powerful than when using previous versions of EIST.

x86[_64]: Add CPU cache topology detection for AMD and Intel CPUs

Added x2APIC support.

* Mostly useful for virtualization at the moment. Works in QEmu.
* Can be enabled by safemode settings/menu.
* Please note that x2APIC normally requires use of VT-d interrupt remapping feature
on real hardware, which we don't support yet.

x86: enable data execution prevention

Set execute disable bit for any page that belongs to area with neither
B_EXECUTE_AREA nor B_KERNEL_EXECUTE_AREA set.

In order to take advanage of NX bit in 32 bit protected mode PAE must be
enabled. Thus, from now on it is also enabled when the CPU supports NX bit.

vm_page_fault() takes additional argument which indicates whether page fault
was caused by an illegal instruction fetch.

x86: Initialize IA32_MSR_ENERGY_PERF_BIAS

The lowest 4 bits of the MSR serves as a hint to the hardware to
favor performance or energy saving. 0 means a hint preference for
highest performance while 15 corresponds to the maximum energy
savings. A value of 7 translates into a hint to balance performance
with energy savings.

The default reset value of the MSR is 0. If BIOS doesn't intialize
the MSR, the hardware will run in performance state. This patch
initialize the MSR with value of 7 for balance between performance
and energy savings

Signed-off-by: Fredrik Holmqvist <fredrik.holmqvist@gmail.com>

Cleaner separation of 32-/64-bit specific CPU/interrupt code.

Renamed {32,64}/int.cpp to {32,64}/descriptors.cpp, which now contain
functions for GDT and TSS setup that were previously in arch_cpu.cpp,
as well as the IDT setup code. These get called from the init functions
in arch_cpu.cpp, rather than having a bunch of ifdef'd chunks of code
for 32/64.

Implemented user debugging support for x86_64.

Reused x86 arch_user_debugger.cpp, with a few minor changes to make
the code work for both 32 and 64 bit. Something isn't quite working
right, if a breakpoint is hit the kernel will hang. Other than that
everything appears to work correctly.

Initial userland support for x86_64.

Userland switch is implemented, as is basic system call support (using
SYSCALL/SYSRET). The system call handler is not yet complete: it doesn't
handle more than 6 arguments, and does not perform all the necessary kernel
entry/exit work (neither does the interrupt handler). However, this is
sufficient for runtime_loader to start and print some debug output.

Moved the exception handling functions to arch_int.cpp, shared between x86 and x86_64.

Moved the 32-bit page fault handler to arch_int.cpp, use it for x86_64.

A proper page fault handler was required for areas that were not locked
into the kernel address space. This enables the boot process to get
up to the point of trying to find the boot volume.

Implemented threading for x86_64.

* Thread creation and switching is working fine, however threads do not yet
get interrupted because I've not implemented hardware interrupt handling
yet (I'll do that next).
* I've made some changes to struct iframe: I've removed the e/r prefixes
from the member names for both 32/64, so now they're just named ip, ax,
bp, etc. This makes it easier to write code that works with both 32/64
without having to deal with different iframe member names.

Renamed remaining i386_* functions to x86_* for consistency.

Implemented system_time() for x86_64.

* Uses 64-bit multiplication, special handling for CPUs clocked < 1 GHz
in system_time_nsecs() not required like on x86.
* Tested against a straight conversion of the x86 version, noticably
faster with a large number of system_time() calls.

Added arch_cpu.cpp to the x86_64 build.

* Some things are currently ifndef'd out completely for x86_64 because
they aren't implemented, there's a few other ifdef's to handle x86_64
differences but most of the code works unchanged.
* Renamed some i386_* functions to x86_*.
* Added a temporary method for setting the current thread on x86_64
(a global variable, not SMP safe). This will be changed to be done
via the GS segment but I've not implemented that yet.

x86_{read,write}_cr{0,4} can just be implemented as macros, put an x86_ prefix on the other read/write macros for consistency.

Merged x86_64 headers into x86 headers.

Not many changes seeing as there's not much x86_64 stuff done yet. Small
differences are handled with ifdefs, large differences (descriptors.h,
struct iframe) have separate headers under arch/x86/32 and arch/x86/64.

Moved the common parts of arch_cpu.h between x86 and x86_64 to arch/common_x86/cpu.h.

x86: add cpuid feature 6 flags

Signed-off-by: Fredrik Holmqvist <fredrik.holmqvist@gmail.com>

x86: AMD C1E with no ARAT(Always Running APIC Timer) idle support

AMD C1E is a BIOS controlled C3 state. Certain processors families
may cut off TSC and the lapic timer when it is in a deep C state,
including C1E state, thus the cpu can't be waken up and system will hang.

This patch firstly adds the support of idle selection during boot. Then
it implements amdc1e_noarat_idle() routine which checks the MSR which
contains the C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27) before
executing the halt instruction, then clear them once set.

However intel C1E doesn't has such problem. AMD C1E is a BIOS controlled
C3 state. The difference between C1E and C3 is that transition into C1E
is not initiated by the operating system. System will enter C1E state
automatically when both cores enters C1 state. As for intel C1E, it
means "reduce CPU voltage before entering corresponding Cx-state".

This patch may fix #8111, #3999, #7562, #7940 and #8060

Copied from the description of #3999:
>but for some reason I hit the power button instead of the reset one. And
>the boot continued!!
The reason is CPUs are waken up once power button is hit.

Signed-off-by: Fredrik Holmqvist <fredrik.holmqvist@gmail.com>

x86: Change cpu feature flags to shifts

* No functional change
* Added missing ia64 emulation flag
* More closely matches AMD_EXT defines
* Easier to read compared to CPU documentation

kernel: x86 SSE improvements

* Prepend x86_ to non-static x86 code
* Add x86_init_fpu function to kernel header
* Don't init fpu multiple times on smp systems
* Verified fpu is still started on smp and non-smp
* SSE code still generates general protection faults
on smp systems though

kernel: Fix FPU SSE + MMX instruction usage.

* Rename init_sse to init_fpu and handle FPU setup.
* Stop trying to set up FPU before VM init.
We tried to set up the FPU before VM init, then
set it up again after VM init with SSE extensions,
this caused SSE and MMX applications to crash.
* Be more logical in FPU setup by detecting CPU flag prior
to enabling FPU. (it's unlikely Haiku will run on
a processor without a fpu... but lets be consistant)
* SSE2 gcc code now runs (faster even) without GPF
* tqh confirms his previously crashing mmx code now works
* The non-SSE FPU enable after VM init needs tested!

added more cpu feature flags for x86


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42263 a95241bf-73f2-0310-859d-f6bbb57e9c96

Merged signals-merge branch into trunk with the following changes:
* Reorganized the kernel locking related to threads and teams.
* We now discriminate correctly between process and thread signals. Signal
handlers have been moved to teams. Fixes #5679.
* Implemented real-time signal support, including signal queuing, SA_SIGINFO
support, sigqueue(), sigwaitinfo(), sigtimedwait(), waitid(), and the addition
of the real-time signal range. Closes #1935 and #2695.
* Gave SIGBUS a separate signal number. Fixes #6704.
* Implemented <time.h> clock and timer support, and fixed/completed alarm() and
[set]itimer(). Closes #5682.
* Implemented support for thread cancellation. Closes #5686.
* Moved send_signal() from <signal.h> to <OS.h>. Fixes #7554.
* Lots over smaller more or less related changes.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42116 a95241bf-73f2-0310-859d-f6bbb57e9c96

Definition for CR4 PAE bit.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@37073 a95241bf-73f2-0310-859d-f6bbb57e9c96

x86:
* Renamed i386_context_switch() to x86_context_switch().
* x86_context_switch() no longer sets the page directory.
arch_thread_context_switch() does that explicitly, now. This allows to solve
the TODO by reordering releasing the previous paging structures reference and
setting the new page directory.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@37024 a95241bf-73f2-0310-859d-f6bbb57e9c96

Renamed i386_swap_pgdir() to x86_swap_pgdir.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@37023 a95241bf-73f2-0310-859d-f6bbb57e9c96

x86:
* Renamed vm_translation_map_arch_info to X86PagingStructures, and all
members and local variables of that type accordingly.
* arch_thread_context_switch(): Added TODO: The still active paging structures
can indeed be deleted before we stop using them.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@37022 a95241bf-73f2-0310-859d-f6bbb57e9c96

* First run through the kernel's private parts to use phys_{addr,size}_t
where appropriate.
* Typedef'ed page_num_t to phys_addr_t and used it in more places in
vm_page.{h,cpp}.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@36937 a95241bf-73f2-0310-859d-f6bbb57e9c96

x86:
Added fields for temporary storage of the debug registers dr6 and dr7 to the
arch_cpu_info structure. The actual registers are stored at the beginning of
x86_exit_user_debug_at_kernel_entry() and read in
x86_handle_debug_exception().
The problem was that x86_exit_user_debug_at_kernel_entry() itself overwrote
dr7 and, if kernel breakpoints were enabled, dr6 could be overwritten anytime
after. So x86_handle_debug_exception() would find incorrect values in the
registers (definitely in dr7) and thus interpret the detected debug condition
incorrectly. Usually watchpoints were recognized as breakpoints.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@35951 a95241bf-73f2-0310-859d-f6bbb57e9c96

* map_physical_memory() does now always set a memory type. If none is given (it
needs to be or'ed to the address specification), "uncached" is assumed.
* Set the memory type for the "BIOS" and "DMA" areas to write-back. Not sure, if
that's correct, but that's what was effectively used on my machines before.
* Changed x86_set_mtrrs() and the CPU module hook to also set the default memory
type.
* Rewrote the MTRR computation once more:
- Now we know all used memory ranges, so we are free to extend used ranges
into unused ones in order to simplify them for MTRR setup.
- Leverage the subtractive properties of uncached and write-through ranges to
simplify ranges of any other respectively write-back type.
- Set the default memory type to write-back, so we don't need MTRRs for the
RAM ranges.
- If a new range intersects with an existing one, we no longer just fail.
Instead we use the strictest requirements implied by the ranges. This fixes
#5383.

Overall the new algorithm should be sufficient with far less MTRRs than before
(on my desktop machine 4 are used at maximum, while 8 didn't quite suffice
before). A drawback of the current implementation is that it doesn't deal with
the case of running out of MTRRs at all, which might result in some ranges
having weaker caching/memory ordering properties than requested.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@35515 a95241bf-73f2-0310-859d-f6bbb57e9c96

Removed unused <arch>_switch_stack_and_call() and
arch_thread_switch_kstack_and_call().


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@34971 a95241bf-73f2-0310-859d-f6bbb57e9c96

Added type nanotime_t (an int64 storing a nanoseconds value) and function
system_time_nsecs(), returning the system time in nanoseconds. The function
is only really implemented for x86. For the other architectures
system_time() * 1000 is returned.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@34543 a95241bf-73f2-0310-859d-f6bbb57e9c96

* Added a set_mtrrs() hook to x86_cpu_module_info, which is supposed to set
all MTRRs at once.
* Added a respective x86_set_mtrrs() kernel function.
* x86 CPU module:
- Implemented the new hook.
- Prefixed most debug output with the CPU index. Otherwise it gets quite
confusing with multiple CPUs.
- generic_init_mtrrs(): No longer clear all MTRRs, if they are already
enabled. This lets us benefit from the BIOS's setup until we install our
own -- otherwise with caching disabled things are *really* slow.
* arch_vm.cpp: Completely rewrote the MTRR handling as the old one was not
only slow (O(2^n)), but also broken (resulting in incorrect setups (e.g.
with cachable ranges larger than requested)), and not working by design for
certain cases (subtractive setups intersecting ranges added later).
Now we maintain an array with the successfully set ranges. When a new range
is added, we recompute the complete MTRR setup as we need to. The new
algorithm analyzing the ranges has linear complexity and also handles range
base addresses with an alignment not matching the range size (e.g. a range
at address 0x1000 with size 0x2000) and joining of adjacent/overlapping
ranges of the same type.

This fixes the slow graphics on my 4 GB machine (though unfortunately the
8 MTRRs aren't enough to fully cover the complete frame buffer (about 35
pixel lines remain uncachable), but that can't be helped without rounding up
the frame buffer size, for which we don't have enough information). It might
also fix #1823.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@34197 a95241bf-73f2-0310-859d-f6bbb57e9c96

* Coding style cleanup, no functional change.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@33792 a95241bf-73f2-0310-859d-f6bbb57e9c96

* Renamed the ROUNDOWN macro to ROUNDDOWN. Also changed the implementation of
ROUNDUP to use '*' and '/' -- the compiler will optimize that for powers of
two anyway and this implementation works for other numbers as well.
* The thread::fault_handler use in C[++] code was broken with gcc 4. At least
when other functions were invoked. Trying to trick the compiler wasn't a
particularly good idea anyway, since the next compiler version could break
the trick again. So the general policy is to use the fault handlers only in
assembly code where we have full control. Changed that for x86 (save for the
vm86 mode, which has a similar mechanism), but not for the other
architectures.
* Introduced fault_handler, fault_handler_stack_pointer, and fault_jump_buffer
fields in the cpu_ent structure, which must be used instead of
thread::fault_handler in the kernel debugger. Consequently user_memcpy() must
not be used in the kernel debugger either. Introduced a debug_memcpy()
instead.
* Introduced debug_call_with_fault_handler() function which calls a function
in a setjmp() and fault handler context. The architecture specific backend
arch_debug_call_with_fault_handler() has only been implemented for x86 yet.
* Introduced debug_is_kernel_memory_accessible() for use in the kernel
debugger. It determines whether a range of memory can be accessed in the
way specified. The architecture specific back end
arch_vm_translation_map_is_kernel_page_accessible() has only been implemented
for x86 yet.
* Added arch_debug_unset_current_thread() (only implemented for x86) to unset
the current thread pointer in the kernel debugger. When entering the kernel
debugger we do some basic sanity checks of the currently set thread structure
and unset it, if they fail. This allows certain commands (most importantly
the stack trace command) to avoid accessing the thread structure.
* x86: When handling a double fault, we do now install a special handler for
page faults. This allows us to gracefully catch faulting commands, even if
e.g. the thread structure is toast.

We are now in much better shape to deal with double faults. Hopefully avoiding
the triple faults that some people have been experiencing on their hardware
and ideally even allowing to use the kernel debugger normally.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@32073 a95241bf-73f2-0310-859d-f6bbb57e9c96

More work towards making our double fault handler less triple fault prone:
* SMP:
- Added smp_send_broadcast_ici_interrupts_disabled(), which is basically
equivalent to smp_send_broadcast_ici(), but is only called with interrupts
disabled and gets the CPU index, so it doesn't have to use
smp_get_current_cpu() (which dereferences the current thread).
- Added cpu index parameter to smp_intercpu_int_handler().
* x86:
- arch_int.c -> arch_int.cpp
- Set up an IDT per CPU. We were using a single IDT for all CPUs, but that
can't work, since we need different tasks for the double fault interrupt
vector.
- Set the per CPU double fault task gates correctly.
- Renamed set_intr_gate() to set_interrupt_gate and set_system_gate() to
set_trap_gate() and documented them a bit.
- Renamed double_fault_exception() x86_double_fault_exception() and fixed
it not to use smp_get_current_cpu(). Instead we have the new
x86_double_fault_get_cpu() that deducts the CPU index from the used stack.
- Fixed the double_fault interrupt handler: It no longer calls int_bottom to
avoid accessing the current thread.
* debug.cpp:
- Introduced explicit debug_double_fault() to enter the kernel debugger from
a double fault handler.
- Avoid using smp_get_current_cpu().
- Don't use kprintf() before sDebuggerOnCPU is set. Otherwise
acquire_spinlock() is invoked by arch_debug_serial_puts().

Things look a bit better when the current thread pointer is broken -- we run
into kernel_debugger_loop() and successfully print the "Welcome to KDL"
message -- but we still dereference the thread pointer afterwards, so that we
don't get a usable kernel debugger yet.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@32050 a95241bf-73f2-0310-859d-f6bbb57e9c96

* Allocate a separate double fault stack for each CPU.
* Added x86_double_fault_get_cpu(), a save way to get the CPU index when in
the double fault handler. smp_get_current_cpu() requires at least a somewhat
intact thread structure, so we rather want to avoid it when handling a double
fault. There are a lot more of those dependencies in the KDL entry code.
Working on it...


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@32028 a95241bf-73f2-0310-859d-f6bbb57e9c96

Synchronize the TSCs of all CPUs early in the boot process, so system_time()
will return consistent values. This helps with debug measurements for the time
being. Obviously we'll have to think of something different when we support
speed-stepping on models with frequency-dependent TSCs.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@30287 a95241bf-73f2-0310-859d-f6bbb57e9c96

When switching to a kernel thread we no longer set the page directory.
This is not necessary, since userland teams' page directories also
contain the kernel mappings, and avoids unnecessary TLB flushes. To make
that possible the vm_translation_map_arch_info objects are reference
counted now.

This optimization reduces the kernel time of the Haiku build on my
machine with SMP disabled a few percent, but interestingly the total
time decreases only marginally. Haven't tested with SMP yet, but for
full impact CPU affinity would be needed.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@28287 a95241bf-73f2-0310-859d-f6bbb57e9c96

Moved definition of the PAUSE macro to <cpu.h>, respectively
<arch/cpu.h>.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@28221 a95241bf-73f2-0310-859d-f6bbb57e9c96

* Implemented x86 assembly version of memset().
* memset() is now available through the commpage.
* CPU modules can provide a model-optimized memset().


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@27952 a95241bf-73f2-0310-859d-f6bbb57e9c96

* Added acpi_shutdown() method. If the ACPI bus manager is installed, this will
be used now. Tested only with VMware so far.
* apm_shutdown() is now called with interrupts turned on.
* Renamed arch_cpu.c to arch_cpu.cpp.
* Minor cleanup.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@27404 a95241bf-73f2-0310-859d-f6bbb57e9c96

Added comment.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@26806 a95241bf-73f2-0310-859d-f6bbb57e9c96

* Introduced x86_get_double_fault_stack(), which returns the address
and size of the double fault stack.
* is_kernel_stack_address() does now also check whether the given
address is on the double fault stack. This fixes stack traces on
double faults, which were broken (i.e. went only to the double fault
iframe) since we started checking whether the addresses are on the
kernel stack at all.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@26775 a95241bf-73f2-0310-859d-f6bbb57e9c96

* Removed the feature_string from the cpu_ent structure.
* Dumping the features as string is now a one time thing, that only happens
when DUMP_FEATURE_STRING is defined to 1.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@26733 a95241bf-73f2-0310-859d-f6bbb57e9c96

Last patch of the vm86 patch series from Jan Klötzke - thanks!:
* The new function vm86_do_int(struct vm86_state *state, uint8 vec) provides a
facility to call BIOS interupt handlers. The function must only be called from
a user thread context because the lower 1MB of the address space is used.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@25610 a95241bf-73f2-0310-859d-f6bbb57e9c96

Patch by Jan Klötzke:
* In vm86 mode CS will have arbitrary values so we check for both USER_CODE_SEG
and the VM flag in EFLAGS. This is also done when entering interrupt gates.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@25607 a95241bf-73f2-0310-859d-f6bbb57e9c96

- Added support in system info for extended cpu family and model.
- Take extended family and model into account when generating the cpu
type and revision.
- Added Intel Core 2 Extreme to the cpu list.

Please review.



git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@24509 a95241bf-73f2-0310-859d-f6bbb57e9c96

Merged branch haiku/branches/developer/bonefish/optimization revision
23139 into trunk, with roughly the following changes (for details svn
log the branch):
* The int 99 syscall handler is now fully in assembly.
* Added a sysenter/sysexit handler and use it on Pentiums that support
it (via commpage).
* Got rid of i386_handle_trap(). A bit of functionality was moved into
the assembly handler which now uses a jump table to call C functions
handling the respective interrupt.
* Some optimizations to get user debugger support code out of the
interrupt handling path.
* Introduced a thread::flags fields which allows to skip handling of
rare events (signals, user debug enabling/disabling) on the
common interrupt handling path.
* Got rid of the explicit iframe stack. The iframes can still be
retrieved by iterating through the stack frames.
* Made the commpage an architecture independent feature. It's used for
the real time data stuff (instead of creating a separate area).
* The x86 CPU modules can now provide processor optimized versions for
common functions (currently memcpy() only). They are used in the
kernel and are provided to the userland via commpage entries.
* Introduced build system feature allowing easy use of C structure
member offsets in assembly code.

Changes after merging:
* Fixed merge conflict in src/system/kernel/arch/x86/arch_debug.cpp
(caused by refactoring and introduction of "call" debugger command).



git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@23370 a95241bf-73f2-0310-859d-f6bbb57e9c96

clean up TSS initialization.

Now two complete tss structures exist within the per-cpu structure. Instead
of having to create a seperate area per each one, initialize them in place.
Also, the old mechanism to getting all of the cpus to get initialized was
subtly broken, but still managed to work. Now, just force all the cpus to
initialize at boot, which makes the actual swapping of esp0 somewhat simpler.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@20131 a95241bf-73f2-0310-859d-f6bbb57e9c96

pulled over some stuff from newos:
at boot, per cpu, detect the cpu, pull down all the relevant cpuid bits and
save them into the per-cpu structure. Changed most of the code scattered here
and there that reads the cpuid to use a new api, x86_check_feature, which looks
at the saved bits.
Also changed the system_info stuff to read from these bits.
While i was at it, refreshed all the bits to be current.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@20072 a95241bf-73f2-0310-859d-f6bbb57e9c96

Applied patch by Vasilis Kaoutsis: now checks for the MSR feature as well; obviously
some Pentium 200 MMX pretend to support MTRRs.
This should fix bug #553.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@19899 a95241bf-73f2-0310-859d-f6bbb57e9c96

Didn't notice that x86_enter_userspace() also copied the thread entry's arguments to
the userland stack in an unsafe way - moved that stuff to arch_thread_enter_userspace(), too.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@19778 a95241bf-73f2-0310-859d-f6bbb57e9c96

* There was no reason to copy the "userland calls exit_thread()" stub with interrupts
turned off - accessing userland memory. Now, arch_thread_enter_userspace() does that
job, and as a result, may also fail.
* dump_thread() now directly prints the info of the current thread when used without
argument (rather than iterating the thread list to look for the current thread).
* If arch_thread_init_tls() fails upon thread creation, the function will now return
an error.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@19775 a95241bf-73f2-0310-859d-f6bbb57e9c96

Reverted my last change as it turned out that the lazy FPU state handling was not SMP safe afterall and the performance gain is questionable. Maybe it'll be implemented correctly in the future. Sorry for any inconvenience this may have cost.

git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@17272 a95241bf-73f2-0310-859d-f6bbb57e9c96

Implemented lazy FPU state save/restore. In the end mostly ported from NewOS. SMP safe.

git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@17251 a95241bf-73f2-0310-859d-f6bbb57e9c96

Implemented SSE2/3 support (tested with VLC).


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@16569 a95241bf-73f2-0310-859d-f6bbb57e9c96

The real_time_data structure contains an architecture specific
substructure now (that's the only member actually). The system time
offset is therefore accessed via architecture specific accessor
functions.
Note, that this commit breaks the PPC build. Since I want to rename at
least one file I've already changed, I can't avoid that.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@15835 a95241bf-73f2-0310-859d-f6bbb57e9c96

* Added some cpuid eax == 1 feature definitions to arch_cpu.h
* Renamed IA32_MTR_WRITE_COMBINED to IA32_MTR_WRITE_COMBINING.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@15559 a95241bf-73f2-0310-859d-f6bbb57e9c96

* We now support the global page feature of x86 processors that prevents
kernel TLBs from being flushed on context switch.
* new arch_cpu_user_TLB_invalidate() that now does what arch_cpu_global_TLB_invalidate()
did before.
* arch_cpu_global_TLB_invalidate() will now flush all TLBs, even those from the
kernel.
* some cleanups.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@15535 a95241bf-73f2-0310-859d-f6bbb57e9c96

The short story: we now have MTRR support on Intel and AMD CPUs (the latter
has not yet been tested, though - I'll do this after this commit):
* Removed the arch_memory_type stuff from vm_area; since there are only 8 memory
ranges on x86, it's simply overkill. The MTRR code now remembers the area ID
and finds the MTRR that way (it could also iterate over the existing MTRRs).
* Introduced some post_modules() init functions.
* If the other x86 CPUs out there don't differ a lot, MTRR functionality might
be put back into the kernel.
* x86_write_msr() was broken, it wrote the 64 bit number with the 32 bit words
switched - it took me some time (and lots of #GPs) to figure that one out.
* Removed the macro read_ebp() and introduced a function x86_read_ebp()
(it's not really a time critical call).
* Followed the Intel docs on how to change MTRRs (symmetrically on all CPUs
with caches turned off).
* Asking for memory types will automatically change the requested length to
a power of two - note that BeOS seems to behave in the same, although that's
not really very clean.
* fixed MTRRs are ignored for now - we should make sure at least, though,
that they are identical on all CPUs (or turn them off, even though I'd
prefer the BIOS stuff to be uncacheable, which we don't enforce yet, though).



git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@15528 a95241bf-73f2-0310-859d-f6bbb57e9c96

Added a wbinvd() macro.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@15526 a95241bf-73f2-0310-859d-f6bbb57e9c96

Some work in progress of the MTRR support. Shouldn't do any harm yet :-)


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@15525 a95241bf-73f2-0310-859d-f6bbb57e9c96

Preparation for MTRR support, code is completely untested, though.
The CPU specific MTRR code will be in modules.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@15520 a95241bf-73f2-0310-859d-f6bbb57e9c96

The "where" or "sc" command now switches the page directory to the specified thread
to be able to follow the stack trace into userland.
No symbols there, yet, though.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@14697 a95241bf-73f2-0310-859d-f6bbb57e9c96

Added calls to read and write the MSR, the machine state register.
Minor cleanup.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@14537 a95241bf-73f2-0310-859d-f6bbb57e9c96

Fixed double fault handler. Personally I disclaim all responsiblity
for these changes. I was mostly just staring in amazement at the screen
while Axel and Thomas were discussing IA32 internals. A particularly
fascinating moment was when Thomas produced the cause of a bug we had
been trying to track down for hours off the top of his head (of course
iret behaves specially when the NT bit is set :-). His slowness must be
excused though, since he hadn't slept for more then 30 hours. ;-)

The code doesn't wholeheartedly deal with multi-processor machines yet.
Axel will certainly do some cleanup...


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@12239 a95241bf-73f2-0310-859d-f6bbb57e9c96

Fixed struct tss; there is no ss3/sp3.
Moved ptentry/pdentry to arch_vm_translation_map.c and renamed them to
page_table_entry and page_directory_entry.
Fixed a race condition that happened when memory was remapped (which
can currently happen because lock_memory() does not work correctly, and
there might be other conditions as well, like certain vm_store fault
handlers). Now, page table and directory entries are updated atomically.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@12229 a95241bf-73f2-0310-859d-f6bbb57e9c96

* Made C++ save.
* Made the parameter for restoring the FPU state const.


git-svn-id: file:///srv/svn/repos/haiku/trunk/current@11522 a95241bf-73f2-0310-859d-f6bbb57e9c96

Added note to keep struct iframe in sync with the struct cpu_state.


git-svn-id: file:///srv/svn/repos/haiku/trunk/current@11471 a95241bf-73f2-0310-859d-f6bbb57e9c96

Incorporated some code from NewOS to set up a double fault handler.


git-svn-id: file:///srv/svn/repos/haiku/trunk/current@10444 a95241bf-73f2-0310-859d-f6bbb57e9c96

Removed unneeded includes of ktypes.h.


git-svn-id: file:///srv/svn/repos/haiku/trunk/current@10036 a95241bf-73f2-0310-859d-f6bbb57e9c96

Replaced all remaining PAGE_SIZE with B_PAGE_SIZE, addr with addr_t.
Removed the definition of PAGE_SIZE and addr.


git-svn-id: file:///srv/svn/repos/haiku/trunk/current@9433 a95241bf-73f2-0310-859d-f6bbb57e9c96

No longer needs the arch_thread.h header.


git-svn-id: file:///srv/svn/repos/haiku/trunk/current@9293 a95241bf-73f2-0310-859d-f6bbb57e9c96

Partially covered by arch_config.h and support/ByteOrder.h now/already.


git-svn-id: file:///srv/svn/repos/haiku/trunk/current@8900 a95241bf-73f2-0310-859d-f6bbb57e9c96

Introduced a macro specifying the type function parameters are aligned to. Not nice, but seems to help with the automatic generation of syscall code (at least on x86).


git-svn-id: file:///srv/svn/repos/haiku/trunk/current@8783 a95241bf-73f2-0310-859d-f6bbb57e9c96

fixed address checking in ppc atomic functions.
fixed compilation on x86.


git-svn-id: file:///srv/svn/repos/haiku/trunk/current@4361 a95241bf-73f2-0310-859d-f6bbb57e9c96

Put spaces between "::" in the asm directive to let it compile in C++ mode.


git-svn-id: file:///srv/svn/repos/haiku/trunk/current@3262 a95241bf-73f2-0310-859d-f6bbb57e9c96

Added another argument parameter for the thread creation code. Helps
implementing a more efficient on_exit_thread().


git-svn-id: file:///srv/svn/repos/haiku/trunk/current@3073 a95241bf-73f2-0310-859d-f6bbb57e9c96

Added a private tls.h file with definitions for the reserved TLS slots.
Renamed i386_set_kstack() to i386_set_tss_and_kstack(), because that's what
it does.
Added a new function arch_thread_init_tls() which must be called after
having allocated the TLS area.
Renamed arch_thread_initialize_kthread_stack() to arch_thread_init_kthread_stack()
to be more consistent.
Changed the parameters for arch_thread_enter_uspace() - it now gets a pointer
to the thread structure and takes the user stack pointer from there (which
might also be architectural different).


git-svn-id: file:///srv/svn/repos/haiku/trunk/current@2379 a95241bf-73f2-0310-859d-f6bbb57e9c96

Moved the gdt_idt_descr struct from arch_stage2.h to stage2_priv.h.
Moved the tss_descriptor structure to descriptor.h, updated it to be a
segment_descriptor structure, and provided inlines for set_tss_descriptor(),
set_segment_descriptor(), set_segment_descriptor_base(), and
clear_segment_descriptor().
Also added defines for the different privilege levels and descriptor types.
Removed the unusused and incorrect TSS definition, introduced new
TSS_BASE_SEGMENT and TLS_BASE_SEGMENT macros.
Removed include of arch/cpu.h in arch_cpu.h.


git-svn-id: file:///srv/svn/repos/haiku/trunk/current@2360 a95241bf-73f2-0310-859d-f6bbb57e9c96

posix signals support, 1st pass


git-svn-id: file:///srv/svn/repos/haiku/trunk/current@1623 a95241bf-73f2-0310-859d-f6bbb57e9c96

Backported the new stack crawl command ("sc", not "bt" like in NewOS) from
NewOS. Untested yet, though.


git-svn-id: file:///srv/svn/repos/haiku/trunk/current@750 a95241bf-73f2-0310-859d-f6bbb57e9c96

Ported my NewOS changes to OpenBeOS.

A couple of changes in various interrupt and thread functions and structures.
These make it now possible to change the stack at any time without making the kernel crash. This is needed for calling VESA 3.0 VBE functions through the protected mode interface.


git-svn-id: file:///srv/svn/repos/haiku/trunk/current@422 a95241bf-73f2-0310-859d-f6bbb57e9c96

It is accomplished ...


git-svn-id: file:///srv/svn/repos/haiku/trunk/current@10 a95241bf-73f2-0310-859d-f6bbb57e9c96

x86: added two MSR definitions.

kernel/x86_64: save fpu state at interrupts

The kernel is allowed to use fpu anywhere so we must make sure that
user state is not clobbered by saving fpu state at interrupt entry.
There is no need to do that in case of system calls since all fpu
data registers are caller saved.

We do not need, though, to save the whole fpu state at task swich
(again, thanks to calling convention). Only status and control
registers are preserved. This patch actually adds xmm0-15 register
to clobber list of task swich code, but the only reason of that is
to make sure that nothing bad happens inside the function that
executes that task swich. Inspection of the generated code shows
that no xmm registers are actually saved.

Signed-off-by: Paweł Dziepak <pdziepak@quarnos.org>

boot/x86_64: enable sse early

Enable SSE as a part of the "preparation of the environment to run any
C or C++ code" in the entry points of stage2 bootloader.

SSE2 is going to be used by memset() and memcpy().

Signed-off-by: Paweł Dziepak <pdziepak@quarnos.org>

kernel/x86[_64]: remove get_optimized_functions from cpu modules

The possibility to specify custom memcpy and memset implementations
in cpu modules is currently unused and there is generally no point
in such feature.

There are only 2 x86 vendors that really matter and there isn't
very big difference in performance of the generic optmized versions
of these funcions across different models. Even if we wanted different
versions of memset and memcpy depending on the processor model or
features much better solution would be to use STT_GNU_IFUNC and save
one indirect call.

Long story short, we don't really benefit in any way from
get_optimized_functions and the feature it implements and it only adds
unnecessary complexity to the code.

Signed-off-by: Paweł Dziepak <pdziepak@quarnos.org>

kernel/x86_64: implement x86_swap_pgdir in C++

No reason not to inline this function.

Signed-off-by: Paweł Dziepak <pdziepak@quarnos.org>

kernel/x86_64: inline x86_{read, write}_msr()

This patch makes it possible to inline rdmsr and wrmsr instruction. The
performance impact shouldn't be significant since they are used relatively
rarely and wrmsr is usually a serializing instruction, but there is no reason
not to do so.

kernel/x86_64: improve context switch implementation

The goal of this patch is to amortize the cost of context switch by making
the compiler aware that context switch clobbers all registers. Because all
register need to be saved anyway there is no additional cost of using
callee saved register in the function that does the context switch.

x86: Implement multicast ICIs

x86: Let each CPU have its own GDT

kernel: Reduce lock contention when processing ICIs

kernel: Rework cpuidle module

* Create new interface for cpuidle modules (similar to the cpufreq
interface)
* Generic cpuidle module is no longer needed
* Fix and update Intel C-State module

kernel: Make CACHE_LINE_ALIGN visible in the whole kernel

kernel: Add cpufreq module for Intel P-states

Since Sandy Bridge managing P-states on Intel processors is much easier
and more powerful than when using previous versions of EIST.

x86[_64]: Add CPU cache topology detection for AMD and Intel CPUs

Added x2APIC support.

* Mostly useful for virtualization at the moment. Works in QEmu.
* Can be enabled by safemode settings/menu.
* Please note that x2APIC normally requires use of VT-d interrupt remapping feature
on real hardware, which we don't support yet.

x86: enable data execution prevention

Set execute disable bit for any page that belongs to area with neither
B_EXECUTE_AREA nor B_KERNEL_EXECUTE_AREA set.

In order to take advanage of NX bit in 32 bit protected mode PAE must be
enabled. Thus, from now on it is also enabled when the CPU supports NX bit.

vm_page_fault() takes additional argument which indicates whether page fault
was caused by an illegal instruction fetch.

x86: Initialize IA32_MSR_ENERGY_PERF_BIAS

The lowest 4 bits of the MSR serves as a hint to the hardware to
favor performance or energy saving. 0 means a hint preference for
highest performance while 15 corresponds to the maximum energy
savings. A value of 7 translates into a hint to balance performance
with energy savings.

The default reset value of the MSR is 0. If BIOS doesn't intialize
the MSR, the hardware will run in performance state. This patch
initialize the MSR with value of 7 for balance between performance
and energy savings

Signed-off-by: Fredrik Holmqvist <fredrik.holmqvist@gmail.com>

Cleaner separation of 32-/64-bit specific CPU/interrupt code.

Renamed {32,64}/int.cpp to {32,64}/descriptors.cpp, which now contain
functions for GDT and TSS setup that were previously in arch_cpu.cpp,
as well as the IDT setup code. These get called from the init functions
in arch_cpu.cpp, rather than having a bunch of ifdef'd chunks of code
for 32/64.

Implemented user debugging support for x86_64.

Reused x86 arch_user_debugger.cpp, with a few minor changes to make
the code work for both 32 and 64 bit. Something isn't quite working
right, if a breakpoint is hit the kernel will hang. Other than that
everything appears to work correctly.

Initial userland support for x86_64.

Userland switch is implemented, as is basic system call support (using
SYSCALL/SYSRET). The system call handler is not yet complete: it doesn't
handle more than 6 arguments, and does not perform all the necessary kernel
entry/exit work (neither does the interrupt handler). However, this is
sufficient for runtime_loader to start and print some debug output.

Moved the exception handling functions to arch_int.cpp, shared between x86 and x86_64.

Moved the 32-bit page fault handler to arch_int.cpp, use it for x86_64.

A proper page fault handler was required for areas that were not locked
into the kernel address space. This enables the boot process to get
up to the point of trying to find the boot volume.

Implemented threading for x86_64.

* Thread creation and switching is working fine, however threads do not yet
get interrupted because I've not implemented hardware interrupt handling
yet (I'll do that next).
* I've made some changes to struct iframe: I've removed the e/r prefixes
from the member names for both 32/64, so now they're just named ip, ax,
bp, etc. This makes it easier to write code that works with both 32/64
without having to deal with different iframe member names.

Renamed remaining i386_* functions to x86_* for consistency.

Implemented system_time() for x86_64.

* Uses 64-bit multiplication, special handling for CPUs clocked < 1 GHz
in system_time_nsecs() not required like on x86.
* Tested against a straight conversion of the x86 version, noticably
faster with a large number of system_time() calls.

Added arch_cpu.cpp to the x86_64 build.

* Some things are currently ifndef'd out completely for x86_64 because
they aren't implemented, there's a few other ifdef's to handle x86_64
differences but most of the code works unchanged.
* Renamed some i386_* functions to x86_*.
* Added a temporary method for setting the current thread on x86_64
(a global variable, not SMP safe). This will be changed to be done
via the GS segment but I've not implemented that yet.

x86_{read,write}_cr{0,4} can just be implemented as macros, put an x86_ prefix on the other read/write macros for consistency.

Merged x86_64 headers into x86 headers.

Not many changes seeing as there's not much x86_64 stuff done yet. Small
differences are handled with ifdefs, large differences (descriptors.h,
struct iframe) have separate headers under arch/x86/32 and arch/x86/64.

Moved the common parts of arch_cpu.h between x86 and x86_64 to arch/common_x86/cpu.h.

x86: add cpuid feature 6 flags

Signed-off-by: Fredrik Holmqvist <fredrik.holmqvist@gmail.com>

x86: AMD C1E with no ARAT(Always Running APIC Timer) idle support

AMD C1E is a BIOS controlled C3 state. Certain processors families
may cut off TSC and the lapic timer when it is in a deep C state,
including C1E state, thus the cpu can't be waken up and system will hang.

This patch firstly adds the support of idle selection during boot. Then
it implements amdc1e_noarat_idle() routine which checks the MSR which
contains the C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27) before
executing the halt instruction, then clear them once set.

However intel C1E doesn't has such problem. AMD C1E is a BIOS controlled
C3 state. The difference between C1E and C3 is that transition into C1E
is not initiated by the operating system. System will enter C1E state
automatically when both cores enters C1 state. As for intel C1E, it
means "reduce CPU voltage before entering corresponding Cx-state".

This patch may fix #8111, #3999, #7562, #7940 and #8060

Copied from the description of #3999:
>but for some reason I hit the power button instead of the reset one. And
>the boot continued!!
The reason is CPUs are waken up once power button is hit.

Signed-off-by: Fredrik Holmqvist <fredrik.holmqvist@gmail.com>

x86: Change cpu feature flags to shifts

* No functional change
* Added missing ia64 emulation flag
* More closely matches AMD_EXT defines
* Easier to read compared to CPU documentation

kernel: x86 SSE improvements

* Prepend x86_ to non-static x86 code
* Add x86_init_fpu function to kernel header
* Don't init fpu multiple times on smp systems
* Verified fpu is still started on smp and non-smp
* SSE code still generates general protection faults
on smp systems though

kernel: Fix FPU SSE + MMX instruction usage.

* Rename init_sse to init_fpu and handle FPU setup.
* Stop trying to set up FPU before VM init.
We tried to set up the FPU before VM init, then
set it up again after VM init with SSE extensions,
this caused SSE and MMX applications to crash.
* Be more logical in FPU setup by detecting CPU flag prior
to enabling FPU. (it's unlikely Haiku will run on
a processor without a fpu... but lets be consistant)
* SSE2 gcc code now runs (faster even) without GPF
* tqh confirms his previously crashing mmx code now works
* The non-SSE FPU enable after VM init needs tested!

added more cpu feature flags for x86


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42263 a95241bf-73f2-0310-859d-f6bbb57e9c96

Merged signals-merge branch into trunk with the following changes:
* Reorganized the kernel locking related to threads and teams.
* We now discriminate correctly between process and thread signals. Signal
handlers have been moved to teams. Fixes #5679.
* Implemented real-time signal support, including signal queuing, SA_SIGINFO
support, sigqueue(), sigwaitinfo(), sigtimedwait(), waitid(), and the addition
of the real-time signal range. Closes #1935 and #2695.
* Gave SIGBUS a separate signal number. Fixes #6704.
* Implemented <time.h> clock and timer support, and fixed/completed alarm() and
[set]itimer(). Closes #5682.
* Implemented support for thread cancellation. Closes #5686.
* Moved send_signal() from <signal.h> to <OS.h>. Fixes #7554.
* Lots over smaller more or less related changes.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42116 a95241bf-73f2-0310-859d-f6bbb57e9c96

Definition for CR4 PAE bit.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@37073 a95241bf-73f2-0310-859d-f6bbb57e9c96

x86:
* Renamed i386_context_switch() to x86_context_switch().
* x86_context_switch() no longer sets the page directory.
arch_thread_context_switch() does that explicitly, now. This allows to solve
the TODO by reordering releasing the previous paging structures reference and
setting the new page directory.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@37024 a95241bf-73f2-0310-859d-f6bbb57e9c96

Renamed i386_swap_pgdir() to x86_swap_pgdir.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@37023 a95241bf-73f2-0310-859d-f6bbb57e9c96

x86:
* Renamed vm_translation_map_arch_info to X86PagingStructures, and all
members and local variables of that type accordingly.
* arch_thread_context_switch(): Added TODO: The still active paging structures
can indeed be deleted before we stop using them.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@37022 a95241bf-73f2-0310-859d-f6bbb57e9c96

* First run through the kernel's private parts to use phys_{addr,size}_t
where appropriate.
* Typedef'ed page_num_t to phys_addr_t and used it in more places in
vm_page.{h,cpp}.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@36937 a95241bf-73f2-0310-859d-f6bbb57e9c96

x86:
Added fields for temporary storage of the debug registers dr6 and dr7 to the
arch_cpu_info structure. The actual registers are stored at the beginning of
x86_exit_user_debug_at_kernel_entry() and read in
x86_handle_debug_exception().
The problem was that x86_exit_user_debug_at_kernel_entry() itself overwrote
dr7 and, if kernel breakpoints were enabled, dr6 could be overwritten anytime
after. So x86_handle_debug_exception() would find incorrect values in the
registers (definitely in dr7) and thus interpret the detected debug condition
incorrectly. Usually watchpoints were recognized as breakpoints.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@35951 a95241bf-73f2-0310-859d-f6bbb57e9c96

* map_physical_memory() does now always set a memory type. If none is given (it
needs to be or'ed to the address specification), "uncached" is assumed.
* Set the memory type for the "BIOS" and "DMA" areas to write-back. Not sure, if
that's correct, but that's what was effectively used on my machines before.
* Changed x86_set_mtrrs() and the CPU module hook to also set the default memory
type.
* Rewrote the MTRR computation once more:
- Now we know all used memory ranges, so we are free to extend used ranges
into unused ones in order to simplify them for MTRR setup.
- Leverage the subtractive properties of uncached and write-through ranges to
simplify ranges of any other respectively write-back type.
- Set the default memory type to write-back, so we don't need MTRRs for the
RAM ranges.
- If a new range intersects with an existing one, we no longer just fail.
Instead we use the strictest requirements implied by the ranges. This fixes
#5383.

Overall the new algorithm should be sufficient with far less MTRRs than before
(on my desktop machine 4 are used at maximum, while 8 didn't quite suffice
before). A drawback of the current implementation is that it doesn't deal with
the case of running out of MTRRs at all, which might result in some ranges
having weaker caching/memory ordering properties than requested.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@35515 a95241bf-73f2-0310-859d-f6bbb57e9c96

Removed unused <arch>_switch_stack_and_call() and
arch_thread_switch_kstack_and_call().


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@34971 a95241bf-73f2-0310-859d-f6bbb57e9c96

Added type nanotime_t (an int64 storing a nanoseconds value) and function
system_time_nsecs(), returning the system time in nanoseconds. The function
is only really implemented for x86. For the other architectures
system_time() * 1000 is returned.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@34543 a95241bf-73f2-0310-859d-f6bbb57e9c96

* Added a set_mtrrs() hook to x86_cpu_module_info, which is supposed to set
all MTRRs at once.
* Added a respective x86_set_mtrrs() kernel function.
* x86 CPU module:
- Implemented the new hook.
- Prefixed most debug output with the CPU index. Otherwise it gets quite
confusing with multiple CPUs.
- generic_init_mtrrs(): No longer clear all MTRRs, if they are already
enabled. This lets us benefit from the BIOS's setup until we install our
own -- otherwise with caching disabled things are *really* slow.
* arch_vm.cpp: Completely rewrote the MTRR handling as the old one was not
only slow (O(2^n)), but also broken (resulting in incorrect setups (e.g.
with cachable ranges larger than requested)), and not working by design for
certain cases (subtractive setups intersecting ranges added later).
Now we maintain an array with the successfully set ranges. When a new range
is added, we recompute the complete MTRR setup as we need to. The new
algorithm analyzing the ranges has linear complexity and also handles range
base addresses with an alignment not matching the range size (e.g. a range
at address 0x1000 with size 0x2000) and joining of adjacent/overlapping
ranges of the same type.

This fixes the slow graphics on my 4 GB machine (though unfortunately the
8 MTRRs aren't enough to fully cover the complete frame buffer (about 35
pixel lines remain uncachable), but that can't be helped without rounding up
the frame buffer size, for which we don't have enough information). It might
also fix #1823.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@34197 a95241bf-73f2-0310-859d-f6bbb57e9c96

* Coding style cleanup, no functional change.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@33792 a95241bf-73f2-0310-859d-f6bbb57e9c96

* Renamed the ROUNDOWN macro to ROUNDDOWN. Also changed the implementation of
ROUNDUP to use '*' and '/' -- the compiler will optimize that for powers of
two anyway and this implementation works for other numbers as well.
* The thread::fault_handler use in C[++] code was broken with gcc 4. At least
when other functions were invoked. Trying to trick the compiler wasn't a
particularly good idea anyway, since the next compiler version could break
the trick again. So the general policy is to use the fault handlers only in
assembly code where we have full control. Changed that for x86 (save for the
vm86 mode, which has a similar mechanism), but not for the other
architectures.
* Introduced fault_handler, fault_handler_stack_pointer, and fault_jump_buffer
fields in the cpu_ent structure, which must be used instead of
thread::fault_handler in the kernel debugger. Consequently user_memcpy() must
not be used in the kernel debugger either. Introduced a debug_memcpy()
instead.
* Introduced debug_call_with_fault_handler() function which calls a function
in a setjmp() and fault handler context. The architecture specific backend
arch_debug_call_with_fault_handler() has only been implemented for x86 yet.
* Introduced debug_is_kernel_memory_accessible() for use in the kernel
debugger. It determines whether a range of memory can be accessed in the
way specified. The architecture specific back end
arch_vm_translation_map_is_kernel_page_accessible() has only been implemented
for x86 yet.
* Added arch_debug_unset_current_thread() (only implemented for x86) to unset
the current thread pointer in the kernel debugger. When entering the kernel
debugger we do some basic sanity checks of the currently set thread structure
and unset it, if they fail. This allows certain commands (most importantly
the stack trace command) to avoid accessing the thread structure.
* x86: When handling a double fault, we do now install a special handler for
page faults. This allows us to gracefully catch faulting commands, even if
e.g. the thread structure is toast.

We are now in much better shape to deal with double faults. Hopefully avoiding
the triple faults that some people have been experiencing on their hardware
and ideally even allowing to use the kernel debugger normally.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@32073 a95241bf-73f2-0310-859d-f6bbb57e9c96

More work towards making our double fault handler less triple fault prone:
* SMP:
- Added smp_send_broadcast_ici_interrupts_disabled(), which is basically
equivalent to smp_send_broadcast_ici(), but is only called with interrupts
disabled and gets the CPU index, so it doesn't have to use
smp_get_current_cpu() (which dereferences the current thread).
- Added cpu index parameter to smp_intercpu_int_handler().
* x86:
- arch_int.c -> arch_int.cpp
- Set up an IDT per CPU. We were using a single IDT for all CPUs, but that
can't work, since we need different tasks for the double fault interrupt
vector.
- Set the per CPU double fault task gates correctly.
- Renamed set_intr_gate() to set_interrupt_gate and set_system_gate() to
set_trap_gate() and documented them a bit.
- Renamed double_fault_exception() x86_double_fault_exception() and fixed
it not to use smp_get_current_cpu(). Instead we have the new
x86_double_fault_get_cpu() that deducts the CPU index from the used stack.
- Fixed the double_fault interrupt handler: It no longer calls int_bottom to
avoid accessing the current thread.
* debug.cpp:
- Introduced explicit debug_double_fault() to enter the kernel debugger from
a double fault handler.
- Avoid using smp_get_current_cpu().
- Don't use kprintf() before sDebuggerOnCPU is set. Otherwise
acquire_spinlock() is invoked by arch_debug_serial_puts().

Things look a bit better when the current thread pointer is broken -- we run
into kernel_debugger_loop() and successfully print the "Welcome to KDL"
message -- but we still dereference the thread pointer afterwards, so that we
don't get a usable kernel debugger yet.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@32050 a95241bf-73f2-0310-859d-f6bbb57e9c96

* Allocate a separate double fault stack for each CPU.
* Added x86_double_fault_get_cpu(), a save way to get the CPU index when in
the double fault handler. smp_get_current_cpu() requires at least a somewhat
intact thread structure, so we rather want to avoid it when handling a double
fault. There are a lot more of those dependencies in the KDL entry code.
Working on it...


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@32028 a95241bf-73f2-0310-859d-f6bbb57e9c96

Synchronize the TSCs of all CPUs early in the boot process, so system_time()
will return consistent values. This helps with debug measurements for the time
being. Obviously we'll have to think of something different when we support
speed-stepping on models with frequency-dependent TSCs.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@30287 a95241bf-73f2-0310-859d-f6bbb57e9c96

When switching to a kernel thread we no longer set the page directory.
This is not necessary, since userland teams' page directories also
contain the kernel mappings, and avoids unnecessary TLB flushes. To make
that possible the vm_translation_map_arch_info objects are reference
counted now.

This optimization reduces the kernel time of the Haiku build on my
machine with SMP disabled a few percent, but interestingly the total
time decreases only marginally. Haven't tested with SMP yet, but for
full impact CPU affinity would be needed.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@28287 a95241bf-73f2-0310-859d-f6bbb57e9c96

Moved definition of the PAUSE macro to <cpu.h>, respectively
<arch/cpu.h>.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@28221 a95241bf-73f2-0310-859d-f6bbb57e9c96

* Implemented x86 assembly version of memset().
* memset() is now available through the commpage.
* CPU modules can provide a model-optimized memset().


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@27952 a95241bf-73f2-0310-859d-f6bbb57e9c96

* Added acpi_shutdown() method. If the ACPI bus manager is installed, this will
be used now. Tested only with VMware so far.
* apm_shutdown() is now called with interrupts turned on.
* Renamed arch_cpu.c to arch_cpu.cpp.
* Minor cleanup.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@27404 a95241bf-73f2-0310-859d-f6bbb57e9c96

Added comment.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@26806 a95241bf-73f2-0310-859d-f6bbb57e9c96

* Introduced x86_get_double_fault_stack(), which returns the address
and size of the double fault stack.
* is_kernel_stack_address() does now also check whether the given
address is on the double fault stack. This fixes stack traces on
double faults, which were broken (i.e. went only to the double fault
iframe) since we started checking whether the addresses are on the
kernel stack at all.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@26775 a95241bf-73f2-0310-859d-f6bbb57e9c96

* Removed the feature_string from the cpu_ent structure.
* Dumping the features as string is now a one time thing, that only happens
when DUMP_FEATURE_STRING is defined to 1.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@26733 a95241bf-73f2-0310-859d-f6bbb57e9c96

Last patch of the vm86 patch series from Jan Klötzke - thanks!:
* The new function vm86_do_int(struct vm86_state *state, uint8 vec) provides a
facility to call BIOS interupt handlers. The function must only be called from
a user thread context because the lower 1MB of the address space is used.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@25610 a95241bf-73f2-0310-859d-f6bbb57e9c96

Patch by Jan Klötzke:
* In vm86 mode CS will have arbitrary values so we check for both USER_CODE_SEG
and the VM flag in EFLAGS. This is also done when entering interrupt gates.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@25607 a95241bf-73f2-0310-859d-f6bbb57e9c96

- Added support in system info for extended cpu family and model.
- Take extended family and model into account when generating the cpu
type and revision.
- Added Intel Core 2 Extreme to the cpu list.

Please review.



git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@24509 a95241bf-73f2-0310-859d-f6bbb57e9c96

Merged branch haiku/branches/developer/bonefish/optimization revision
23139 into trunk, with roughly the following changes (for details svn
log the branch):
* The int 99 syscall handler is now fully in assembly.
* Added a sysenter/sysexit handler and use it on Pentiums that support
it (via commpage).
* Got rid of i386_handle_trap(). A bit of functionality was moved into
the assembly handler which now uses a jump table to call C functions
handling the respective interrupt.
* Some optimizations to get user debugger support code out of the
interrupt handling path.
* Introduced a thread::flags fields which allows to skip handling of
rare events (signals, user debug enabling/disabling) on the
common interrupt handling path.
* Got rid of the explicit iframe stack. The iframes can still be
retrieved by iterating through the stack frames.
* Made the commpage an architecture independent feature. It's used for
the real time data stuff (instead of creating a separate area).
* The x86 CPU modules can now provide processor optimized versions for
common functions (currently memcpy() only). They are used in the
kernel and are provided to the userland via commpage entries.
* Introduced build system feature allowing easy use of C structure
member offsets in assembly code.

Changes after merging:
* Fixed merge conflict in src/system/kernel/arch/x86/arch_debug.cpp
(caused by refactoring and introduction of "call" debugger command).



git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@23370 a95241bf-73f2-0310-859d-f6bbb57e9c96

clean up TSS initialization.

Now two complete tss structures exist within the per-cpu structure. Instead
of having to create a seperate area per each one, initialize them in place.
Also, the old mechanism to getting all of the cpus to get initialized was
subtly broken, but still managed to work. Now, just force all the cpus to
initialize at boot, which makes the actual swapping of esp0 somewhat simpler.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@20131 a95241bf-73f2-0310-859d-f6bbb57e9c96

pulled over some stuff from newos:
at boot, per cpu, detect the cpu, pull down all the relevant cpuid bits and
save them into the per-cpu structure. Changed most of the code scattered here
and there that reads the cpuid to use a new api, x86_check_feature, which looks
at the saved bits.
Also changed the system_info stuff to read from these bits.
While i was at it, refreshed all the bits to be current.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@20072 a95241bf-73f2-0310-859d-f6bbb57e9c96

Applied patch by Vasilis Kaoutsis: now checks for the MSR feature as well; obviously
some Pentium 200 MMX pretend to support MTRRs.
This should fix bug #553.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@19899 a95241bf-73f2-0310-859d-f6bbb57e9c96

Didn't notice that x86_enter_userspace() also copied the thread entry's arguments to
the userland stack in an unsafe way - moved that stuff to arch_thread_enter_userspace(), too.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@19778 a95241bf-73f2-0310-859d-f6bbb57e9c96

* There was no reason to copy the "userland calls exit_thread()" stub with interrupts
turned off - accessing userland memory. Now, arch_thread_enter_userspace() does that
job, and as a result, may also fail.
* dump_thread() now directly prints the info of the current thread when used without
argument (rather than iterating the thread list to look for the current thread).
* If arch_thread_init_tls() fails upon thread creation, the function will now return
an error.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@19775 a95241bf-73f2-0310-859d-f6bbb57e9c96

Reverted my last change as it turned out that the lazy FPU state handling was not SMP safe afterall and the performance gain is questionable. Maybe it'll be implemented correctly in the future. Sorry for any inconvenience this may have cost.

git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@17272 a95241bf-73f2-0310-859d-f6bbb57e9c96

Implemented lazy FPU state save/restore. In the end mostly ported from NewOS. SMP safe.

git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@17251 a95241bf-73f2-0310-859d-f6bbb57e9c96

Implemented SSE2/3 support (tested with VLC).


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@16569 a95241bf-73f2-0310-859d-f6bbb57e9c96

The real_time_data structure contains an architecture specific
substructure now (that's the only member actually). The system time
offset is therefore accessed via architecture specific accessor
functions.
Note, that this commit breaks the PPC build. Since I want to rename at
least one file I've already changed, I can't avoid that.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@15835 a95241bf-73f2-0310-859d-f6bbb57e9c96

* Added some cpuid eax == 1 feature definitions to arch_cpu.h
* Renamed IA32_MTR_WRITE_COMBINED to IA32_MTR_WRITE_COMBINING.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@15559 a95241bf-73f2-0310-859d-f6bbb57e9c96

* We now support the global page feature of x86 processors that prevents
kernel TLBs from being flushed on context switch.
* new arch_cpu_user_TLB_invalidate() that now does what arch_cpu_global_TLB_invalidate()
did before.
* arch_cpu_global_TLB_invalidate() will now flush all TLBs, even those from the
kernel.
* some cleanups.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@15535 a95241bf-73f2-0310-859d-f6bbb57e9c96

The short story: we now have MTRR support on Intel and AMD CPUs (the latter
has not yet been tested, though - I'll do this after this commit):
* Removed the arch_memory_type stuff from vm_area; since there are only 8 memory
ranges on x86, it's simply overkill. The MTRR code now remembers the area ID
and finds the MTRR that way (it could also iterate over the existing MTRRs).
* Introduced some post_modules() init functions.
* If the other x86 CPUs out there don't differ a lot, MTRR functionality might
be put back into the kernel.
* x86_write_msr() was broken, it wrote the 64 bit number with the 32 bit words
switched - it took me some time (and lots of #GPs) to figure that one out.
* Removed the macro read_ebp() and introduced a function x86_read_ebp()
(it's not really a time critical call).
* Followed the Intel docs on how to change MTRRs (symmetrically on all CPUs
with caches turned off).
* Asking for memory types will automatically change the requested length to
a power of two - note that BeOS seems to behave in the same, although that's
not really very clean.
* fixed MTRRs are ignored for now - we should make sure at least, though,
that they are identical on all CPUs (or turn them off, even though I'd
prefer the BIOS stuff to be uncacheable, which we don't enforce yet, though).



git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@15528 a95241bf-73f2-0310-859d-f6bbb57e9c96

Added a wbinvd() macro.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@15526 a95241bf-73f2-0310-859d-f6bbb57e9c96

Some work in progress of the MTRR support. Shouldn't do any harm yet :-)


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@15525 a95241bf-73f2-0310-859d-f6bbb57e9c96

Preparation for MTRR support, code is completely untested, though.
The CPU specific MTRR code will be in modules.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@15520 a95241bf-73f2-0310-859d-f6bbb57e9c96

The "where" or "sc" command now switches the page directory to the specified thread
to be able to follow the stack trace into userland.
No symbols there, yet, though.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@14697 a95241bf-73f2-0310-859d-f6bbb57e9c96

Added calls to read and write the MSR, the machine state register.
Minor cleanup.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@14537 a95241bf-73f2-0310-859d-f6bbb57e9c96

Fixed double fault handler. Personally I disclaim all responsiblity
for these changes. I was mostly just staring in amazement at the screen
while Axel and Thomas were discussing IA32 internals. A particularly
fascinating moment was when Thomas produced the cause of a bug we had
been trying to track down for hours off the top of his head (of course
iret behaves specially when the NT bit is set :-). His slowness must be
excused though, since he hadn't slept for more then 30 hours. ;-)

The code doesn't wholeheartedly deal with multi-processor machines yet.
Axel will certainly do some cleanup...


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@12239 a95241bf-73f2-0310-859d-f6bbb57e9c96

Fixed struct tss; there is no ss3/sp3.
Moved ptentry/pdentry to arch_vm_translation_map.c and renamed them to
page_table_entry and page_directory_entry.
Fixed a race condition that happened when memory was remapped (which
can currently happen because lock_memory() does not work correctly, and
there might be other conditions as well, like certain vm_store fault
handlers). Now, page table and directory entries are updated atomically.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@12229 a95241bf-73f2-0310-859d-f6bbb57e9c96

* Made C++ save.
* Made the parameter for restoring the FPU state const.


git-svn-id: file:///srv/svn/repos/haiku/trunk/current@11522 a95241bf-73f2-0310-859d-f6bbb57e9c96

Added note to keep struct iframe in sync with the struct cpu_state.


git-svn-id: file:///srv/svn/repos/haiku/trunk/current@11471 a95241bf-73f2-0310-859d-f6bbb57e9c96

Incorporated some code from NewOS to set up a double fault handler.


git-svn-id: file:///srv/svn/repos/haiku/trunk/current@10444 a95241bf-73f2-0310-859d-f6bbb57e9c96

Removed unneeded includes of ktypes.h.


git-svn-id: file:///srv/svn/repos/haiku/trunk/current@10036 a95241bf-73f2-0310-859d-f6bbb57e9c96

Replaced all remaining PAGE_SIZE with B_PAGE_SIZE, addr with addr_t.
Removed the definition of PAGE_SIZE and addr.


git-svn-id: file:///srv/svn/repos/haiku/trunk/current@9433 a95241bf-73f2-0310-859d-f6bbb57e9c96

No longer needs the arch_thread.h header.


git-svn-id: file:///srv/svn/repos/haiku/trunk/current@9293 a95241bf-73f2-0310-859d-f6bbb57e9c96

Partially covered by arch_config.h and support/ByteOrder.h now/already.


git-svn-id: file:///srv/svn/repos/haiku/trunk/current@8900 a95241bf-73f2-0310-859d-f6bbb57e9c96

Introduced a macro specifying the type function parameters are aligned to. Not nice, but seems to help with the automatic generation of syscall code (at least on x86).


git-svn-id: file:///srv/svn/repos/haiku/trunk/current@8783 a95241bf-73f2-0310-859d-f6bbb57e9c96

fixed address checking in ppc atomic functions.
fixed compilation on x86.


git-svn-id: file:///srv/svn/repos/haiku/trunk/current@4361 a95241bf-73f2-0310-859d-f6bbb57e9c96

Put spaces between "::" in the asm directive to let it compile in C++ mode.


git-svn-id: file:///srv/svn/repos/haiku/trunk/current@3262 a95241bf-73f2-0310-859d-f6bbb57e9c96

Added another argument parameter for the thread creation code. Helps
implementing a more efficient on_exit_thread().


git-svn-id: file:///srv/svn/repos/haiku/trunk/current@3073 a95241bf-73f2-0310-859d-f6bbb57e9c96

Added a private tls.h file with definitions for the reserved TLS slots.
Renamed i386_set_kstack() to i386_set_tss_and_kstack(), because that's what
it does.
Added a new function arch_thread_init_tls() which must be called after
having allocated the TLS area.
Renamed arch_thread_initialize_kthread_stack() to arch_thread_init_kthread_stack()
to be more consistent.
Changed the parameters for arch_thread_enter_uspace() - it now gets a pointer
to the thread structure and takes the user stack pointer from there (which
might also be architectural different).


git-svn-id: file:///srv/svn/repos/haiku/trunk/current@2379 a95241bf-73f2-0310-859d-f6bbb57e9c96

Moved the gdt_idt_descr struct from arch_stage2.h to stage2_priv.h.
Moved the tss_descriptor structure to descriptor.h, updated it to be a
segment_descriptor structure, and provided inlines for set_tss_descriptor(),
set_segment_descriptor(), set_segment_descriptor_base(), and
clear_segment_descriptor().
Also added defines for the different privilege levels and descriptor types.
Removed the unusused and incorrect TSS definition, introduced new
TSS_BASE_SEGMENT and TLS_BASE_SEGMENT macros.
Removed include of arch/cpu.h in arch_cpu.h.


git-svn-id: file:///srv/svn/repos/haiku/trunk/current@2360 a95241bf-73f2-0310-859d-f6bbb57e9c96

posix signals support, 1st pass


git-svn-id: file:///srv/svn/repos/haiku/trunk/current@1623 a95241bf-73f2-0310-859d-f6bbb57e9c96

Backported the new stack crawl command ("sc", not "bt" like in NewOS) from
NewOS. Untested yet, though.


git-svn-id: file:///srv/svn/repos/haiku/trunk/current@750 a95241bf-73f2-0310-859d-f6bbb57e9c96

Ported my NewOS changes to OpenBeOS.

A couple of changes in various interrupt and thread functions and structures.
These make it now possible to change the stack at any time without making the kernel crash. This is needed for calling VESA 3.0 VBE functions through the protected mode interface.


git-svn-id: file:///srv/svn/repos/haiku/trunk/current@422 a95241bf-73f2-0310-859d-f6bbb57e9c96

It is accomplished ...


git-svn-id: file:///srv/svn/repos/haiku/trunk/current@10 a95241bf-73f2-0310-859d-f6bbb57e9c96