| #
a312738b |
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25-Sep-2018 |
Eric Holland <hollande@google.com> |
[aml][clock] fix rate change/enable sequence
TEST: Tested on astro hardware (clkctl measure)
Change-Id: I6a223e0eef1cb728e772d3aabf7c91291e93b7d1
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| #
b0718eac |
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24-Sep-2018 |
John Bauman <jbauman@google.com> |
[dev][s905d2] Initialize PLL register 6
It's possible this is causing clock issues.
Test: boot astro
ZX-2612
Change-Id: Ia0ef321ce0b9b0db5e9a3c1c2900bc1b530f5849
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| #
a8cf34e0 |
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31-Aug-2018 |
John Bauman <jbauman@google.com> |
[dev][aml-gpu] Use GP0 for 846MHz on S905D2
Test: "clkctl measure" and vkcube_image_pipe_swapchain
ZX-2557 #done
Change-Id: Ib8a966f8a48fd32e2220e88585407f4cff8d3c06
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| #
6d8b47a0 |
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28-Aug-2018 |
Brijen Raval <braval@google.com> |
[amlogic][cpu-freq] Add CPU Freq. Scaling support
- Added support for configuring the dynamic mux
to generate frequencies less than 1GHz using MPLL.
- Cleanup and bug fixes in HIU PLL library.
Test: Used clkctl utility to verfiy freq. changes are
actually applied.
Change-Id: I9ef0da66c73b15814b566e5ab07a565ac08b875a
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| #
13f5cc60 |
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22-Aug-2018 |
Eric Holland <hollande@google.com> |
[aml][clock] Fix bit offset
TEST: Tested on astro hardware
Change-Id: Ic322571423b528fdfc7484ed13db52a69cffc839
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| #
bf92b657 |
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16-Aug-2018 |
Eric Holland <hollande@google.com> |
[aml][clocks] pll settings
Library for manipulation of Amlogic PLLs, all within the hiu block
of memory.
TEST: tested on Astro by changing audio clock frequencies via HIFI pll.
Change-Id: I0cbd5a4dbda50d445c7438282b009ad06c626199
|